5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
68 select GENERIC_ALLOCATOR
79 The Extended Industry Standard Architecture (EISA) bus was
80 developed as an open alternative to the IBM MicroChannel bus.
82 The EISA bus provided some of the features of the IBM MicroChannel
83 bus while maintaining backward compatibility with cards made for
84 the older ISA bus. The EISA bus saw limited use between 1988 and
85 1995 when it was made obsolete by the PCI bus.
87 Say Y here if you are building a kernel for an EISA-based machine.
97 MicroChannel Architecture is found in some IBM PS/2 machines and
98 laptops. It is a bus system similar to PCI or ISA. See
99 <file:Documentation/mca.txt> (and especially the web page given
100 there) before attempting to build an MCA bus kernel.
102 config STACKTRACE_SUPPORT
106 config HAVE_LATENCYTOP_SUPPORT
111 config LOCKDEP_SUPPORT
115 config TRACE_IRQFLAGS_SUPPORT
119 config HARDIRQS_SW_RESEND
123 config GENERIC_IRQ_PROBE
127 config GENERIC_LOCKBREAK
130 depends on SMP && PREEMPT
132 config RWSEM_GENERIC_SPINLOCK
136 config RWSEM_XCHGADD_ALGORITHM
139 config ARCH_HAS_ILOG2_U32
142 config ARCH_HAS_ILOG2_U64
145 config ARCH_HAS_CPUFREQ
148 Internal node to signify that the ARCH has CPUFREQ support
149 and that the relevant menu configurations are displayed for
152 config ARCH_HAS_CPU_IDLE_WAIT
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config GENERIC_ISA_DMA
181 config ARM_L1_CACHE_SHIFT_6
184 Setting ARM L1 cache line size to 64 Bytes.
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 source "init/Kconfig"
196 source "kernel/Kconfig.freezer"
201 bool "MMU-based Paged Memory Management Support"
204 Select if you want MMU-based virtualised addressing space
205 support by paged memory management. If unsure, say 'Y'.
208 # The "ARM system type" choice list is ordered alphabetically by option
209 # text. Please add new entries in the option alphabetic order.
212 prompt "ARM system type"
213 default ARCH_VERSATILE
216 bool "Agilent AAEC-2000 based"
220 select ARCH_USES_GETTIMEOFFSET
222 This enables support for systems based on the Agilent AAEC-2000
224 config ARCH_INTEGRATOR
225 bool "ARM Ltd. Integrator family"
227 select ARCH_HAS_CPUFREQ
230 select GENERIC_CLOCKEVENTS
231 select PLAT_VERSATILE
233 Support for ARM's Integrator platform.
236 bool "ARM Ltd. RealView family"
239 select HAVE_SCHED_CLOCK
241 select GENERIC_CLOCKEVENTS
242 select ARCH_WANT_OPTIONAL_GPIOLIB
243 select PLAT_VERSATILE
244 select ARM_TIMER_SP804
245 select GPIO_PL061 if GPIOLIB
247 This enables support for ARM Ltd RealView boards.
249 config ARCH_VERSATILE
250 bool "ARM Ltd. Versatile family"
254 select HAVE_SCHED_CLOCK
256 select GENERIC_CLOCKEVENTS
257 select ARCH_WANT_OPTIONAL_GPIOLIB
258 select PLAT_VERSATILE
259 select ARM_TIMER_SP804
261 This enables support for ARM Ltd Versatile board.
264 bool "ARM Ltd. Versatile Express family"
265 select ARCH_WANT_OPTIONAL_GPIOLIB
267 select ARM_TIMER_SP804
269 select GENERIC_CLOCKEVENTS
271 select HAVE_SCHED_CLOCK
273 select PLAT_VERSATILE
275 This enables support for the ARM Ltd Versatile Express boards.
279 select ARCH_REQUIRE_GPIOLIB
282 This enables support for systems based on the Atmel AT91RM9200,
283 AT91SAM9 and AT91CAP9 processors.
286 bool "Broadcom BCMRING"
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
294 Support for Broadcom's BCMRing platform.
297 bool "Cirrus Logic CLPS711x/EP721x-based"
299 select ARCH_USES_GETTIMEOFFSET
301 Support for Cirrus Logic 711x/721x based boards.
304 bool "Cavium Networks CNS3XXX family"
306 select GENERIC_CLOCKEVENTS
308 select MIGHT_HAVE_PCI
309 select PCI_DOMAINS if PCI
311 Support for Cavium Networks CNS3XXX platform.
314 bool "Cortina Systems Gemini"
316 select ARCH_REQUIRE_GPIOLIB
317 select ARCH_USES_GETTIMEOFFSET
319 Support for the Cortina Systems Gemini family SoCs
326 select ARCH_USES_GETTIMEOFFSET
328 This is an evaluation board for the StrongARM processor available
329 from Digital. It has limited hardware on-board, including an
330 Ethernet interface, two PCMCIA sockets, two serial ports and a
339 select ARCH_REQUIRE_GPIOLIB
340 select ARCH_HAS_HOLES_MEMORYMODEL
341 select ARCH_USES_GETTIMEOFFSET
343 This enables support for the Cirrus EP93xx series of CPUs.
345 config ARCH_FOOTBRIDGE
349 select ARCH_USES_GETTIMEOFFSET
351 Support for systems based on the DC21285 companion chip
352 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
355 bool "Freescale MXC/iMX-based"
356 select GENERIC_CLOCKEVENTS
357 select ARCH_REQUIRE_GPIOLIB
360 Support for Freescale MXC/iMX-based family of processors
363 bool "Freescale MXS-based"
364 select GENERIC_CLOCKEVENTS
365 select ARCH_REQUIRE_GPIOLIB
368 Support for Freescale MXS-based family of processors
371 bool "Freescale STMP3xxx"
374 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
376 select USB_ARCH_HAS_EHCI
378 Support for systems based on the Freescale 3xxx CPUs.
381 bool "Hilscher NetX based"
384 select GENERIC_CLOCKEVENTS
386 This enables support for systems based on the Hilscher NetX Soc
389 bool "Hynix HMS720x-based"
392 select ARCH_USES_GETTIMEOFFSET
394 This enables support for systems based on the Hynix HMS720x
402 select ARCH_SUPPORTS_MSI
405 Support for Intel's IOP13XX (XScale) family of processors.
413 select ARCH_REQUIRE_GPIOLIB
415 Support for Intel's 80219 and IOP32X (XScale) family of
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's IOP33X (XScale) family of processors.
433 select ARCH_USES_GETTIMEOFFSET
435 Support for Intel's IXP23xx (XScale) family of processors.
438 bool "IXP2400/2800-based"
442 select ARCH_USES_GETTIMEOFFSET
444 Support for Intel's IXP2400/2800 (XScale) family of processors.
451 select GENERIC_CLOCKEVENTS
452 select HAVE_SCHED_CLOCK
453 select MIGHT_HAVE_PCI
454 select DMABOUNCE if PCI
456 Support for Intel's IXP4XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
462 select GENERIC_CLOCKEVENTS
465 Support for the Marvell Dove SoC 88AP510
468 bool "Marvell Kirkwood"
471 select ARCH_REQUIRE_GPIOLIB
472 select GENERIC_CLOCKEVENTS
475 Support for the following Marvell Kirkwood series SoCs:
476 88F6180, 88F6192 and 88F6281.
479 bool "Marvell Loki (88RC8480)"
481 select GENERIC_CLOCKEVENTS
484 Support for the Marvell Loki (88RC8480) SoC.
489 select ARCH_REQUIRE_GPIOLIB
492 select USB_ARCH_HAS_OHCI
495 select GENERIC_CLOCKEVENTS
497 Support for the NXP LPC32XX family of processors
500 bool "Marvell MV78xx0"
503 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
507 Support for the following Marvell MV78xx0 series SoCs:
515 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
519 Support for the following Marvell Orion 5x series SoCs:
520 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
521 Orion-2 (5281), Orion-1-90 (6183).
524 bool "Marvell PXA168/910/MMP2"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select HAVE_SCHED_CLOCK
534 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
537 bool "Micrel/Kendin KS8695"
539 select ARCH_REQUIRE_GPIOLIB
540 select ARCH_USES_GETTIMEOFFSET
542 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
543 System-on-Chip devices.
546 bool "NetSilicon NS9xxx"
549 select GENERIC_CLOCKEVENTS
552 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
555 <http://www.digi.com/products/microprocessors/index.jsp>
558 bool "Nuvoton W90X900 CPU"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
565 At present, the w90x900 has been renamed nuc900, regarding
566 the ARM series product line, you can login the following
567 link address to know more.
569 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
570 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
573 bool "Nuvoton NUC93X CPU"
577 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
578 low-power and high performance MPEG-4/JPEG multimedia controller chip.
584 select GENERIC_CLOCKEVENTS
587 select HAVE_SCHED_CLOCK
588 select ARCH_HAS_BARRIERS if CACHE_L2X0
589 select ARCH_HAS_CPUFREQ
591 This enables support for NVIDIA Tegra based systems (Tegra APX,
592 Tegra 6xx and Tegra 2 series).
595 bool "Philips Nexperia PNX4008 Mobile"
598 select ARCH_USES_GETTIMEOFFSET
600 This enables support for Philips PNX4008 mobile platform.
603 bool "PXA2xx/PXA3xx-based"
606 select ARCH_HAS_CPUFREQ
608 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select HAVE_SCHED_CLOCK
615 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
620 select GENERIC_CLOCKEVENTS
621 select ARCH_REQUIRE_GPIOLIB
623 Support for Qualcomm MSM/QSD based systems. This runs on the
624 apps processor of the MSM/QSD and depends on a shared memory
625 interface to the modem processor which runs the baseband
626 stack and controls some vital subsystems
627 (clock and power control, etc).
630 bool "Renesas SH-Mobile / R-Mobile"
633 select GENERIC_CLOCKEVENTS
636 select MULTI_IRQ_HANDLER
638 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
645 select ARCH_MAY_HAVE_PC_FDC
646 select HAVE_PATA_PLATFORM
649 select ARCH_SPARSEMEM_ENABLE
650 select ARCH_USES_GETTIMEOFFSET
652 On the Acorn Risc-PC, Linux can support the internal IDE disk and
653 CD-ROM interface, serial and parallel port, and the floppy drive.
659 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_HAS_CPUFREQ
663 select GENERIC_CLOCKEVENTS
665 select HAVE_SCHED_CLOCK
667 select ARCH_REQUIRE_GPIOLIB
669 Support for StrongARM 11x0 based boards.
672 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
674 select ARCH_HAS_CPUFREQ
676 select ARCH_USES_GETTIMEOFFSET
677 select HAVE_S3C2410_I2C if I2C
679 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
680 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
681 the Samsung SMDK2410 development board (and derivatives).
683 Note, the S3C2416 and the S3C2450 are so close that they even share
684 the same SoC ID code. This means that there is no seperate machine
685 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
688 bool "Samsung S3C64XX"
694 select ARCH_USES_GETTIMEOFFSET
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
697 select SAMSUNG_CLKSRC
698 select SAMSUNG_IRQ_VIC_TIMER
699 select SAMSUNG_IRQ_UART
700 select S3C_GPIO_TRACK
701 select S3C_GPIO_PULL_UPDOWN
702 select S3C_GPIO_CFG_S3C24XX
703 select S3C_GPIO_CFG_S3C64XX
705 select USB_ARCH_HAS_OHCI
706 select SAMSUNG_GPIOLIB_4BIT
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 Samsung S3C64XX series based systems
713 bool "Samsung S5P6440 S5P6450"
717 select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 select ARCH_USES_GETTIMEOFFSET
719 select HAVE_S3C2410_I2C if I2C
720 select HAVE_S3C_RTC if RTC_CLASS
722 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
726 bool "Samsung S5P6442"
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 Samsung S5P6442 CPU based systems
736 bool "Samsung S5PC100"
740 select ARM_L1_CACHE_SHIFT_6
741 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_S3C2410_I2C if I2C
743 select HAVE_S3C_RTC if RTC_CLASS
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 Samsung S5PC100 series based systems
749 bool "Samsung S5PV210/S5PC110"
751 select ARCH_SPARSEMEM_ENABLE
754 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_HAS_CPUFREQ
756 select ARCH_USES_GETTIMEOFFSET
757 select HAVE_S3C2410_I2C if I2C
758 select HAVE_S3C_RTC if RTC_CLASS
759 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 Samsung S5PV210/S5PC110 series based systems
764 bool "Samsung S5PV310/S5PC210"
766 select ARCH_SPARSEMEM_ENABLE
769 select ARCH_HAS_CPUFREQ
770 select GENERIC_CLOCKEVENTS
771 select HAVE_S3C_RTC if RTC_CLASS
772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 Samsung S5PV310 series based systems
784 select ARCH_USES_GETTIMEOFFSET
786 Support for the StrongARM based Digital DNARD machine, also known
787 as "Shark" (<http://www.shark-linux.de/shark.html>).
790 bool "Telechips TCC ARM926-based systems"
794 select GENERIC_CLOCKEVENTS
796 Support for Telechips TCC ARM926-based systems.
801 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
802 select ARCH_USES_GETTIMEOFFSET
804 Say Y here for systems based on one of the Sharp LH7A40X
805 System on a Chip processors. These CPUs include an ARM922T
806 core with a wide array of integrated devices for
807 hand-held and low-power applications.
810 bool "ST-Ericsson U300 Series"
813 select HAVE_SCHED_CLOCK
817 select GENERIC_CLOCKEVENTS
821 Support for ST-Ericsson U300 series mobile platforms.
824 bool "ST-Ericsson U8500 Series"
827 select GENERIC_CLOCKEVENTS
829 select ARCH_REQUIRE_GPIOLIB
830 select ARCH_HAS_CPUFREQ
832 Support for ST-Ericsson's Ux500 architecture
835 bool "STMicroelectronics Nomadik"
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
843 Support for the Nomadik platform by ST-Ericsson
847 select GENERIC_CLOCKEVENTS
848 select ARCH_REQUIRE_GPIOLIB
852 select GENERIC_ALLOCATOR
853 select ARCH_HAS_HOLES_MEMORYMODEL
855 Support for TI's DaVinci platform.
860 select ARCH_REQUIRE_GPIOLIB
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_SCHED_CLOCK
864 select ARCH_HAS_HOLES_MEMORYMODEL
866 Support for TI's OMAP platform (OMAP1/2/3/4).
871 select ARCH_REQUIRE_GPIOLIB
873 select GENERIC_CLOCKEVENTS
876 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
881 # This is sorted alphabetically by mach-* pathname. However, plat-*
882 # Kconfigs may be included either alphabetically (according to the
883 # plat- suffix) or along side the corresponding mach-* source.
885 source "arch/arm/mach-aaec2000/Kconfig"
887 source "arch/arm/mach-at91/Kconfig"
889 source "arch/arm/mach-bcmring/Kconfig"
891 source "arch/arm/mach-clps711x/Kconfig"
893 source "arch/arm/mach-cns3xxx/Kconfig"
895 source "arch/arm/mach-davinci/Kconfig"
897 source "arch/arm/mach-dove/Kconfig"
899 source "arch/arm/mach-ep93xx/Kconfig"
901 source "arch/arm/mach-footbridge/Kconfig"
903 source "arch/arm/mach-gemini/Kconfig"
905 source "arch/arm/mach-h720x/Kconfig"
907 source "arch/arm/mach-integrator/Kconfig"
909 source "arch/arm/mach-iop32x/Kconfig"
911 source "arch/arm/mach-iop33x/Kconfig"
913 source "arch/arm/mach-iop13xx/Kconfig"
915 source "arch/arm/mach-ixp4xx/Kconfig"
917 source "arch/arm/mach-ixp2000/Kconfig"
919 source "arch/arm/mach-ixp23xx/Kconfig"
921 source "arch/arm/mach-kirkwood/Kconfig"
923 source "arch/arm/mach-ks8695/Kconfig"
925 source "arch/arm/mach-lh7a40x/Kconfig"
927 source "arch/arm/mach-loki/Kconfig"
929 source "arch/arm/mach-lpc32xx/Kconfig"
931 source "arch/arm/mach-msm/Kconfig"
933 source "arch/arm/mach-mv78xx0/Kconfig"
935 source "arch/arm/plat-mxc/Kconfig"
937 source "arch/arm/mach-mxs/Kconfig"
939 source "arch/arm/mach-netx/Kconfig"
941 source "arch/arm/mach-nomadik/Kconfig"
942 source "arch/arm/plat-nomadik/Kconfig"
944 source "arch/arm/mach-ns9xxx/Kconfig"
946 source "arch/arm/mach-nuc93x/Kconfig"
948 source "arch/arm/plat-omap/Kconfig"
950 source "arch/arm/mach-omap1/Kconfig"
952 source "arch/arm/mach-omap2/Kconfig"
954 source "arch/arm/mach-orion5x/Kconfig"
956 source "arch/arm/mach-pxa/Kconfig"
957 source "arch/arm/plat-pxa/Kconfig"
959 source "arch/arm/mach-mmp/Kconfig"
961 source "arch/arm/mach-realview/Kconfig"
963 source "arch/arm/mach-sa1100/Kconfig"
965 source "arch/arm/plat-samsung/Kconfig"
966 source "arch/arm/plat-s3c24xx/Kconfig"
967 source "arch/arm/plat-s5p/Kconfig"
969 source "arch/arm/plat-spear/Kconfig"
971 source "arch/arm/plat-tcc/Kconfig"
974 source "arch/arm/mach-s3c2400/Kconfig"
975 source "arch/arm/mach-s3c2410/Kconfig"
976 source "arch/arm/mach-s3c2412/Kconfig"
977 source "arch/arm/mach-s3c2416/Kconfig"
978 source "arch/arm/mach-s3c2440/Kconfig"
979 source "arch/arm/mach-s3c2443/Kconfig"
983 source "arch/arm/mach-s3c64xx/Kconfig"
986 source "arch/arm/mach-s5p64x0/Kconfig"
988 source "arch/arm/mach-s5p6442/Kconfig"
990 source "arch/arm/mach-s5pc100/Kconfig"
992 source "arch/arm/mach-s5pv210/Kconfig"
994 source "arch/arm/mach-s5pv310/Kconfig"
996 source "arch/arm/mach-shmobile/Kconfig"
998 source "arch/arm/plat-stmp3xxx/Kconfig"
1000 source "arch/arm/mach-tegra/Kconfig"
1002 source "arch/arm/mach-u300/Kconfig"
1004 source "arch/arm/mach-ux500/Kconfig"
1006 source "arch/arm/mach-versatile/Kconfig"
1008 source "arch/arm/mach-vexpress/Kconfig"
1010 source "arch/arm/mach-w90x900/Kconfig"
1012 # Definitions to make life easier
1018 select GENERIC_CLOCKEVENTS
1019 select HAVE_SCHED_CLOCK
1023 select HAVE_SCHED_CLOCK
1028 config PLAT_VERSATILE
1031 config ARM_TIMER_SP804
1034 source arch/arm/mm/Kconfig
1037 bool "Enable iWMMXt support"
1038 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1039 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1041 Enable support for iWMMXt context switching at run time if
1042 running on a CPU that supports it.
1044 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1047 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1051 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1052 (!ARCH_OMAP3 || OMAP3_EMU)
1056 config MULTI_IRQ_HANDLER
1059 Allow each machine to specify it's own IRQ handler at run time.
1062 source "arch/arm/Kconfig-nommu"
1065 config ARM_ERRATA_411920
1066 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1069 Invalidation of the Instruction Cache operation can
1070 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1071 It does not affect the MPCore. This option enables the ARM Ltd.
1072 recommended workaround.
1074 config ARM_ERRATA_430973
1075 bool "ARM errata: Stale prediction on replaced interworking branch"
1078 This option enables the workaround for the 430973 Cortex-A8
1079 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1080 interworking branch is replaced with another code sequence at the
1081 same virtual address, whether due to self-modifying code or virtual
1082 to physical address re-mapping, Cortex-A8 does not recover from the
1083 stale interworking branch prediction. This results in Cortex-A8
1084 executing the new code sequence in the incorrect ARM or Thumb state.
1085 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1086 and also flushes the branch target cache at every context switch.
1087 Note that setting specific bits in the ACTLR register may not be
1088 available in non-secure mode.
1090 config ARM_ERRATA_458693
1091 bool "ARM errata: Processor deadlock when a false hazard is created"
1094 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1095 erratum. For very specific sequences of memory operations, it is
1096 possible for a hazard condition intended for a cache line to instead
1097 be incorrectly associated with a different cache line. This false
1098 hazard might then cause a processor deadlock. The workaround enables
1099 the L1 caching of the NEON accesses and disables the PLD instruction
1100 in the ACTLR register. Note that setting specific bits in the ACTLR
1101 register may not be available in non-secure mode.
1103 config ARM_ERRATA_460075
1104 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1107 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1108 erratum. Any asynchronous access to the L2 cache may encounter a
1109 situation in which recent store transactions to the L2 cache are lost
1110 and overwritten with stale memory contents from external memory. The
1111 workaround disables the write-allocate mode for the L2 cache via the
1112 ACTLR register. Note that setting specific bits in the ACTLR register
1113 may not be available in non-secure mode.
1115 config ARM_ERRATA_742230
1116 bool "ARM errata: DMB operation may be faulty"
1117 depends on CPU_V7 && SMP
1119 This option enables the workaround for the 742230 Cortex-A9
1120 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1121 between two write operations may not ensure the correct visibility
1122 ordering of the two writes. This workaround sets a specific bit in
1123 the diagnostic register of the Cortex-A9 which causes the DMB
1124 instruction to behave as a DSB, ensuring the correct behaviour of
1127 config ARM_ERRATA_742231
1128 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1129 depends on CPU_V7 && SMP
1131 This option enables the workaround for the 742231 Cortex-A9
1132 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1133 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1134 accessing some data located in the same cache line, may get corrupted
1135 data due to bad handling of the address hazard when the line gets
1136 replaced from one of the CPUs at the same time as another CPU is
1137 accessing it. This workaround sets specific bits in the diagnostic
1138 register of the Cortex-A9 which reduces the linefill issuing
1139 capabilities of the processor.
1141 config PL310_ERRATA_588369
1142 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1143 depends on CACHE_L2X0 && ARCH_OMAP4
1145 The PL310 L2 cache controller implements three types of Clean &
1146 Invalidate maintenance operations: by Physical Address
1147 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1148 They are architecturally defined to behave as the execution of a
1149 clean operation followed immediately by an invalidate operation,
1150 both performing to the same memory location. This functionality
1151 is not correctly implemented in PL310 as clean lines are not
1152 invalidated as a result of these operations. Note that this errata
1153 uses Texas Instrument's secure monitor api.
1155 config ARM_ERRATA_720789
1156 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1157 depends on CPU_V7 && SMP
1159 This option enables the workaround for the 720789 Cortex-A9 (prior to
1160 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1161 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1162 As a consequence of this erratum, some TLB entries which should be
1163 invalidated are not, resulting in an incoherency in the system page
1164 tables. The workaround changes the TLB flushing routines to invalidate
1165 entries regardless of the ASID.
1167 config ARM_ERRATA_743622
1168 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1171 This option enables the workaround for the 743622 Cortex-A9
1172 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1173 optimisation in the Cortex-A9 Store Buffer may lead to data
1174 corruption. This workaround sets a specific bit in the diagnostic
1175 register of the Cortex-A9 which disables the Store Buffer
1176 optimisation, preventing the defect from occurring. This has no
1177 visible impact on the overall performance or power consumption of the
1180 config ARM_ERRATA_753970
1181 bool "ARM errata: cache sync operation may be faulty"
1182 depends on CACHE_PL310
1184 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1186 Under some condition the effect of cache sync operation on
1187 the store buffer still remains when the operation completes.
1188 This means that the store buffer is always asked to drain and
1189 this prevents it from merging any further writes. The workaround
1190 is to replace the normal offset of cache sync operation (0x730)
1191 by another offset targeting an unmapped PL310 register 0x740.
1192 This has the same effect as the cache sync operation: store buffer
1193 drain and waiting for all buffers empty.
1197 source "arch/arm/common/Kconfig"
1207 Find out whether you have ISA slots on your motherboard. ISA is the
1208 name of a bus system, i.e. the way the CPU talks to the other stuff
1209 inside your box. Other bus systems are PCI, EISA, MicroChannel
1210 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1211 newer boards don't support it. If you have ISA, say Y, otherwise N.
1213 # Select ISA DMA controller support
1218 # Select ISA DMA interface
1223 bool "PCI support" if MIGHT_HAVE_PCI
1225 Find out whether you have a PCI motherboard. PCI is the name of a
1226 bus system, i.e. the way the CPU talks to the other stuff inside
1227 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1228 VESA. If you have PCI, say Y, otherwise N.
1234 config PCI_NANOENGINE
1235 bool "BSE nanoEngine PCI support"
1236 depends on SA1100_NANOENGINE
1238 Enable PCI on the BSE nanoEngine board.
1243 # Select the host bridge type
1244 config PCI_HOST_VIA82C505
1246 depends on PCI && ARCH_SHARK
1249 config PCI_HOST_ITE8152
1251 depends on PCI && MACH_ARMCORE
1255 source "drivers/pci/Kconfig"
1257 source "drivers/pcmcia/Kconfig"
1261 menu "Kernel Features"
1263 source "kernel/time/Kconfig"
1266 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1267 depends on EXPERIMENTAL
1268 depends on GENERIC_CLOCKEVENTS
1269 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1270 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1271 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1272 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1273 select USE_GENERIC_SMP_HELPERS
1274 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1276 This enables support for systems with more than one CPU. If you have
1277 a system with only one CPU, like most personal computers, say N. If
1278 you have a system with more than one CPU, say Y.
1280 If you say N here, the kernel will run on single and multiprocessor
1281 machines, but will use only one CPU of a multiprocessor machine. If
1282 you say Y here, the kernel will run on many, but not all, single
1283 processor machines. On a single processor machine, the kernel will
1284 run faster if you say N here.
1286 See also <file:Documentation/i386/IO-APIC.txt>,
1287 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1288 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1290 If you don't know what to do here, say N.
1293 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1294 depends on EXPERIMENTAL
1295 depends on SMP && !XIP_KERNEL
1298 SMP kernels contain instructions which fail on non-SMP processors.
1299 Enabling this option allows the kernel to modify itself to make
1300 these instructions safe. Disabling it allows about 1K of space
1303 If you don't know what to do here, say Y.
1309 This option enables support for the ARM system coherency unit
1316 This options enables support for the ARM timer and watchdog unit
1319 prompt "Memory split"
1322 Select the desired split between kernel and user memory.
1324 If you are not absolutely sure what you are doing, leave this
1328 bool "3G/1G user/kernel split"
1330 bool "2G/2G user/kernel split"
1332 bool "1G/3G user/kernel split"
1337 default 0x40000000 if VMSPLIT_1G
1338 default 0x80000000 if VMSPLIT_2G
1342 int "Maximum number of CPUs (2-32)"
1348 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1349 depends on SMP && HOTPLUG && EXPERIMENTAL
1350 depends on !ARCH_MSM
1352 Say Y here to experiment with turning CPUs off and on. CPUs
1353 can be controlled through /sys/devices/system/cpu.
1356 bool "Use local timer interrupts"
1359 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1361 Enable support for local timers on SMP platforms, rather then the
1362 legacy IPI broadcast method. Local timers allows the system
1363 accounting to be spread across the timer interval, preventing a
1364 "thundering herd" at every timer tick.
1366 source kernel/Kconfig.preempt
1370 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1371 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1372 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1373 default AT91_TIMER_HZ if ARCH_AT91
1374 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1377 config THUMB2_KERNEL
1378 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1379 depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
1381 select ARM_ASM_UNIFIED
1383 By enabling this option, the kernel will be compiled in
1384 Thumb-2 mode. A compiler/assembler that understand the unified
1385 ARM-Thumb syntax is needed.
1389 config ARM_ASM_UNIFIED
1393 bool "Use the ARM EABI to compile the kernel"
1395 This option allows for the kernel to be compiled using the latest
1396 ARM ABI (aka EABI). This is only useful if you are using a user
1397 space environment that is also compiled with EABI.
1399 Since there are major incompatibilities between the legacy ABI and
1400 EABI, especially with regard to structure member alignment, this
1401 option also changes the kernel syscall calling convention to
1402 disambiguate both ABIs and allow for backward compatibility support
1403 (selected with CONFIG_OABI_COMPAT).
1405 To use this you need GCC version 4.0.0 or later.
1408 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1409 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1412 This option preserves the old syscall interface along with the
1413 new (ARM EABI) one. It also provides a compatibility layer to
1414 intercept syscalls that have structure arguments which layout
1415 in memory differs between the legacy ABI and the new ARM EABI
1416 (only for non "thumb" binaries). This option adds a tiny
1417 overhead to all syscalls and produces a slightly larger kernel.
1418 If you know you'll be using only pure EABI user space then you
1419 can say N here. If this option is not selected and you attempt
1420 to execute a legacy ABI binary then the result will be
1421 UNPREDICTABLE (in fact it can be predicted that it won't work
1422 at all). If in doubt say Y.
1424 config ARCH_HAS_HOLES_MEMORYMODEL
1427 config ARCH_SPARSEMEM_ENABLE
1430 config ARCH_SPARSEMEM_DEFAULT
1431 def_bool ARCH_SPARSEMEM_ENABLE
1433 config ARCH_SELECT_MEMORY_MODEL
1434 def_bool ARCH_SPARSEMEM_ENABLE
1437 bool "High Memory Support (EXPERIMENTAL)"
1438 depends on MMU && EXPERIMENTAL
1440 The address space of ARM processors is only 4 Gigabytes large
1441 and it has to accommodate user address space, kernel address
1442 space as well as some memory mapped IO. That means that, if you
1443 have a large amount of physical memory and/or IO, not all of the
1444 memory can be "permanently mapped" by the kernel. The physical
1445 memory that is not permanently mapped is called "high memory".
1447 Depending on the selected kernel/user memory split, minimum
1448 vmalloc space and actual amount of RAM, you may not need this
1449 option which should result in a slightly faster kernel.
1454 bool "Allocate 2nd-level pagetables from highmem"
1456 depends on !OUTER_CACHE
1458 config HW_PERF_EVENTS
1459 bool "Enable hardware performance counter support for perf events"
1460 depends on PERF_EVENTS && CPU_HAS_PMU
1463 Enable hardware performance counter support for perf events. If
1464 disabled, perf events will use software events only.
1468 config FORCE_MAX_ZONEORDER
1469 int "Maximum zone order" if ARCH_SHMOBILE
1470 range 11 64 if ARCH_SHMOBILE
1471 default "9" if SA1111
1474 The kernel memory allocator divides physically contiguous memory
1475 blocks into "zones", where each zone is a power of two number of
1476 pages. This option selects the largest power of two that the kernel
1477 keeps in the memory allocator. If you need to allocate very large
1478 blocks of physically contiguous memory, then you may need to
1479 increase this value.
1481 This config option is actually maximum order plus one. For example,
1482 a value of 11 means that the largest free memory block is 2^10 pages.
1485 bool "Timer and CPU usage LEDs"
1486 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1487 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1488 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1489 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1490 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1491 ARCH_AT91 || ARCH_DAVINCI || \
1492 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1494 If you say Y here, the LEDs on your machine will be used
1495 to provide useful information about your current system status.
1497 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1498 be able to select which LEDs are active using the options below. If
1499 you are compiling a kernel for the EBSA-110 or the LART however, the
1500 red LED will simply flash regularly to indicate that the system is
1501 still functional. It is safe to say Y here if you have a CATS
1502 system, but the driver will do nothing.
1505 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1506 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1507 || MACH_OMAP_PERSEUS2
1509 depends on !GENERIC_CLOCKEVENTS
1510 default y if ARCH_EBSA110
1512 If you say Y here, one of the system LEDs (the green one on the
1513 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1514 will flash regularly to indicate that the system is still
1515 operational. This is mainly useful to kernel hackers who are
1516 debugging unstable kernels.
1518 The LART uses the same LED for both Timer LED and CPU usage LED
1519 functions. You may choose to use both, but the Timer LED function
1520 will overrule the CPU usage LED.
1523 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1525 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1526 || MACH_OMAP_PERSEUS2
1529 If you say Y here, the red LED will be used to give a good real
1530 time indication of CPU usage, by lighting whenever the idle task
1531 is not currently executing.
1533 The LART uses the same LED for both Timer LED and CPU usage LED
1534 functions. You may choose to use both, but the Timer LED function
1535 will overrule the CPU usage LED.
1537 config ALIGNMENT_TRAP
1539 depends on CPU_CP15_MMU
1540 default y if !ARCH_EBSA110
1541 select HAVE_PROC_CPU if PROC_FS
1543 ARM processors cannot fetch/store information which is not
1544 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1545 address divisible by 4. On 32-bit ARM processors, these non-aligned
1546 fetch/store instructions will be emulated in software if you say
1547 here, which has a severe performance impact. This is necessary for
1548 correct operation of some network protocols. With an IP-only
1549 configuration it is safe to say N, otherwise say Y.
1551 config UACCESS_WITH_MEMCPY
1552 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1553 depends on MMU && EXPERIMENTAL
1554 default y if CPU_FEROCEON
1556 Implement faster copy_to_user and clear_user methods for CPU
1557 cores where a 8-word STM instruction give significantly higher
1558 memory write throughput than a sequence of individual 32bit stores.
1560 A possible side effect is a slight increase in scheduling latency
1561 between threads sharing the same address space if they invoke
1562 such copy operations with large buffers.
1564 However, if the CPU data cache is using a write-allocate mode,
1565 this option is unlikely to provide any performance gain.
1569 prompt "Enable seccomp to safely compute untrusted bytecode"
1571 This kernel feature is useful for number crunching applications
1572 that may need to compute untrusted bytecode during their
1573 execution. By using pipes or other transports made available to
1574 the process as file descriptors supporting the read/write
1575 syscalls, it's possible to isolate those applications in
1576 their own address space using seccomp. Once seccomp is
1577 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1578 and the task is only allowed to execute a few safe syscalls
1579 defined by each seccomp mode.
1581 config CC_STACKPROTECTOR
1582 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1583 depends on EXPERIMENTAL
1585 This option turns on the -fstack-protector GCC feature. This
1586 feature puts, at the beginning of functions, a canary value on
1587 the stack just before the return address, and validates
1588 the value just before actually returning. Stack based buffer
1589 overflows (that need to overwrite this return address) now also
1590 overwrite the canary, which gets detected and the attack is then
1591 neutralized via a kernel panic.
1592 This feature requires gcc version 4.2 or above.
1594 config DEPRECATED_PARAM_STRUCT
1595 bool "Provide old way to pass kernel parameters"
1597 This was deprecated in 2001 and announced to live on for 5 years.
1598 Some old boot loaders still use this way.
1604 # Compressed boot loader in ROM. Yes, we really want to ask about
1605 # TEXT and BSS so we preserve their values in the config files.
1606 config ZBOOT_ROM_TEXT
1607 hex "Compressed ROM boot loader base address"
1610 The physical address at which the ROM-able zImage is to be
1611 placed in the target. Platforms which normally make use of
1612 ROM-able zImage formats normally set this to a suitable
1613 value in their defconfig file.
1615 If ZBOOT_ROM is not enabled, this has no effect.
1617 config ZBOOT_ROM_BSS
1618 hex "Compressed ROM boot loader BSS address"
1621 The base address of an area of read/write memory in the target
1622 for the ROM-able zImage which must be available while the
1623 decompressor is running. It must be large enough to hold the
1624 entire decompressed kernel plus an additional 128 KiB.
1625 Platforms which normally make use of ROM-able zImage formats
1626 normally set this to a suitable value in their defconfig file.
1628 If ZBOOT_ROM is not enabled, this has no effect.
1631 bool "Compressed boot loader in ROM/flash"
1632 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1634 Say Y here if you intend to execute your compressed kernel image
1635 (zImage) directly from ROM or flash. If unsure, say N.
1638 string "Default kernel command string"
1641 On some architectures (EBSA110 and CATS), there is currently no way
1642 for the boot loader to pass arguments to the kernel. For these
1643 architectures, you should supply some command-line options at build
1644 time by entering them here. As a minimum, you should specify the
1645 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1647 config CMDLINE_FORCE
1648 bool "Always use the default kernel command string"
1649 depends on CMDLINE != ""
1651 Always use the default kernel command string, even if the boot
1652 loader passes other arguments to the kernel.
1653 This is useful if you cannot or don't want to change the
1654 command-line options your boot loader passes to the kernel.
1659 bool "Kernel Execute-In-Place from ROM"
1660 depends on !ZBOOT_ROM
1662 Execute-In-Place allows the kernel to run from non-volatile storage
1663 directly addressable by the CPU, such as NOR flash. This saves RAM
1664 space since the text section of the kernel is not loaded from flash
1665 to RAM. Read-write sections, such as the data section and stack,
1666 are still copied to RAM. The XIP kernel is not compressed since
1667 it has to run directly from flash, so it will take more space to
1668 store it. The flash address used to link the kernel object files,
1669 and for storing it, is configuration dependent. Therefore, if you
1670 say Y here, you must know the proper physical address where to
1671 store the kernel image depending on your own flash memory usage.
1673 Also note that the make target becomes "make xipImage" rather than
1674 "make zImage" or "make Image". The final kernel binary to put in
1675 ROM memory will be arch/arm/boot/xipImage.
1679 config XIP_PHYS_ADDR
1680 hex "XIP Kernel Physical Location"
1681 depends on XIP_KERNEL
1682 default "0x00080000"
1684 This is the physical address in your flash memory the kernel will
1685 be linked for and stored to. This address is dependent on your
1689 bool "Kexec system call (EXPERIMENTAL)"
1690 depends on EXPERIMENTAL
1692 kexec is a system call that implements the ability to shutdown your
1693 current kernel, and to start another kernel. It is like a reboot
1694 but it is independent of the system firmware. And like a reboot
1695 you can start any kernel with it, not just Linux.
1697 It is an ongoing process to be certain the hardware in a machine
1698 is properly shutdown, so do not be surprised if this code does not
1699 initially work for you. It may help to enable device hotplugging
1703 bool "Export atags in procfs"
1707 Should the atags used to boot the kernel be exported in an "atags"
1708 file in procfs. Useful with kexec.
1711 bool "Build kdump crash kernel (EXPERIMENTAL)"
1712 depends on EXPERIMENTAL
1714 Generate crash dump after being started by kexec. This should
1715 be normally only set in special crash dump kernels which are
1716 loaded in the main kernel with kexec-tools into a specially
1717 reserved region and then later executed after a crash by
1718 kdump/kexec. The crash dump kernel must be compiled to a
1719 memory address not used by the main kernel
1721 For more details see Documentation/kdump/kdump.txt
1723 config AUTO_ZRELADDR
1724 bool "Auto calculation of the decompressed kernel image address"
1725 depends on !ZBOOT_ROM && !ARCH_U300
1727 ZRELADDR is the physical address where the decompressed kernel
1728 image will be placed. If AUTO_ZRELADDR is selected, the address
1729 will be determined at run-time by masking the current IP with
1730 0xf8000000. This assumes the zImage being placed in the first 128MB
1731 from start of memory.
1735 menu "CPU Power Management"
1739 source "drivers/cpufreq/Kconfig"
1742 tristate "CPUfreq driver for i.MX CPUs"
1743 depends on ARCH_MXC && CPU_FREQ
1745 This enables the CPUfreq driver for i.MX CPUs.
1747 config CPU_FREQ_SA1100
1750 config CPU_FREQ_SA1110
1753 config CPU_FREQ_INTEGRATOR
1754 tristate "CPUfreq driver for ARM Integrator CPUs"
1755 depends on ARCH_INTEGRATOR && CPU_FREQ
1758 This enables the CPUfreq driver for ARM Integrator CPUs.
1760 For details, take a look at <file:Documentation/cpu-freq>.
1766 depends on CPU_FREQ && ARCH_PXA && PXA25x
1768 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1770 config CPU_FREQ_S3C64XX
1771 bool "CPUfreq support for Samsung S3C64XX CPUs"
1772 depends on CPU_FREQ && CPU_S3C6410
1777 Internal configuration node for common cpufreq on Samsung SoC
1779 config CPU_FREQ_S3C24XX
1780 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1781 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1784 This enables the CPUfreq driver for the Samsung S3C24XX family
1787 For details, take a look at <file:Documentation/cpu-freq>.
1791 config CPU_FREQ_S3C24XX_PLL
1792 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1793 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1795 Compile in support for changing the PLL frequency from the
1796 S3C24XX series CPUfreq driver. The PLL takes time to settle
1797 after a frequency change, so by default it is not enabled.
1799 This also means that the PLL tables for the selected CPU(s) will
1800 be built which may increase the size of the kernel image.
1802 config CPU_FREQ_S3C24XX_DEBUG
1803 bool "Debug CPUfreq Samsung driver core"
1804 depends on CPU_FREQ_S3C24XX
1806 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1808 config CPU_FREQ_S3C24XX_IODEBUG
1809 bool "Debug CPUfreq Samsung driver IO timing"
1810 depends on CPU_FREQ_S3C24XX
1812 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1814 config CPU_FREQ_S3C24XX_DEBUGFS
1815 bool "Export debugfs for CPUFreq"
1816 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1818 Export status information via debugfs.
1822 source "drivers/cpuidle/Kconfig"
1826 menu "Floating point emulation"
1828 comment "At least one emulation must be selected"
1831 bool "NWFPE math emulation"
1832 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1834 Say Y to include the NWFPE floating point emulator in the kernel.
1835 This is necessary to run most binaries. Linux does not currently
1836 support floating point hardware so you need to say Y here even if
1837 your machine has an FPA or floating point co-processor podule.
1839 You may say N here if you are going to load the Acorn FPEmulator
1840 early in the bootup.
1843 bool "Support extended precision"
1844 depends on FPE_NWFPE
1846 Say Y to include 80-bit support in the kernel floating-point
1847 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1848 Note that gcc does not generate 80-bit operations by default,
1849 so in most cases this option only enlarges the size of the
1850 floating point emulator without any good reason.
1852 You almost surely want to say N here.
1855 bool "FastFPE math emulation (EXPERIMENTAL)"
1856 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1858 Say Y here to include the FAST floating point emulator in the kernel.
1859 This is an experimental much faster emulator which now also has full
1860 precision for the mantissa. It does not support any exceptions.
1861 It is very simple, and approximately 3-6 times faster than NWFPE.
1863 It should be sufficient for most programs. It may be not suitable
1864 for scientific calculations, but you have to check this for yourself.
1865 If you do not feel you need a faster FP emulation you should better
1869 bool "VFP-format floating point maths"
1870 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1872 Say Y to include VFP support code in the kernel. This is needed
1873 if your hardware includes a VFP unit.
1875 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1876 release notes and additional status information.
1878 Say N if your target does not have VFP hardware.
1886 bool "Advanced SIMD (NEON) Extension support"
1887 depends on VFPv3 && CPU_V7
1889 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1894 menu "Userspace binary formats"
1896 source "fs/Kconfig.binfmt"
1899 tristate "RISC OS personality"
1902 Say Y here to include the kernel code necessary if you want to run
1903 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1904 experimental; if this sounds frightening, say N and sleep in peace.
1905 You can also say M here to compile this support as a module (which
1906 will be called arthur).
1910 menu "Power management options"
1912 source "kernel/power/Kconfig"
1914 config ARCH_SUSPEND_POSSIBLE
1919 source "net/Kconfig"
1921 source "drivers/Kconfig"
1925 source "arch/arm/Kconfig.debug"
1927 source "security/Kconfig"
1929 source "crypto/Kconfig"
1931 source "lib/Kconfig"