5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 Support for Broadcom's BCMRing platform.
331 bool "Cirrus Logic CLPS711x/EP721x-based"
333 select ARCH_USES_GETTIMEOFFSET
335 Support for Cirrus Logic 711x/721x based boards.
338 bool "Cavium Networks CNS3XXX family"
340 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select PCI_DOMAINS if PCI
344 select NO_MACH_MEMORY_H
346 Support for Cavium Networks CNS3XXX platform.
349 bool "Cortina Systems Gemini"
351 select ARCH_REQUIRE_GPIOLIB
352 select ARCH_USES_GETTIMEOFFSET
353 select NO_MACH_MEMORY_H
355 Support for the Cortina Systems Gemini family SoCs
358 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
362 select GENERIC_CLOCKEVENTS
364 select GENERIC_IRQ_CHIP
368 Support for CSR SiRFSoC ARM Cortex A9 Platform
375 select ARCH_USES_GETTIMEOFFSET
377 This is an evaluation board for the StrongARM processor available
378 from Digital. It has limited hardware on-board, including an
379 Ethernet interface, two PCMCIA sockets, two serial ports and a
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_HAS_HOLES_MEMORYMODEL
390 select ARCH_USES_GETTIMEOFFSET
392 This enables support for the Cirrus EP93xx series of CPUs.
394 config ARCH_FOOTBRIDGE
398 select GENERIC_CLOCKEVENTS
400 Support for systems based on the DC21285 companion chip
401 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
404 bool "Freescale MXC/iMX-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
409 select GENERIC_IRQ_CHIP
410 select HAVE_SCHED_CLOCK
412 Support for Freescale MXC/iMX-based family of processors
415 bool "Freescale MXS-based"
416 select GENERIC_CLOCKEVENTS
417 select ARCH_REQUIRE_GPIOLIB
420 select NO_MACH_MEMORY_H
422 Support for Freescale MXS-based family of processors
425 bool "Hilscher NetX based"
429 select GENERIC_CLOCKEVENTS
430 select NO_MACH_MEMORY_H
432 This enables support for systems based on the Hilscher NetX Soc
435 bool "Hynix HMS720x-based"
438 select ARCH_USES_GETTIMEOFFSET
440 This enables support for systems based on the Hynix HMS720x
448 select ARCH_SUPPORTS_MSI
451 Support for Intel's IOP13XX (XScale) family of processors.
459 select ARCH_REQUIRE_GPIOLIB
460 select NO_MACH_MEMORY_H
462 Support for Intel's 80219 and IOP32X (XScale) family of
471 select ARCH_REQUIRE_GPIOLIB
472 select NO_MACH_MEMORY_H
474 Support for Intel's IOP33X (XScale) family of processors.
481 select ARCH_USES_GETTIMEOFFSET
483 Support for Intel's IXP23xx (XScale) family of processors.
486 bool "IXP2400/2800-based"
490 select ARCH_USES_GETTIMEOFFSET
492 Support for Intel's IXP2400/2800 (XScale) family of processors.
500 select GENERIC_CLOCKEVENTS
501 select HAVE_SCHED_CLOCK
502 select MIGHT_HAVE_PCI
503 select DMABOUNCE if PCI
505 Support for Intel's IXP4XX (XScale) family of processors.
511 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
514 select NO_MACH_MEMORY_H
516 Support for the Marvell Dove SoC 88AP510
519 bool "Marvell Kirkwood"
522 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
525 select NO_MACH_MEMORY_H
527 Support for the following Marvell Kirkwood series SoCs:
528 88F6180, 88F6192 and 88F6281.
534 select ARCH_REQUIRE_GPIOLIB
537 select USB_ARCH_HAS_OHCI
540 select GENERIC_CLOCKEVENTS
541 select NO_MACH_MEMORY_H
543 Support for the NXP LPC32XX family of processors
546 bool "Marvell MV78xx0"
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
552 select NO_MACH_MEMORY_H
554 Support for the following Marvell MV78xx0 series SoCs:
562 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
565 select NO_MACH_MEMORY_H
567 Support for the following Marvell Orion 5x series SoCs:
568 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
569 Orion-2 (5281), Orion-1-90 (6183).
572 bool "Marvell PXA168/910/MMP2"
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select HAVE_SCHED_CLOCK
581 select NO_MACH_MEMORY_H
583 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
586 bool "Micrel/Kendin KS8695"
588 select ARCH_REQUIRE_GPIOLIB
589 select ARCH_USES_GETTIMEOFFSET
591 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
592 System-on-Chip devices.
595 bool "Nuvoton W90X900 CPU"
597 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
601 select NO_MACH_MEMORY_H
603 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
604 At present, the w90x900 has been renamed nuc900, regarding
605 the ARM series product line, you can login the following
606 link address to know more.
608 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
609 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
612 bool "Nuvoton NUC93X CPU"
615 select NO_MACH_MEMORY_H
617 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
618 low-power and high performance MPEG-4/JPEG multimedia controller chip.
625 select GENERIC_CLOCKEVENTS
628 select HAVE_SCHED_CLOCK
629 select ARCH_HAS_CPUFREQ
631 This enables support for NVIDIA Tegra based systems (Tegra APX,
632 Tegra 6xx and Tegra 2 series).
635 bool "Philips Nexperia PNX4008 Mobile"
638 select ARCH_USES_GETTIMEOFFSET
639 select NO_MACH_MEMORY_H
641 This enables support for Philips PNX4008 mobile platform.
644 bool "PXA2xx/PXA3xx-based"
647 select ARCH_HAS_CPUFREQ
650 select ARCH_REQUIRE_GPIOLIB
651 select GENERIC_CLOCKEVENTS
652 select HAVE_SCHED_CLOCK
657 select MULTI_IRQ_HANDLER
659 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
664 select GENERIC_CLOCKEVENTS
665 select ARCH_REQUIRE_GPIOLIB
667 select NO_MACH_MEMORY_H
669 Support for Qualcomm MSM/QSD based systems. This runs on the
670 apps processor of the MSM/QSD and depends on a shared memory
671 interface to the modem processor which runs the baseband
672 stack and controls some vital subsystems
673 (clock and power control, etc).
676 bool "Renesas SH-Mobile / R-Mobile"
679 select HAVE_MACH_CLKDEV
680 select GENERIC_CLOCKEVENTS
683 select MULTI_IRQ_HANDLER
684 select PM_GENERIC_DOMAINS if PM
686 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
693 select ARCH_MAY_HAVE_PC_FDC
694 select HAVE_PATA_PLATFORM
697 select ARCH_SPARSEMEM_ENABLE
698 select ARCH_USES_GETTIMEOFFSET
700 On the Acorn Risc-PC, Linux can support the internal IDE disk and
701 CD-ROM interface, serial and parallel port, and the floppy drive.
708 select ARCH_SPARSEMEM_ENABLE
710 select ARCH_HAS_CPUFREQ
712 select GENERIC_CLOCKEVENTS
714 select HAVE_SCHED_CLOCK
716 select ARCH_REQUIRE_GPIOLIB
718 Support for StrongARM 11x0 based boards.
721 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
723 select ARCH_HAS_CPUFREQ
726 select ARCH_USES_GETTIMEOFFSET
727 select HAVE_S3C2410_I2C if I2C
728 select NO_MACH_MEMORY_H
730 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
731 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
732 the Samsung SMDK2410 development board (and derivatives).
734 Note, the S3C2416 and the S3C2450 are so close that they even share
735 the same SoC ID code. This means that there is no separate machine
736 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
739 bool "Samsung S3C64XX"
746 select ARCH_USES_GETTIMEOFFSET
747 select ARCH_HAS_CPUFREQ
748 select ARCH_REQUIRE_GPIOLIB
749 select SAMSUNG_CLKSRC
750 select SAMSUNG_IRQ_VIC_TIMER
751 select SAMSUNG_IRQ_UART
752 select S3C_GPIO_TRACK
753 select S3C_GPIO_PULL_UPDOWN
754 select S3C_GPIO_CFG_S3C24XX
755 select S3C_GPIO_CFG_S3C64XX
757 select USB_ARCH_HAS_OHCI
758 select SAMSUNG_GPIOLIB_4BIT
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 Samsung S3C64XX series based systems
765 bool "Samsung S5P6440 S5P6450"
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select GENERIC_CLOCKEVENTS
773 select HAVE_SCHED_CLOCK
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C_RTC if RTC_CLASS
777 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
781 bool "Samsung S5PC100"
786 select ARM_L1_CACHE_SHIFT_6
787 select ARCH_USES_GETTIMEOFFSET
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C_RTC if RTC_CLASS
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 Samsung S5PC100 series based systems
795 bool "Samsung S5PV210/S5PC110"
797 select ARCH_SPARSEMEM_ENABLE
798 select ARCH_HAS_HOLES_MEMORYMODEL
803 select ARM_L1_CACHE_SHIFT_6
804 select ARCH_HAS_CPUFREQ
805 select GENERIC_CLOCKEVENTS
806 select HAVE_SCHED_CLOCK
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C_RTC if RTC_CLASS
809 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 Samsung S5PV210/S5PC110 series based systems
814 bool "Samsung EXYNOS4"
816 select ARCH_SPARSEMEM_ENABLE
817 select ARCH_HAS_HOLES_MEMORYMODEL
821 select ARCH_HAS_CPUFREQ
822 select GENERIC_CLOCKEVENTS
823 select HAVE_S3C_RTC if RTC_CLASS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 Samsung EXYNOS4 series based systems
836 select ARCH_USES_GETTIMEOFFSET
838 Support for the StrongARM based Digital DNARD machine, also known
839 as "Shark" (<http://www.shark-linux.de/shark.html>).
842 bool "Telechips TCC ARM926-based systems"
847 select GENERIC_CLOCKEVENTS
848 select NO_MACH_MEMORY_H
850 Support for Telechips TCC ARM926-based systems.
853 bool "ST-Ericsson U300 Series"
857 select HAVE_SCHED_CLOCK
861 select GENERIC_CLOCKEVENTS
863 select HAVE_MACH_CLKDEV
866 Support for ST-Ericsson U300 series mobile platforms.
869 bool "ST-Ericsson U8500 Series"
872 select GENERIC_CLOCKEVENTS
874 select ARCH_REQUIRE_GPIOLIB
875 select ARCH_HAS_CPUFREQ
876 select NO_MACH_MEMORY_H
878 Support for ST-Ericsson's Ux500 architecture
881 bool "STMicroelectronics Nomadik"
886 select GENERIC_CLOCKEVENTS
887 select ARCH_REQUIRE_GPIOLIB
888 select NO_MACH_MEMORY_H
890 Support for the Nomadik platform by ST-Ericsson
894 select GENERIC_CLOCKEVENTS
895 select ARCH_REQUIRE_GPIOLIB
899 select GENERIC_ALLOCATOR
900 select GENERIC_IRQ_CHIP
901 select ARCH_HAS_HOLES_MEMORYMODEL
903 Support for TI's DaVinci platform.
908 select ARCH_REQUIRE_GPIOLIB
909 select ARCH_HAS_CPUFREQ
911 select GENERIC_CLOCKEVENTS
912 select HAVE_SCHED_CLOCK
913 select ARCH_HAS_HOLES_MEMORYMODEL
915 Support for TI's OMAP platform (OMAP1/2/3/4).
920 select ARCH_REQUIRE_GPIOLIB
923 select GENERIC_CLOCKEVENTS
925 select NO_MACH_MEMORY_H
927 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
930 bool "VIA/WonderMedia 85xx"
933 select ARCH_HAS_CPUFREQ
934 select GENERIC_CLOCKEVENTS
935 select ARCH_REQUIRE_GPIOLIB
938 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
941 bool "Xilinx Zynq ARM Cortex A9 Platform"
944 select GENERIC_CLOCKEVENTS
951 Support for Xilinx Zynq ARM Cortex A9 Platform
955 # This is sorted alphabetically by mach-* pathname. However, plat-*
956 # Kconfigs may be included either alphabetically (according to the
957 # plat- suffix) or along side the corresponding mach-* source.
959 source "arch/arm/mach-at91/Kconfig"
961 source "arch/arm/mach-bcmring/Kconfig"
963 source "arch/arm/mach-clps711x/Kconfig"
965 source "arch/arm/mach-cns3xxx/Kconfig"
967 source "arch/arm/mach-davinci/Kconfig"
969 source "arch/arm/mach-dove/Kconfig"
971 source "arch/arm/mach-ep93xx/Kconfig"
973 source "arch/arm/mach-footbridge/Kconfig"
975 source "arch/arm/mach-gemini/Kconfig"
977 source "arch/arm/mach-h720x/Kconfig"
979 source "arch/arm/mach-integrator/Kconfig"
981 source "arch/arm/mach-iop32x/Kconfig"
983 source "arch/arm/mach-iop33x/Kconfig"
985 source "arch/arm/mach-iop13xx/Kconfig"
987 source "arch/arm/mach-ixp4xx/Kconfig"
989 source "arch/arm/mach-ixp2000/Kconfig"
991 source "arch/arm/mach-ixp23xx/Kconfig"
993 source "arch/arm/mach-kirkwood/Kconfig"
995 source "arch/arm/mach-ks8695/Kconfig"
997 source "arch/arm/mach-lpc32xx/Kconfig"
999 source "arch/arm/mach-msm/Kconfig"
1001 source "arch/arm/mach-mv78xx0/Kconfig"
1003 source "arch/arm/plat-mxc/Kconfig"
1005 source "arch/arm/mach-mxs/Kconfig"
1007 source "arch/arm/mach-netx/Kconfig"
1009 source "arch/arm/mach-nomadik/Kconfig"
1010 source "arch/arm/plat-nomadik/Kconfig"
1012 source "arch/arm/mach-nuc93x/Kconfig"
1014 source "arch/arm/plat-omap/Kconfig"
1016 source "arch/arm/mach-omap1/Kconfig"
1018 source "arch/arm/mach-omap2/Kconfig"
1020 source "arch/arm/mach-orion5x/Kconfig"
1022 source "arch/arm/mach-pxa/Kconfig"
1023 source "arch/arm/plat-pxa/Kconfig"
1025 source "arch/arm/mach-mmp/Kconfig"
1027 source "arch/arm/mach-realview/Kconfig"
1029 source "arch/arm/mach-sa1100/Kconfig"
1031 source "arch/arm/plat-samsung/Kconfig"
1032 source "arch/arm/plat-s3c24xx/Kconfig"
1033 source "arch/arm/plat-s5p/Kconfig"
1035 source "arch/arm/plat-spear/Kconfig"
1037 source "arch/arm/plat-tcc/Kconfig"
1040 source "arch/arm/mach-s3c2410/Kconfig"
1041 source "arch/arm/mach-s3c2412/Kconfig"
1042 source "arch/arm/mach-s3c2416/Kconfig"
1043 source "arch/arm/mach-s3c2440/Kconfig"
1044 source "arch/arm/mach-s3c2443/Kconfig"
1048 source "arch/arm/mach-s3c64xx/Kconfig"
1051 source "arch/arm/mach-s5p64x0/Kconfig"
1053 source "arch/arm/mach-s5pc100/Kconfig"
1055 source "arch/arm/mach-s5pv210/Kconfig"
1057 source "arch/arm/mach-exynos4/Kconfig"
1059 source "arch/arm/mach-shmobile/Kconfig"
1061 source "arch/arm/mach-tegra/Kconfig"
1063 source "arch/arm/mach-u300/Kconfig"
1065 source "arch/arm/mach-ux500/Kconfig"
1067 source "arch/arm/mach-versatile/Kconfig"
1069 source "arch/arm/mach-vexpress/Kconfig"
1070 source "arch/arm/plat-versatile/Kconfig"
1072 source "arch/arm/mach-vt8500/Kconfig"
1074 source "arch/arm/mach-w90x900/Kconfig"
1076 # Definitions to make life easier
1082 select GENERIC_CLOCKEVENTS
1083 select HAVE_SCHED_CLOCK
1088 select GENERIC_IRQ_CHIP
1089 select HAVE_SCHED_CLOCK
1094 config PLAT_VERSATILE
1097 config ARM_TIMER_SP804
1101 source arch/arm/mm/Kconfig
1104 bool "Enable iWMMXt support"
1105 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1106 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1108 Enable support for iWMMXt context switching at run time if
1109 running on a CPU that supports it.
1111 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1114 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1118 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1119 (!ARCH_OMAP3 || OMAP3_EMU)
1123 config MULTI_IRQ_HANDLER
1126 Allow each machine to specify it's own IRQ handler at run time.
1129 source "arch/arm/Kconfig-nommu"
1132 config ARM_ERRATA_411920
1133 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1134 depends on CPU_V6 || CPU_V6K
1136 Invalidation of the Instruction Cache operation can
1137 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1138 It does not affect the MPCore. This option enables the ARM Ltd.
1139 recommended workaround.
1141 config ARM_ERRATA_430973
1142 bool "ARM errata: Stale prediction on replaced interworking branch"
1145 This option enables the workaround for the 430973 Cortex-A8
1146 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1147 interworking branch is replaced with another code sequence at the
1148 same virtual address, whether due to self-modifying code or virtual
1149 to physical address re-mapping, Cortex-A8 does not recover from the
1150 stale interworking branch prediction. This results in Cortex-A8
1151 executing the new code sequence in the incorrect ARM or Thumb state.
1152 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1153 and also flushes the branch target cache at every context switch.
1154 Note that setting specific bits in the ACTLR register may not be
1155 available in non-secure mode.
1157 config ARM_ERRATA_458693
1158 bool "ARM errata: Processor deadlock when a false hazard is created"
1161 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1162 erratum. For very specific sequences of memory operations, it is
1163 possible for a hazard condition intended for a cache line to instead
1164 be incorrectly associated with a different cache line. This false
1165 hazard might then cause a processor deadlock. The workaround enables
1166 the L1 caching of the NEON accesses and disables the PLD instruction
1167 in the ACTLR register. Note that setting specific bits in the ACTLR
1168 register may not be available in non-secure mode.
1170 config ARM_ERRATA_460075
1171 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1174 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1175 erratum. Any asynchronous access to the L2 cache may encounter a
1176 situation in which recent store transactions to the L2 cache are lost
1177 and overwritten with stale memory contents from external memory. The
1178 workaround disables the write-allocate mode for the L2 cache via the
1179 ACTLR register. Note that setting specific bits in the ACTLR register
1180 may not be available in non-secure mode.
1182 config ARM_ERRATA_742230
1183 bool "ARM errata: DMB operation may be faulty"
1184 depends on CPU_V7 && SMP
1186 This option enables the workaround for the 742230 Cortex-A9
1187 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1188 between two write operations may not ensure the correct visibility
1189 ordering of the two writes. This workaround sets a specific bit in
1190 the diagnostic register of the Cortex-A9 which causes the DMB
1191 instruction to behave as a DSB, ensuring the correct behaviour of
1194 config ARM_ERRATA_742231
1195 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1196 depends on CPU_V7 && SMP
1198 This option enables the workaround for the 742231 Cortex-A9
1199 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1200 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1201 accessing some data located in the same cache line, may get corrupted
1202 data due to bad handling of the address hazard when the line gets
1203 replaced from one of the CPUs at the same time as another CPU is
1204 accessing it. This workaround sets specific bits in the diagnostic
1205 register of the Cortex-A9 which reduces the linefill issuing
1206 capabilities of the processor.
1208 config PL310_ERRATA_588369
1209 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1210 depends on CACHE_L2X0
1212 The PL310 L2 cache controller implements three types of Clean &
1213 Invalidate maintenance operations: by Physical Address
1214 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1215 They are architecturally defined to behave as the execution of a
1216 clean operation followed immediately by an invalidate operation,
1217 both performing to the same memory location. This functionality
1218 is not correctly implemented in PL310 as clean lines are not
1219 invalidated as a result of these operations.
1221 config ARM_ERRATA_720789
1222 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1223 depends on CPU_V7 && SMP
1225 This option enables the workaround for the 720789 Cortex-A9 (prior to
1226 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1227 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1228 As a consequence of this erratum, some TLB entries which should be
1229 invalidated are not, resulting in an incoherency in the system page
1230 tables. The workaround changes the TLB flushing routines to invalidate
1231 entries regardless of the ASID.
1233 config PL310_ERRATA_727915
1234 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1235 depends on CACHE_L2X0
1237 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1238 operation (offset 0x7FC). This operation runs in background so that
1239 PL310 can handle normal accesses while it is in progress. Under very
1240 rare circumstances, due to this erratum, write data can be lost when
1241 PL310 treats a cacheable write transaction during a Clean &
1242 Invalidate by Way operation.
1244 config ARM_ERRATA_743622
1245 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1248 This option enables the workaround for the 743622 Cortex-A9
1249 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1250 optimisation in the Cortex-A9 Store Buffer may lead to data
1251 corruption. This workaround sets a specific bit in the diagnostic
1252 register of the Cortex-A9 which disables the Store Buffer
1253 optimisation, preventing the defect from occurring. This has no
1254 visible impact on the overall performance or power consumption of the
1257 config ARM_ERRATA_751472
1258 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1259 depends on CPU_V7 && SMP
1261 This option enables the workaround for the 751472 Cortex-A9 (prior
1262 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1263 completion of a following broadcasted operation if the second
1264 operation is received by a CPU before the ICIALLUIS has completed,
1265 potentially leading to corrupted entries in the cache or TLB.
1267 config ARM_ERRATA_753970
1268 bool "ARM errata: cache sync operation may be faulty"
1269 depends on CACHE_PL310
1271 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1273 Under some condition the effect of cache sync operation on
1274 the store buffer still remains when the operation completes.
1275 This means that the store buffer is always asked to drain and
1276 this prevents it from merging any further writes. The workaround
1277 is to replace the normal offset of cache sync operation (0x730)
1278 by another offset targeting an unmapped PL310 register 0x740.
1279 This has the same effect as the cache sync operation: store buffer
1280 drain and waiting for all buffers empty.
1282 config ARM_ERRATA_754322
1283 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1286 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1287 r3p*) erratum. A speculative memory access may cause a page table walk
1288 which starts prior to an ASID switch but completes afterwards. This
1289 can populate the micro-TLB with a stale entry which may be hit with
1290 the new ASID. This workaround places two dsb instructions in the mm
1291 switching code so that no page table walks can cross the ASID switch.
1293 config ARM_ERRATA_754327
1294 bool "ARM errata: no automatic Store Buffer drain"
1295 depends on CPU_V7 && SMP
1297 This option enables the workaround for the 754327 Cortex-A9 (prior to
1298 r2p0) erratum. The Store Buffer does not have any automatic draining
1299 mechanism and therefore a livelock may occur if an external agent
1300 continuously polls a memory location waiting to observe an update.
1301 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1302 written polling loops from denying visibility of updates to memory.
1306 source "arch/arm/common/Kconfig"
1316 Find out whether you have ISA slots on your motherboard. ISA is the
1317 name of a bus system, i.e. the way the CPU talks to the other stuff
1318 inside your box. Other bus systems are PCI, EISA, MicroChannel
1319 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1320 newer boards don't support it. If you have ISA, say Y, otherwise N.
1322 # Select ISA DMA controller support
1327 # Select ISA DMA interface
1332 bool "PCI support" if MIGHT_HAVE_PCI
1334 Find out whether you have a PCI motherboard. PCI is the name of a
1335 bus system, i.e. the way the CPU talks to the other stuff inside
1336 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1337 VESA. If you have PCI, say Y, otherwise N.
1343 config PCI_NANOENGINE
1344 bool "BSE nanoEngine PCI support"
1345 depends on SA1100_NANOENGINE
1347 Enable PCI on the BSE nanoEngine board.
1352 # Select the host bridge type
1353 config PCI_HOST_VIA82C505
1355 depends on PCI && ARCH_SHARK
1358 config PCI_HOST_ITE8152
1360 depends on PCI && MACH_ARMCORE
1364 source "drivers/pci/Kconfig"
1366 source "drivers/pcmcia/Kconfig"
1370 menu "Kernel Features"
1372 source "kernel/time/Kconfig"
1375 bool "Symmetric Multi-Processing"
1376 depends on CPU_V6K || CPU_V7
1377 depends on GENERIC_CLOCKEVENTS
1378 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1379 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1380 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1381 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1382 select USE_GENERIC_SMP_HELPERS
1383 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1385 This enables support for systems with more than one CPU. If you have
1386 a system with only one CPU, like most personal computers, say N. If
1387 you have a system with more than one CPU, say Y.
1389 If you say N here, the kernel will run on single and multiprocessor
1390 machines, but will use only one CPU of a multiprocessor machine. If
1391 you say Y here, the kernel will run on many, but not all, single
1392 processor machines. On a single processor machine, the kernel will
1393 run faster if you say N here.
1395 See also <file:Documentation/i386/IO-APIC.txt>,
1396 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1397 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1399 If you don't know what to do here, say N.
1402 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1403 depends on EXPERIMENTAL
1404 depends on SMP && !XIP_KERNEL
1407 SMP kernels contain instructions which fail on non-SMP processors.
1408 Enabling this option allows the kernel to modify itself to make
1409 these instructions safe. Disabling it allows about 1K of space
1412 If you don't know what to do here, say Y.
1417 This option enables support for the ARM system coherency unit
1424 This options enables support for the ARM timer and watchdog unit
1427 prompt "Memory split"
1430 Select the desired split between kernel and user memory.
1432 If you are not absolutely sure what you are doing, leave this
1436 bool "3G/1G user/kernel split"
1438 bool "2G/2G user/kernel split"
1440 bool "1G/3G user/kernel split"
1445 default 0x40000000 if VMSPLIT_1G
1446 default 0x80000000 if VMSPLIT_2G
1450 int "Maximum number of CPUs (2-32)"
1456 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1457 depends on SMP && HOTPLUG && EXPERIMENTAL
1459 Say Y here to experiment with turning CPUs off and on. CPUs
1460 can be controlled through /sys/devices/system/cpu.
1463 bool "Use local timer interrupts"
1466 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1468 Enable support for local timers on SMP platforms, rather then the
1469 legacy IPI broadcast method. Local timers allows the system
1470 accounting to be spread across the timer interval, preventing a
1471 "thundering herd" at every timer tick.
1473 source kernel/Kconfig.preempt
1477 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1478 ARCH_S5PV210 || ARCH_EXYNOS4
1479 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1480 default AT91_TIMER_HZ if ARCH_AT91
1481 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1484 config THUMB2_KERNEL
1485 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1486 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1488 select ARM_ASM_UNIFIED
1490 By enabling this option, the kernel will be compiled in
1491 Thumb-2 mode. A compiler/assembler that understand the unified
1492 ARM-Thumb syntax is needed.
1496 config THUMB2_AVOID_R_ARM_THM_JUMP11
1497 bool "Work around buggy Thumb-2 short branch relocations in gas"
1498 depends on THUMB2_KERNEL && MODULES
1501 Various binutils versions can resolve Thumb-2 branches to
1502 locally-defined, preemptible global symbols as short-range "b.n"
1503 branch instructions.
1505 This is a problem, because there's no guarantee the final
1506 destination of the symbol, or any candidate locations for a
1507 trampoline, are within range of the branch. For this reason, the
1508 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1509 relocation in modules at all, and it makes little sense to add
1512 The symptom is that the kernel fails with an "unsupported
1513 relocation" error when loading some modules.
1515 Until fixed tools are available, passing
1516 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1517 code which hits this problem, at the cost of a bit of extra runtime
1518 stack usage in some cases.
1520 The problem is described in more detail at:
1521 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1523 Only Thumb-2 kernels are affected.
1525 Unless you are sure your tools don't have this problem, say Y.
1527 config ARM_ASM_UNIFIED
1531 bool "Use the ARM EABI to compile the kernel"
1533 This option allows for the kernel to be compiled using the latest
1534 ARM ABI (aka EABI). This is only useful if you are using a user
1535 space environment that is also compiled with EABI.
1537 Since there are major incompatibilities between the legacy ABI and
1538 EABI, especially with regard to structure member alignment, this
1539 option also changes the kernel syscall calling convention to
1540 disambiguate both ABIs and allow for backward compatibility support
1541 (selected with CONFIG_OABI_COMPAT).
1543 To use this you need GCC version 4.0.0 or later.
1546 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1547 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1550 This option preserves the old syscall interface along with the
1551 new (ARM EABI) one. It also provides a compatibility layer to
1552 intercept syscalls that have structure arguments which layout
1553 in memory differs between the legacy ABI and the new ARM EABI
1554 (only for non "thumb" binaries). This option adds a tiny
1555 overhead to all syscalls and produces a slightly larger kernel.
1556 If you know you'll be using only pure EABI user space then you
1557 can say N here. If this option is not selected and you attempt
1558 to execute a legacy ABI binary then the result will be
1559 UNPREDICTABLE (in fact it can be predicted that it won't work
1560 at all). If in doubt say Y.
1562 config ARCH_HAS_HOLES_MEMORYMODEL
1565 config ARCH_SPARSEMEM_ENABLE
1568 config ARCH_SPARSEMEM_DEFAULT
1569 def_bool ARCH_SPARSEMEM_ENABLE
1571 config ARCH_SELECT_MEMORY_MODEL
1572 def_bool ARCH_SPARSEMEM_ENABLE
1574 config HAVE_ARCH_PFN_VALID
1575 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1578 bool "High Memory Support"
1581 The address space of ARM processors is only 4 Gigabytes large
1582 and it has to accommodate user address space, kernel address
1583 space as well as some memory mapped IO. That means that, if you
1584 have a large amount of physical memory and/or IO, not all of the
1585 memory can be "permanently mapped" by the kernel. The physical
1586 memory that is not permanently mapped is called "high memory".
1588 Depending on the selected kernel/user memory split, minimum
1589 vmalloc space and actual amount of RAM, you may not need this
1590 option which should result in a slightly faster kernel.
1595 bool "Allocate 2nd-level pagetables from highmem"
1598 config HW_PERF_EVENTS
1599 bool "Enable hardware performance counter support for perf events"
1600 depends on PERF_EVENTS && CPU_HAS_PMU
1603 Enable hardware performance counter support for perf events. If
1604 disabled, perf events will use software events only.
1608 config FORCE_MAX_ZONEORDER
1609 int "Maximum zone order" if ARCH_SHMOBILE
1610 range 11 64 if ARCH_SHMOBILE
1611 default "9" if SA1111
1614 The kernel memory allocator divides physically contiguous memory
1615 blocks into "zones", where each zone is a power of two number of
1616 pages. This option selects the largest power of two that the kernel
1617 keeps in the memory allocator. If you need to allocate very large
1618 blocks of physically contiguous memory, then you may need to
1619 increase this value.
1621 This config option is actually maximum order plus one. For example,
1622 a value of 11 means that the largest free memory block is 2^10 pages.
1625 bool "Timer and CPU usage LEDs"
1626 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1627 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1628 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1629 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1630 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1631 ARCH_AT91 || ARCH_DAVINCI || \
1632 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1634 If you say Y here, the LEDs on your machine will be used
1635 to provide useful information about your current system status.
1637 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1638 be able to select which LEDs are active using the options below. If
1639 you are compiling a kernel for the EBSA-110 or the LART however, the
1640 red LED will simply flash regularly to indicate that the system is
1641 still functional. It is safe to say Y here if you have a CATS
1642 system, but the driver will do nothing.
1645 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1646 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1647 || MACH_OMAP_PERSEUS2
1649 depends on !GENERIC_CLOCKEVENTS
1650 default y if ARCH_EBSA110
1652 If you say Y here, one of the system LEDs (the green one on the
1653 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1654 will flash regularly to indicate that the system is still
1655 operational. This is mainly useful to kernel hackers who are
1656 debugging unstable kernels.
1658 The LART uses the same LED for both Timer LED and CPU usage LED
1659 functions. You may choose to use both, but the Timer LED function
1660 will overrule the CPU usage LED.
1663 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1665 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1666 || MACH_OMAP_PERSEUS2
1669 If you say Y here, the red LED will be used to give a good real
1670 time indication of CPU usage, by lighting whenever the idle task
1671 is not currently executing.
1673 The LART uses the same LED for both Timer LED and CPU usage LED
1674 functions. You may choose to use both, but the Timer LED function
1675 will overrule the CPU usage LED.
1677 config ALIGNMENT_TRAP
1679 depends on CPU_CP15_MMU
1680 default y if !ARCH_EBSA110
1681 select HAVE_PROC_CPU if PROC_FS
1683 ARM processors cannot fetch/store information which is not
1684 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1685 address divisible by 4. On 32-bit ARM processors, these non-aligned
1686 fetch/store instructions will be emulated in software if you say
1687 here, which has a severe performance impact. This is necessary for
1688 correct operation of some network protocols. With an IP-only
1689 configuration it is safe to say N, otherwise say Y.
1691 config UACCESS_WITH_MEMCPY
1692 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1693 depends on MMU && EXPERIMENTAL
1694 default y if CPU_FEROCEON
1696 Implement faster copy_to_user and clear_user methods for CPU
1697 cores where a 8-word STM instruction give significantly higher
1698 memory write throughput than a sequence of individual 32bit stores.
1700 A possible side effect is a slight increase in scheduling latency
1701 between threads sharing the same address space if they invoke
1702 such copy operations with large buffers.
1704 However, if the CPU data cache is using a write-allocate mode,
1705 this option is unlikely to provide any performance gain.
1709 prompt "Enable seccomp to safely compute untrusted bytecode"
1711 This kernel feature is useful for number crunching applications
1712 that may need to compute untrusted bytecode during their
1713 execution. By using pipes or other transports made available to
1714 the process as file descriptors supporting the read/write
1715 syscalls, it's possible to isolate those applications in
1716 their own address space using seccomp. Once seccomp is
1717 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1718 and the task is only allowed to execute a few safe syscalls
1719 defined by each seccomp mode.
1721 config CC_STACKPROTECTOR
1722 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1723 depends on EXPERIMENTAL
1725 This option turns on the -fstack-protector GCC feature. This
1726 feature puts, at the beginning of functions, a canary value on
1727 the stack just before the return address, and validates
1728 the value just before actually returning. Stack based buffer
1729 overflows (that need to overwrite this return address) now also
1730 overwrite the canary, which gets detected and the attack is then
1731 neutralized via a kernel panic.
1732 This feature requires gcc version 4.2 or above.
1734 config DEPRECATED_PARAM_STRUCT
1735 bool "Provide old way to pass kernel parameters"
1737 This was deprecated in 2001 and announced to live on for 5 years.
1738 Some old boot loaders still use this way.
1745 bool "Flattened Device Tree support"
1747 select OF_EARLY_FLATTREE
1750 Include support for flattened device tree machine descriptions.
1752 # Compressed boot loader in ROM. Yes, we really want to ask about
1753 # TEXT and BSS so we preserve their values in the config files.
1754 config ZBOOT_ROM_TEXT
1755 hex "Compressed ROM boot loader base address"
1758 The physical address at which the ROM-able zImage is to be
1759 placed in the target. Platforms which normally make use of
1760 ROM-able zImage formats normally set this to a suitable
1761 value in their defconfig file.
1763 If ZBOOT_ROM is not enabled, this has no effect.
1765 config ZBOOT_ROM_BSS
1766 hex "Compressed ROM boot loader BSS address"
1769 The base address of an area of read/write memory in the target
1770 for the ROM-able zImage which must be available while the
1771 decompressor is running. It must be large enough to hold the
1772 entire decompressed kernel plus an additional 128 KiB.
1773 Platforms which normally make use of ROM-able zImage formats
1774 normally set this to a suitable value in their defconfig file.
1776 If ZBOOT_ROM is not enabled, this has no effect.
1779 bool "Compressed boot loader in ROM/flash"
1780 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1782 Say Y here if you intend to execute your compressed kernel image
1783 (zImage) directly from ROM or flash. If unsure, say N.
1786 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1787 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1788 default ZBOOT_ROM_NONE
1790 Include experimental SD/MMC loading code in the ROM-able zImage.
1791 With this enabled it is possible to write the the ROM-able zImage
1792 kernel image to an MMC or SD card and boot the kernel straight
1793 from the reset vector. At reset the processor Mask ROM will load
1794 the first part of the the ROM-able zImage which in turn loads the
1795 rest the kernel image to RAM.
1797 config ZBOOT_ROM_NONE
1798 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1800 Do not load image from SD or MMC
1802 config ZBOOT_ROM_MMCIF
1803 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1805 Load image from MMCIF hardware block.
1807 config ZBOOT_ROM_SH_MOBILE_SDHI
1808 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1810 Load image from SDHI hardware block
1815 string "Default kernel command string"
1818 On some architectures (EBSA110 and CATS), there is currently no way
1819 for the boot loader to pass arguments to the kernel. For these
1820 architectures, you should supply some command-line options at build
1821 time by entering them here. As a minimum, you should specify the
1822 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1825 prompt "Kernel command line type" if CMDLINE != ""
1826 default CMDLINE_FROM_BOOTLOADER
1828 config CMDLINE_FROM_BOOTLOADER
1829 bool "Use bootloader kernel arguments if available"
1831 Uses the command-line options passed by the boot loader. If
1832 the boot loader doesn't provide any, the default kernel command
1833 string provided in CMDLINE will be used.
1835 config CMDLINE_EXTEND
1836 bool "Extend bootloader kernel arguments"
1838 The command-line arguments provided by the boot loader will be
1839 appended to the default kernel command string.
1841 config CMDLINE_FORCE
1842 bool "Always use the default kernel command string"
1844 Always use the default kernel command string, even if the boot
1845 loader passes other arguments to the kernel.
1846 This is useful if you cannot or don't want to change the
1847 command-line options your boot loader passes to the kernel.
1851 bool "Kernel Execute-In-Place from ROM"
1852 depends on !ZBOOT_ROM
1854 Execute-In-Place allows the kernel to run from non-volatile storage
1855 directly addressable by the CPU, such as NOR flash. This saves RAM
1856 space since the text section of the kernel is not loaded from flash
1857 to RAM. Read-write sections, such as the data section and stack,
1858 are still copied to RAM. The XIP kernel is not compressed since
1859 it has to run directly from flash, so it will take more space to
1860 store it. The flash address used to link the kernel object files,
1861 and for storing it, is configuration dependent. Therefore, if you
1862 say Y here, you must know the proper physical address where to
1863 store the kernel image depending on your own flash memory usage.
1865 Also note that the make target becomes "make xipImage" rather than
1866 "make zImage" or "make Image". The final kernel binary to put in
1867 ROM memory will be arch/arm/boot/xipImage.
1871 config XIP_PHYS_ADDR
1872 hex "XIP Kernel Physical Location"
1873 depends on XIP_KERNEL
1874 default "0x00080000"
1876 This is the physical address in your flash memory the kernel will
1877 be linked for and stored to. This address is dependent on your
1881 bool "Kexec system call (EXPERIMENTAL)"
1882 depends on EXPERIMENTAL
1884 kexec is a system call that implements the ability to shutdown your
1885 current kernel, and to start another kernel. It is like a reboot
1886 but it is independent of the system firmware. And like a reboot
1887 you can start any kernel with it, not just Linux.
1889 It is an ongoing process to be certain the hardware in a machine
1890 is properly shutdown, so do not be surprised if this code does not
1891 initially work for you. It may help to enable device hotplugging
1895 bool "Export atags in procfs"
1899 Should the atags used to boot the kernel be exported in an "atags"
1900 file in procfs. Useful with kexec.
1903 bool "Build kdump crash kernel (EXPERIMENTAL)"
1904 depends on EXPERIMENTAL
1906 Generate crash dump after being started by kexec. This should
1907 be normally only set in special crash dump kernels which are
1908 loaded in the main kernel with kexec-tools into a specially
1909 reserved region and then later executed after a crash by
1910 kdump/kexec. The crash dump kernel must be compiled to a
1911 memory address not used by the main kernel
1913 For more details see Documentation/kdump/kdump.txt
1915 config AUTO_ZRELADDR
1916 bool "Auto calculation of the decompressed kernel image address"
1917 depends on !ZBOOT_ROM && !ARCH_U300
1919 ZRELADDR is the physical address where the decompressed kernel
1920 image will be placed. If AUTO_ZRELADDR is selected, the address
1921 will be determined at run-time by masking the current IP with
1922 0xf8000000. This assumes the zImage being placed in the first 128MB
1923 from start of memory.
1927 menu "CPU Power Management"
1931 source "drivers/cpufreq/Kconfig"
1934 tristate "CPUfreq driver for i.MX CPUs"
1935 depends on ARCH_MXC && CPU_FREQ
1937 This enables the CPUfreq driver for i.MX CPUs.
1939 config CPU_FREQ_SA1100
1942 config CPU_FREQ_SA1110
1945 config CPU_FREQ_INTEGRATOR
1946 tristate "CPUfreq driver for ARM Integrator CPUs"
1947 depends on ARCH_INTEGRATOR && CPU_FREQ
1950 This enables the CPUfreq driver for ARM Integrator CPUs.
1952 For details, take a look at <file:Documentation/cpu-freq>.
1958 depends on CPU_FREQ && ARCH_PXA && PXA25x
1960 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1965 Internal configuration node for common cpufreq on Samsung SoC
1967 config CPU_FREQ_S3C24XX
1968 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1969 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1972 This enables the CPUfreq driver for the Samsung S3C24XX family
1975 For details, take a look at <file:Documentation/cpu-freq>.
1979 config CPU_FREQ_S3C24XX_PLL
1980 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1981 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1983 Compile in support for changing the PLL frequency from the
1984 S3C24XX series CPUfreq driver. The PLL takes time to settle
1985 after a frequency change, so by default it is not enabled.
1987 This also means that the PLL tables for the selected CPU(s) will
1988 be built which may increase the size of the kernel image.
1990 config CPU_FREQ_S3C24XX_DEBUG
1991 bool "Debug CPUfreq Samsung driver core"
1992 depends on CPU_FREQ_S3C24XX
1994 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1996 config CPU_FREQ_S3C24XX_IODEBUG
1997 bool "Debug CPUfreq Samsung driver IO timing"
1998 depends on CPU_FREQ_S3C24XX
2000 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2002 config CPU_FREQ_S3C24XX_DEBUGFS
2003 bool "Export debugfs for CPUFreq"
2004 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2006 Export status information via debugfs.
2010 source "drivers/cpuidle/Kconfig"
2014 menu "Floating point emulation"
2016 comment "At least one emulation must be selected"
2019 bool "NWFPE math emulation"
2020 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2022 Say Y to include the NWFPE floating point emulator in the kernel.
2023 This is necessary to run most binaries. Linux does not currently
2024 support floating point hardware so you need to say Y here even if
2025 your machine has an FPA or floating point co-processor podule.
2027 You may say N here if you are going to load the Acorn FPEmulator
2028 early in the bootup.
2031 bool "Support extended precision"
2032 depends on FPE_NWFPE
2034 Say Y to include 80-bit support in the kernel floating-point
2035 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2036 Note that gcc does not generate 80-bit operations by default,
2037 so in most cases this option only enlarges the size of the
2038 floating point emulator without any good reason.
2040 You almost surely want to say N here.
2043 bool "FastFPE math emulation (EXPERIMENTAL)"
2044 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2046 Say Y here to include the FAST floating point emulator in the kernel.
2047 This is an experimental much faster emulator which now also has full
2048 precision for the mantissa. It does not support any exceptions.
2049 It is very simple, and approximately 3-6 times faster than NWFPE.
2051 It should be sufficient for most programs. It may be not suitable
2052 for scientific calculations, but you have to check this for yourself.
2053 If you do not feel you need a faster FP emulation you should better
2057 bool "VFP-format floating point maths"
2058 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2060 Say Y to include VFP support code in the kernel. This is needed
2061 if your hardware includes a VFP unit.
2063 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2064 release notes and additional status information.
2066 Say N if your target does not have VFP hardware.
2074 bool "Advanced SIMD (NEON) Extension support"
2075 depends on VFPv3 && CPU_V7
2077 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2082 menu "Userspace binary formats"
2084 source "fs/Kconfig.binfmt"
2087 tristate "RISC OS personality"
2090 Say Y here to include the kernel code necessary if you want to run
2091 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2092 experimental; if this sounds frightening, say N and sleep in peace.
2093 You can also say M here to compile this support as a module (which
2094 will be called arthur).
2098 menu "Power management options"
2100 source "kernel/power/Kconfig"
2102 config ARCH_SUSPEND_POSSIBLE
2103 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2104 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2105 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2110 source "net/Kconfig"
2112 source "drivers/Kconfig"
2116 source "arch/arm/Kconfig.debug"
2118 source "security/Kconfig"
2120 source "crypto/Kconfig"
2122 source "lib/Kconfig"