5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 Support for Broadcom's BCMRing platform.
331 bool "Cirrus Logic CLPS711x/EP721x-based"
333 select ARCH_USES_GETTIMEOFFSET
335 Support for Cirrus Logic 711x/721x based boards.
338 bool "Cavium Networks CNS3XXX family"
340 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select PCI_DOMAINS if PCI
345 Support for Cavium Networks CNS3XXX platform.
348 bool "Cortina Systems Gemini"
350 select ARCH_REQUIRE_GPIOLIB
351 select ARCH_USES_GETTIMEOFFSET
353 Support for the Cortina Systems Gemini family SoCs
356 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
360 select GENERIC_CLOCKEVENTS
362 select GENERIC_IRQ_CHIP
366 Support for CSR SiRFSoC ARM Cortex A9 Platform
373 select ARCH_USES_GETTIMEOFFSET
375 This is an evaluation board for the StrongARM processor available
376 from Digital. It has limited hardware on-board, including an
377 Ethernet interface, two PCMCIA sockets, two serial ports and a
386 select ARCH_REQUIRE_GPIOLIB
387 select ARCH_HAS_HOLES_MEMORYMODEL
388 select ARCH_USES_GETTIMEOFFSET
390 This enables support for the Cirrus EP93xx series of CPUs.
392 config ARCH_FOOTBRIDGE
396 select GENERIC_CLOCKEVENTS
398 Support for systems based on the DC21285 companion chip
399 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
402 bool "Freescale MXC/iMX-based"
403 select GENERIC_CLOCKEVENTS
404 select ARCH_REQUIRE_GPIOLIB
407 select GENERIC_IRQ_CHIP
408 select HAVE_SCHED_CLOCK
410 Support for Freescale MXC/iMX-based family of processors
413 bool "Freescale MXS-based"
414 select GENERIC_CLOCKEVENTS
415 select ARCH_REQUIRE_GPIOLIB
419 Support for Freescale MXS-based family of processors
422 bool "Hilscher NetX based"
426 select GENERIC_CLOCKEVENTS
428 This enables support for systems based on the Hilscher NetX Soc
431 bool "Hynix HMS720x-based"
434 select ARCH_USES_GETTIMEOFFSET
436 This enables support for systems based on the Hynix HMS720x
444 select ARCH_SUPPORTS_MSI
447 Support for Intel's IOP13XX (XScale) family of processors.
455 select ARCH_REQUIRE_GPIOLIB
456 select NO_MACH_MEMORY_H
458 Support for Intel's 80219 and IOP32X (XScale) family of
467 select ARCH_REQUIRE_GPIOLIB
468 select NO_MACH_MEMORY_H
470 Support for Intel's IOP33X (XScale) family of processors.
477 select ARCH_USES_GETTIMEOFFSET
479 Support for Intel's IXP23xx (XScale) family of processors.
482 bool "IXP2400/2800-based"
486 select ARCH_USES_GETTIMEOFFSET
488 Support for Intel's IXP2400/2800 (XScale) family of processors.
496 select GENERIC_CLOCKEVENTS
497 select HAVE_SCHED_CLOCK
498 select MIGHT_HAVE_PCI
499 select DMABOUNCE if PCI
501 Support for Intel's IXP4XX (XScale) family of processors.
507 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
510 select NO_MACH_MEMORY_H
512 Support for the Marvell Dove SoC 88AP510
515 bool "Marvell Kirkwood"
518 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
521 select NO_MACH_MEMORY_H
523 Support for the following Marvell Kirkwood series SoCs:
524 88F6180, 88F6192 and 88F6281.
530 select ARCH_REQUIRE_GPIOLIB
533 select USB_ARCH_HAS_OHCI
536 select GENERIC_CLOCKEVENTS
538 Support for the NXP LPC32XX family of processors
541 bool "Marvell MV78xx0"
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
547 select NO_MACH_MEMORY_H
549 Support for the following Marvell MV78xx0 series SoCs:
557 select ARCH_REQUIRE_GPIOLIB
558 select GENERIC_CLOCKEVENTS
560 select NO_MACH_MEMORY_H
562 Support for the following Marvell Orion 5x series SoCs:
563 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
564 Orion-2 (5281), Orion-1-90 (6183).
567 bool "Marvell PXA168/910/MMP2"
569 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
572 select HAVE_SCHED_CLOCK
577 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
580 bool "Micrel/Kendin KS8695"
582 select ARCH_REQUIRE_GPIOLIB
583 select ARCH_USES_GETTIMEOFFSET
585 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
586 System-on-Chip devices.
589 bool "Nuvoton W90X900 CPU"
591 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
595 select NO_MACH_MEMORY_H
597 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
598 At present, the w90x900 has been renamed nuc900, regarding
599 the ARM series product line, you can login the following
600 link address to know more.
602 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
603 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
606 bool "Nuvoton NUC93X CPU"
610 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
611 low-power and high performance MPEG-4/JPEG multimedia controller chip.
618 select GENERIC_CLOCKEVENTS
621 select HAVE_SCHED_CLOCK
622 select ARCH_HAS_CPUFREQ
624 This enables support for NVIDIA Tegra based systems (Tegra APX,
625 Tegra 6xx and Tegra 2 series).
628 bool "Philips Nexperia PNX4008 Mobile"
631 select ARCH_USES_GETTIMEOFFSET
632 select NO_MACH_MEMORY_H
634 This enables support for Philips PNX4008 mobile platform.
637 bool "PXA2xx/PXA3xx-based"
640 select ARCH_HAS_CPUFREQ
643 select ARCH_REQUIRE_GPIOLIB
644 select GENERIC_CLOCKEVENTS
645 select HAVE_SCHED_CLOCK
650 select MULTI_IRQ_HANDLER
652 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
657 select GENERIC_CLOCKEVENTS
658 select ARCH_REQUIRE_GPIOLIB
661 Support for Qualcomm MSM/QSD based systems. This runs on the
662 apps processor of the MSM/QSD and depends on a shared memory
663 interface to the modem processor which runs the baseband
664 stack and controls some vital subsystems
665 (clock and power control, etc).
668 bool "Renesas SH-Mobile / R-Mobile"
671 select HAVE_MACH_CLKDEV
672 select GENERIC_CLOCKEVENTS
675 select MULTI_IRQ_HANDLER
676 select PM_GENERIC_DOMAINS if PM
678 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
685 select ARCH_MAY_HAVE_PC_FDC
686 select HAVE_PATA_PLATFORM
689 select ARCH_SPARSEMEM_ENABLE
690 select ARCH_USES_GETTIMEOFFSET
692 On the Acorn Risc-PC, Linux can support the internal IDE disk and
693 CD-ROM interface, serial and parallel port, and the floppy drive.
700 select ARCH_SPARSEMEM_ENABLE
702 select ARCH_HAS_CPUFREQ
704 select GENERIC_CLOCKEVENTS
706 select HAVE_SCHED_CLOCK
708 select ARCH_REQUIRE_GPIOLIB
710 Support for StrongARM 11x0 based boards.
713 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
715 select ARCH_HAS_CPUFREQ
718 select ARCH_USES_GETTIMEOFFSET
719 select HAVE_S3C2410_I2C if I2C
720 select NO_MACH_MEMORY_H
722 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
723 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
724 the Samsung SMDK2410 development board (and derivatives).
726 Note, the S3C2416 and the S3C2450 are so close that they even share
727 the same SoC ID code. This means that there is no separate machine
728 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
731 bool "Samsung S3C64XX"
738 select ARCH_USES_GETTIMEOFFSET
739 select ARCH_HAS_CPUFREQ
740 select ARCH_REQUIRE_GPIOLIB
741 select SAMSUNG_CLKSRC
742 select SAMSUNG_IRQ_VIC_TIMER
743 select SAMSUNG_IRQ_UART
744 select S3C_GPIO_TRACK
745 select S3C_GPIO_PULL_UPDOWN
746 select S3C_GPIO_CFG_S3C24XX
747 select S3C_GPIO_CFG_S3C64XX
749 select USB_ARCH_HAS_OHCI
750 select SAMSUNG_GPIOLIB_4BIT
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 Samsung S3C64XX series based systems
757 bool "Samsung S5P6440 S5P6450"
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select GENERIC_CLOCKEVENTS
765 select HAVE_SCHED_CLOCK
766 select HAVE_S3C2410_I2C if I2C
767 select HAVE_S3C_RTC if RTC_CLASS
769 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
773 bool "Samsung S5PC100"
778 select ARM_L1_CACHE_SHIFT_6
779 select ARCH_USES_GETTIMEOFFSET
780 select HAVE_S3C2410_I2C if I2C
781 select HAVE_S3C_RTC if RTC_CLASS
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 Samsung S5PC100 series based systems
787 bool "Samsung S5PV210/S5PC110"
789 select ARCH_SPARSEMEM_ENABLE
790 select ARCH_HAS_HOLES_MEMORYMODEL
795 select ARM_L1_CACHE_SHIFT_6
796 select ARCH_HAS_CPUFREQ
797 select GENERIC_CLOCKEVENTS
798 select HAVE_SCHED_CLOCK
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C_RTC if RTC_CLASS
801 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 Samsung S5PV210/S5PC110 series based systems
806 bool "Samsung EXYNOS4"
808 select ARCH_SPARSEMEM_ENABLE
809 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_HAS_CPUFREQ
814 select GENERIC_CLOCKEVENTS
815 select HAVE_S3C_RTC if RTC_CLASS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 Samsung EXYNOS4 series based systems
828 select ARCH_USES_GETTIMEOFFSET
830 Support for the StrongARM based Digital DNARD machine, also known
831 as "Shark" (<http://www.shark-linux.de/shark.html>).
834 bool "Telechips TCC ARM926-based systems"
839 select GENERIC_CLOCKEVENTS
841 Support for Telechips TCC ARM926-based systems.
844 bool "ST-Ericsson U300 Series"
848 select HAVE_SCHED_CLOCK
852 select GENERIC_CLOCKEVENTS
854 select HAVE_MACH_CLKDEV
857 Support for ST-Ericsson U300 series mobile platforms.
860 bool "ST-Ericsson U8500 Series"
863 select GENERIC_CLOCKEVENTS
865 select ARCH_REQUIRE_GPIOLIB
866 select ARCH_HAS_CPUFREQ
867 select NO_MACH_MEMORY_H
869 Support for ST-Ericsson's Ux500 architecture
872 bool "STMicroelectronics Nomadik"
877 select GENERIC_CLOCKEVENTS
878 select ARCH_REQUIRE_GPIOLIB
879 select NO_MACH_MEMORY_H
881 Support for the Nomadik platform by ST-Ericsson
885 select GENERIC_CLOCKEVENTS
886 select ARCH_REQUIRE_GPIOLIB
890 select GENERIC_ALLOCATOR
891 select GENERIC_IRQ_CHIP
892 select ARCH_HAS_HOLES_MEMORYMODEL
894 Support for TI's DaVinci platform.
899 select ARCH_REQUIRE_GPIOLIB
900 select ARCH_HAS_CPUFREQ
902 select GENERIC_CLOCKEVENTS
903 select HAVE_SCHED_CLOCK
904 select ARCH_HAS_HOLES_MEMORYMODEL
906 Support for TI's OMAP platform (OMAP1/2/3/4).
911 select ARCH_REQUIRE_GPIOLIB
914 select GENERIC_CLOCKEVENTS
917 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
920 bool "VIA/WonderMedia 85xx"
923 select ARCH_HAS_CPUFREQ
924 select GENERIC_CLOCKEVENTS
925 select ARCH_REQUIRE_GPIOLIB
928 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
931 bool "Xilinx Zynq ARM Cortex A9 Platform"
934 select GENERIC_CLOCKEVENTS
941 Support for Xilinx Zynq ARM Cortex A9 Platform
945 # This is sorted alphabetically by mach-* pathname. However, plat-*
946 # Kconfigs may be included either alphabetically (according to the
947 # plat- suffix) or along side the corresponding mach-* source.
949 source "arch/arm/mach-at91/Kconfig"
951 source "arch/arm/mach-bcmring/Kconfig"
953 source "arch/arm/mach-clps711x/Kconfig"
955 source "arch/arm/mach-cns3xxx/Kconfig"
957 source "arch/arm/mach-davinci/Kconfig"
959 source "arch/arm/mach-dove/Kconfig"
961 source "arch/arm/mach-ep93xx/Kconfig"
963 source "arch/arm/mach-footbridge/Kconfig"
965 source "arch/arm/mach-gemini/Kconfig"
967 source "arch/arm/mach-h720x/Kconfig"
969 source "arch/arm/mach-integrator/Kconfig"
971 source "arch/arm/mach-iop32x/Kconfig"
973 source "arch/arm/mach-iop33x/Kconfig"
975 source "arch/arm/mach-iop13xx/Kconfig"
977 source "arch/arm/mach-ixp4xx/Kconfig"
979 source "arch/arm/mach-ixp2000/Kconfig"
981 source "arch/arm/mach-ixp23xx/Kconfig"
983 source "arch/arm/mach-kirkwood/Kconfig"
985 source "arch/arm/mach-ks8695/Kconfig"
987 source "arch/arm/mach-lpc32xx/Kconfig"
989 source "arch/arm/mach-msm/Kconfig"
991 source "arch/arm/mach-mv78xx0/Kconfig"
993 source "arch/arm/plat-mxc/Kconfig"
995 source "arch/arm/mach-mxs/Kconfig"
997 source "arch/arm/mach-netx/Kconfig"
999 source "arch/arm/mach-nomadik/Kconfig"
1000 source "arch/arm/plat-nomadik/Kconfig"
1002 source "arch/arm/mach-nuc93x/Kconfig"
1004 source "arch/arm/plat-omap/Kconfig"
1006 source "arch/arm/mach-omap1/Kconfig"
1008 source "arch/arm/mach-omap2/Kconfig"
1010 source "arch/arm/mach-orion5x/Kconfig"
1012 source "arch/arm/mach-pxa/Kconfig"
1013 source "arch/arm/plat-pxa/Kconfig"
1015 source "arch/arm/mach-mmp/Kconfig"
1017 source "arch/arm/mach-realview/Kconfig"
1019 source "arch/arm/mach-sa1100/Kconfig"
1021 source "arch/arm/plat-samsung/Kconfig"
1022 source "arch/arm/plat-s3c24xx/Kconfig"
1023 source "arch/arm/plat-s5p/Kconfig"
1025 source "arch/arm/plat-spear/Kconfig"
1027 source "arch/arm/plat-tcc/Kconfig"
1030 source "arch/arm/mach-s3c2410/Kconfig"
1031 source "arch/arm/mach-s3c2412/Kconfig"
1032 source "arch/arm/mach-s3c2416/Kconfig"
1033 source "arch/arm/mach-s3c2440/Kconfig"
1034 source "arch/arm/mach-s3c2443/Kconfig"
1038 source "arch/arm/mach-s3c64xx/Kconfig"
1041 source "arch/arm/mach-s5p64x0/Kconfig"
1043 source "arch/arm/mach-s5pc100/Kconfig"
1045 source "arch/arm/mach-s5pv210/Kconfig"
1047 source "arch/arm/mach-exynos4/Kconfig"
1049 source "arch/arm/mach-shmobile/Kconfig"
1051 source "arch/arm/mach-tegra/Kconfig"
1053 source "arch/arm/mach-u300/Kconfig"
1055 source "arch/arm/mach-ux500/Kconfig"
1057 source "arch/arm/mach-versatile/Kconfig"
1059 source "arch/arm/mach-vexpress/Kconfig"
1060 source "arch/arm/plat-versatile/Kconfig"
1062 source "arch/arm/mach-vt8500/Kconfig"
1064 source "arch/arm/mach-w90x900/Kconfig"
1066 # Definitions to make life easier
1072 select GENERIC_CLOCKEVENTS
1073 select HAVE_SCHED_CLOCK
1078 select GENERIC_IRQ_CHIP
1079 select HAVE_SCHED_CLOCK
1084 config PLAT_VERSATILE
1087 config ARM_TIMER_SP804
1091 source arch/arm/mm/Kconfig
1094 bool "Enable iWMMXt support"
1095 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1096 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1098 Enable support for iWMMXt context switching at run time if
1099 running on a CPU that supports it.
1101 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1104 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1108 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1109 (!ARCH_OMAP3 || OMAP3_EMU)
1113 config MULTI_IRQ_HANDLER
1116 Allow each machine to specify it's own IRQ handler at run time.
1119 source "arch/arm/Kconfig-nommu"
1122 config ARM_ERRATA_411920
1123 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1124 depends on CPU_V6 || CPU_V6K
1126 Invalidation of the Instruction Cache operation can
1127 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1128 It does not affect the MPCore. This option enables the ARM Ltd.
1129 recommended workaround.
1131 config ARM_ERRATA_430973
1132 bool "ARM errata: Stale prediction on replaced interworking branch"
1135 This option enables the workaround for the 430973 Cortex-A8
1136 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1137 interworking branch is replaced with another code sequence at the
1138 same virtual address, whether due to self-modifying code or virtual
1139 to physical address re-mapping, Cortex-A8 does not recover from the
1140 stale interworking branch prediction. This results in Cortex-A8
1141 executing the new code sequence in the incorrect ARM or Thumb state.
1142 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1143 and also flushes the branch target cache at every context switch.
1144 Note that setting specific bits in the ACTLR register may not be
1145 available in non-secure mode.
1147 config ARM_ERRATA_458693
1148 bool "ARM errata: Processor deadlock when a false hazard is created"
1151 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1152 erratum. For very specific sequences of memory operations, it is
1153 possible for a hazard condition intended for a cache line to instead
1154 be incorrectly associated with a different cache line. This false
1155 hazard might then cause a processor deadlock. The workaround enables
1156 the L1 caching of the NEON accesses and disables the PLD instruction
1157 in the ACTLR register. Note that setting specific bits in the ACTLR
1158 register may not be available in non-secure mode.
1160 config ARM_ERRATA_460075
1161 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1164 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1165 erratum. Any asynchronous access to the L2 cache may encounter a
1166 situation in which recent store transactions to the L2 cache are lost
1167 and overwritten with stale memory contents from external memory. The
1168 workaround disables the write-allocate mode for the L2 cache via the
1169 ACTLR register. Note that setting specific bits in the ACTLR register
1170 may not be available in non-secure mode.
1172 config ARM_ERRATA_742230
1173 bool "ARM errata: DMB operation may be faulty"
1174 depends on CPU_V7 && SMP
1176 This option enables the workaround for the 742230 Cortex-A9
1177 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1178 between two write operations may not ensure the correct visibility
1179 ordering of the two writes. This workaround sets a specific bit in
1180 the diagnostic register of the Cortex-A9 which causes the DMB
1181 instruction to behave as a DSB, ensuring the correct behaviour of
1184 config ARM_ERRATA_742231
1185 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1186 depends on CPU_V7 && SMP
1188 This option enables the workaround for the 742231 Cortex-A9
1189 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1190 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1191 accessing some data located in the same cache line, may get corrupted
1192 data due to bad handling of the address hazard when the line gets
1193 replaced from one of the CPUs at the same time as another CPU is
1194 accessing it. This workaround sets specific bits in the diagnostic
1195 register of the Cortex-A9 which reduces the linefill issuing
1196 capabilities of the processor.
1198 config PL310_ERRATA_588369
1199 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1200 depends on CACHE_L2X0
1202 The PL310 L2 cache controller implements three types of Clean &
1203 Invalidate maintenance operations: by Physical Address
1204 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1205 They are architecturally defined to behave as the execution of a
1206 clean operation followed immediately by an invalidate operation,
1207 both performing to the same memory location. This functionality
1208 is not correctly implemented in PL310 as clean lines are not
1209 invalidated as a result of these operations.
1211 config ARM_ERRATA_720789
1212 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1213 depends on CPU_V7 && SMP
1215 This option enables the workaround for the 720789 Cortex-A9 (prior to
1216 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1217 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1218 As a consequence of this erratum, some TLB entries which should be
1219 invalidated are not, resulting in an incoherency in the system page
1220 tables. The workaround changes the TLB flushing routines to invalidate
1221 entries regardless of the ASID.
1223 config PL310_ERRATA_727915
1224 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1225 depends on CACHE_L2X0
1227 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1228 operation (offset 0x7FC). This operation runs in background so that
1229 PL310 can handle normal accesses while it is in progress. Under very
1230 rare circumstances, due to this erratum, write data can be lost when
1231 PL310 treats a cacheable write transaction during a Clean &
1232 Invalidate by Way operation.
1234 config ARM_ERRATA_743622
1235 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1238 This option enables the workaround for the 743622 Cortex-A9
1239 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1240 optimisation in the Cortex-A9 Store Buffer may lead to data
1241 corruption. This workaround sets a specific bit in the diagnostic
1242 register of the Cortex-A9 which disables the Store Buffer
1243 optimisation, preventing the defect from occurring. This has no
1244 visible impact on the overall performance or power consumption of the
1247 config ARM_ERRATA_751472
1248 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1249 depends on CPU_V7 && SMP
1251 This option enables the workaround for the 751472 Cortex-A9 (prior
1252 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1253 completion of a following broadcasted operation if the second
1254 operation is received by a CPU before the ICIALLUIS has completed,
1255 potentially leading to corrupted entries in the cache or TLB.
1257 config ARM_ERRATA_753970
1258 bool "ARM errata: cache sync operation may be faulty"
1259 depends on CACHE_PL310
1261 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1263 Under some condition the effect of cache sync operation on
1264 the store buffer still remains when the operation completes.
1265 This means that the store buffer is always asked to drain and
1266 this prevents it from merging any further writes. The workaround
1267 is to replace the normal offset of cache sync operation (0x730)
1268 by another offset targeting an unmapped PL310 register 0x740.
1269 This has the same effect as the cache sync operation: store buffer
1270 drain and waiting for all buffers empty.
1272 config ARM_ERRATA_754322
1273 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1276 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1277 r3p*) erratum. A speculative memory access may cause a page table walk
1278 which starts prior to an ASID switch but completes afterwards. This
1279 can populate the micro-TLB with a stale entry which may be hit with
1280 the new ASID. This workaround places two dsb instructions in the mm
1281 switching code so that no page table walks can cross the ASID switch.
1283 config ARM_ERRATA_754327
1284 bool "ARM errata: no automatic Store Buffer drain"
1285 depends on CPU_V7 && SMP
1287 This option enables the workaround for the 754327 Cortex-A9 (prior to
1288 r2p0) erratum. The Store Buffer does not have any automatic draining
1289 mechanism and therefore a livelock may occur if an external agent
1290 continuously polls a memory location waiting to observe an update.
1291 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1292 written polling loops from denying visibility of updates to memory.
1296 source "arch/arm/common/Kconfig"
1306 Find out whether you have ISA slots on your motherboard. ISA is the
1307 name of a bus system, i.e. the way the CPU talks to the other stuff
1308 inside your box. Other bus systems are PCI, EISA, MicroChannel
1309 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1310 newer boards don't support it. If you have ISA, say Y, otherwise N.
1312 # Select ISA DMA controller support
1317 # Select ISA DMA interface
1322 bool "PCI support" if MIGHT_HAVE_PCI
1324 Find out whether you have a PCI motherboard. PCI is the name of a
1325 bus system, i.e. the way the CPU talks to the other stuff inside
1326 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1327 VESA. If you have PCI, say Y, otherwise N.
1333 config PCI_NANOENGINE
1334 bool "BSE nanoEngine PCI support"
1335 depends on SA1100_NANOENGINE
1337 Enable PCI on the BSE nanoEngine board.
1342 # Select the host bridge type
1343 config PCI_HOST_VIA82C505
1345 depends on PCI && ARCH_SHARK
1348 config PCI_HOST_ITE8152
1350 depends on PCI && MACH_ARMCORE
1354 source "drivers/pci/Kconfig"
1356 source "drivers/pcmcia/Kconfig"
1360 menu "Kernel Features"
1362 source "kernel/time/Kconfig"
1365 bool "Symmetric Multi-Processing"
1366 depends on CPU_V6K || CPU_V7
1367 depends on GENERIC_CLOCKEVENTS
1368 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1369 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1370 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1371 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1372 select USE_GENERIC_SMP_HELPERS
1373 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1375 This enables support for systems with more than one CPU. If you have
1376 a system with only one CPU, like most personal computers, say N. If
1377 you have a system with more than one CPU, say Y.
1379 If you say N here, the kernel will run on single and multiprocessor
1380 machines, but will use only one CPU of a multiprocessor machine. If
1381 you say Y here, the kernel will run on many, but not all, single
1382 processor machines. On a single processor machine, the kernel will
1383 run faster if you say N here.
1385 See also <file:Documentation/i386/IO-APIC.txt>,
1386 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1387 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1389 If you don't know what to do here, say N.
1392 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1393 depends on EXPERIMENTAL
1394 depends on SMP && !XIP_KERNEL
1397 SMP kernels contain instructions which fail on non-SMP processors.
1398 Enabling this option allows the kernel to modify itself to make
1399 these instructions safe. Disabling it allows about 1K of space
1402 If you don't know what to do here, say Y.
1407 This option enables support for the ARM system coherency unit
1414 This options enables support for the ARM timer and watchdog unit
1417 prompt "Memory split"
1420 Select the desired split between kernel and user memory.
1422 If you are not absolutely sure what you are doing, leave this
1426 bool "3G/1G user/kernel split"
1428 bool "2G/2G user/kernel split"
1430 bool "1G/3G user/kernel split"
1435 default 0x40000000 if VMSPLIT_1G
1436 default 0x80000000 if VMSPLIT_2G
1440 int "Maximum number of CPUs (2-32)"
1446 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1447 depends on SMP && HOTPLUG && EXPERIMENTAL
1449 Say Y here to experiment with turning CPUs off and on. CPUs
1450 can be controlled through /sys/devices/system/cpu.
1453 bool "Use local timer interrupts"
1456 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1458 Enable support for local timers on SMP platforms, rather then the
1459 legacy IPI broadcast method. Local timers allows the system
1460 accounting to be spread across the timer interval, preventing a
1461 "thundering herd" at every timer tick.
1463 source kernel/Kconfig.preempt
1467 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1468 ARCH_S5PV210 || ARCH_EXYNOS4
1469 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1470 default AT91_TIMER_HZ if ARCH_AT91
1471 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1474 config THUMB2_KERNEL
1475 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1476 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1478 select ARM_ASM_UNIFIED
1480 By enabling this option, the kernel will be compiled in
1481 Thumb-2 mode. A compiler/assembler that understand the unified
1482 ARM-Thumb syntax is needed.
1486 config THUMB2_AVOID_R_ARM_THM_JUMP11
1487 bool "Work around buggy Thumb-2 short branch relocations in gas"
1488 depends on THUMB2_KERNEL && MODULES
1491 Various binutils versions can resolve Thumb-2 branches to
1492 locally-defined, preemptible global symbols as short-range "b.n"
1493 branch instructions.
1495 This is a problem, because there's no guarantee the final
1496 destination of the symbol, or any candidate locations for a
1497 trampoline, are within range of the branch. For this reason, the
1498 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1499 relocation in modules at all, and it makes little sense to add
1502 The symptom is that the kernel fails with an "unsupported
1503 relocation" error when loading some modules.
1505 Until fixed tools are available, passing
1506 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1507 code which hits this problem, at the cost of a bit of extra runtime
1508 stack usage in some cases.
1510 The problem is described in more detail at:
1511 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1513 Only Thumb-2 kernels are affected.
1515 Unless you are sure your tools don't have this problem, say Y.
1517 config ARM_ASM_UNIFIED
1521 bool "Use the ARM EABI to compile the kernel"
1523 This option allows for the kernel to be compiled using the latest
1524 ARM ABI (aka EABI). This is only useful if you are using a user
1525 space environment that is also compiled with EABI.
1527 Since there are major incompatibilities between the legacy ABI and
1528 EABI, especially with regard to structure member alignment, this
1529 option also changes the kernel syscall calling convention to
1530 disambiguate both ABIs and allow for backward compatibility support
1531 (selected with CONFIG_OABI_COMPAT).
1533 To use this you need GCC version 4.0.0 or later.
1536 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1537 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1540 This option preserves the old syscall interface along with the
1541 new (ARM EABI) one. It also provides a compatibility layer to
1542 intercept syscalls that have structure arguments which layout
1543 in memory differs between the legacy ABI and the new ARM EABI
1544 (only for non "thumb" binaries). This option adds a tiny
1545 overhead to all syscalls and produces a slightly larger kernel.
1546 If you know you'll be using only pure EABI user space then you
1547 can say N here. If this option is not selected and you attempt
1548 to execute a legacy ABI binary then the result will be
1549 UNPREDICTABLE (in fact it can be predicted that it won't work
1550 at all). If in doubt say Y.
1552 config ARCH_HAS_HOLES_MEMORYMODEL
1555 config ARCH_SPARSEMEM_ENABLE
1558 config ARCH_SPARSEMEM_DEFAULT
1559 def_bool ARCH_SPARSEMEM_ENABLE
1561 config ARCH_SELECT_MEMORY_MODEL
1562 def_bool ARCH_SPARSEMEM_ENABLE
1564 config HAVE_ARCH_PFN_VALID
1565 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1568 bool "High Memory Support"
1571 The address space of ARM processors is only 4 Gigabytes large
1572 and it has to accommodate user address space, kernel address
1573 space as well as some memory mapped IO. That means that, if you
1574 have a large amount of physical memory and/or IO, not all of the
1575 memory can be "permanently mapped" by the kernel. The physical
1576 memory that is not permanently mapped is called "high memory".
1578 Depending on the selected kernel/user memory split, minimum
1579 vmalloc space and actual amount of RAM, you may not need this
1580 option which should result in a slightly faster kernel.
1585 bool "Allocate 2nd-level pagetables from highmem"
1588 config HW_PERF_EVENTS
1589 bool "Enable hardware performance counter support for perf events"
1590 depends on PERF_EVENTS && CPU_HAS_PMU
1593 Enable hardware performance counter support for perf events. If
1594 disabled, perf events will use software events only.
1598 config FORCE_MAX_ZONEORDER
1599 int "Maximum zone order" if ARCH_SHMOBILE
1600 range 11 64 if ARCH_SHMOBILE
1601 default "9" if SA1111
1604 The kernel memory allocator divides physically contiguous memory
1605 blocks into "zones", where each zone is a power of two number of
1606 pages. This option selects the largest power of two that the kernel
1607 keeps in the memory allocator. If you need to allocate very large
1608 blocks of physically contiguous memory, then you may need to
1609 increase this value.
1611 This config option is actually maximum order plus one. For example,
1612 a value of 11 means that the largest free memory block is 2^10 pages.
1615 bool "Timer and CPU usage LEDs"
1616 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1617 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1618 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1619 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1620 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1621 ARCH_AT91 || ARCH_DAVINCI || \
1622 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1624 If you say Y here, the LEDs on your machine will be used
1625 to provide useful information about your current system status.
1627 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1628 be able to select which LEDs are active using the options below. If
1629 you are compiling a kernel for the EBSA-110 or the LART however, the
1630 red LED will simply flash regularly to indicate that the system is
1631 still functional. It is safe to say Y here if you have a CATS
1632 system, but the driver will do nothing.
1635 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1636 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1637 || MACH_OMAP_PERSEUS2
1639 depends on !GENERIC_CLOCKEVENTS
1640 default y if ARCH_EBSA110
1642 If you say Y here, one of the system LEDs (the green one on the
1643 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1644 will flash regularly to indicate that the system is still
1645 operational. This is mainly useful to kernel hackers who are
1646 debugging unstable kernels.
1648 The LART uses the same LED for both Timer LED and CPU usage LED
1649 functions. You may choose to use both, but the Timer LED function
1650 will overrule the CPU usage LED.
1653 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1655 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1656 || MACH_OMAP_PERSEUS2
1659 If you say Y here, the red LED will be used to give a good real
1660 time indication of CPU usage, by lighting whenever the idle task
1661 is not currently executing.
1663 The LART uses the same LED for both Timer LED and CPU usage LED
1664 functions. You may choose to use both, but the Timer LED function
1665 will overrule the CPU usage LED.
1667 config ALIGNMENT_TRAP
1669 depends on CPU_CP15_MMU
1670 default y if !ARCH_EBSA110
1671 select HAVE_PROC_CPU if PROC_FS
1673 ARM processors cannot fetch/store information which is not
1674 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1675 address divisible by 4. On 32-bit ARM processors, these non-aligned
1676 fetch/store instructions will be emulated in software if you say
1677 here, which has a severe performance impact. This is necessary for
1678 correct operation of some network protocols. With an IP-only
1679 configuration it is safe to say N, otherwise say Y.
1681 config UACCESS_WITH_MEMCPY
1682 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1683 depends on MMU && EXPERIMENTAL
1684 default y if CPU_FEROCEON
1686 Implement faster copy_to_user and clear_user methods for CPU
1687 cores where a 8-word STM instruction give significantly higher
1688 memory write throughput than a sequence of individual 32bit stores.
1690 A possible side effect is a slight increase in scheduling latency
1691 between threads sharing the same address space if they invoke
1692 such copy operations with large buffers.
1694 However, if the CPU data cache is using a write-allocate mode,
1695 this option is unlikely to provide any performance gain.
1699 prompt "Enable seccomp to safely compute untrusted bytecode"
1701 This kernel feature is useful for number crunching applications
1702 that may need to compute untrusted bytecode during their
1703 execution. By using pipes or other transports made available to
1704 the process as file descriptors supporting the read/write
1705 syscalls, it's possible to isolate those applications in
1706 their own address space using seccomp. Once seccomp is
1707 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1708 and the task is only allowed to execute a few safe syscalls
1709 defined by each seccomp mode.
1711 config CC_STACKPROTECTOR
1712 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1713 depends on EXPERIMENTAL
1715 This option turns on the -fstack-protector GCC feature. This
1716 feature puts, at the beginning of functions, a canary value on
1717 the stack just before the return address, and validates
1718 the value just before actually returning. Stack based buffer
1719 overflows (that need to overwrite this return address) now also
1720 overwrite the canary, which gets detected and the attack is then
1721 neutralized via a kernel panic.
1722 This feature requires gcc version 4.2 or above.
1724 config DEPRECATED_PARAM_STRUCT
1725 bool "Provide old way to pass kernel parameters"
1727 This was deprecated in 2001 and announced to live on for 5 years.
1728 Some old boot loaders still use this way.
1735 bool "Flattened Device Tree support"
1737 select OF_EARLY_FLATTREE
1740 Include support for flattened device tree machine descriptions.
1742 # Compressed boot loader in ROM. Yes, we really want to ask about
1743 # TEXT and BSS so we preserve their values in the config files.
1744 config ZBOOT_ROM_TEXT
1745 hex "Compressed ROM boot loader base address"
1748 The physical address at which the ROM-able zImage is to be
1749 placed in the target. Platforms which normally make use of
1750 ROM-able zImage formats normally set this to a suitable
1751 value in their defconfig file.
1753 If ZBOOT_ROM is not enabled, this has no effect.
1755 config ZBOOT_ROM_BSS
1756 hex "Compressed ROM boot loader BSS address"
1759 The base address of an area of read/write memory in the target
1760 for the ROM-able zImage which must be available while the
1761 decompressor is running. It must be large enough to hold the
1762 entire decompressed kernel plus an additional 128 KiB.
1763 Platforms which normally make use of ROM-able zImage formats
1764 normally set this to a suitable value in their defconfig file.
1766 If ZBOOT_ROM is not enabled, this has no effect.
1769 bool "Compressed boot loader in ROM/flash"
1770 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1772 Say Y here if you intend to execute your compressed kernel image
1773 (zImage) directly from ROM or flash. If unsure, say N.
1776 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1777 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1778 default ZBOOT_ROM_NONE
1780 Include experimental SD/MMC loading code in the ROM-able zImage.
1781 With this enabled it is possible to write the the ROM-able zImage
1782 kernel image to an MMC or SD card and boot the kernel straight
1783 from the reset vector. At reset the processor Mask ROM will load
1784 the first part of the the ROM-able zImage which in turn loads the
1785 rest the kernel image to RAM.
1787 config ZBOOT_ROM_NONE
1788 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1790 Do not load image from SD or MMC
1792 config ZBOOT_ROM_MMCIF
1793 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1795 Load image from MMCIF hardware block.
1797 config ZBOOT_ROM_SH_MOBILE_SDHI
1798 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1800 Load image from SDHI hardware block
1805 string "Default kernel command string"
1808 On some architectures (EBSA110 and CATS), there is currently no way
1809 for the boot loader to pass arguments to the kernel. For these
1810 architectures, you should supply some command-line options at build
1811 time by entering them here. As a minimum, you should specify the
1812 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1815 prompt "Kernel command line type" if CMDLINE != ""
1816 default CMDLINE_FROM_BOOTLOADER
1818 config CMDLINE_FROM_BOOTLOADER
1819 bool "Use bootloader kernel arguments if available"
1821 Uses the command-line options passed by the boot loader. If
1822 the boot loader doesn't provide any, the default kernel command
1823 string provided in CMDLINE will be used.
1825 config CMDLINE_EXTEND
1826 bool "Extend bootloader kernel arguments"
1828 The command-line arguments provided by the boot loader will be
1829 appended to the default kernel command string.
1831 config CMDLINE_FORCE
1832 bool "Always use the default kernel command string"
1834 Always use the default kernel command string, even if the boot
1835 loader passes other arguments to the kernel.
1836 This is useful if you cannot or don't want to change the
1837 command-line options your boot loader passes to the kernel.
1841 bool "Kernel Execute-In-Place from ROM"
1842 depends on !ZBOOT_ROM
1844 Execute-In-Place allows the kernel to run from non-volatile storage
1845 directly addressable by the CPU, such as NOR flash. This saves RAM
1846 space since the text section of the kernel is not loaded from flash
1847 to RAM. Read-write sections, such as the data section and stack,
1848 are still copied to RAM. The XIP kernel is not compressed since
1849 it has to run directly from flash, so it will take more space to
1850 store it. The flash address used to link the kernel object files,
1851 and for storing it, is configuration dependent. Therefore, if you
1852 say Y here, you must know the proper physical address where to
1853 store the kernel image depending on your own flash memory usage.
1855 Also note that the make target becomes "make xipImage" rather than
1856 "make zImage" or "make Image". The final kernel binary to put in
1857 ROM memory will be arch/arm/boot/xipImage.
1861 config XIP_PHYS_ADDR
1862 hex "XIP Kernel Physical Location"
1863 depends on XIP_KERNEL
1864 default "0x00080000"
1866 This is the physical address in your flash memory the kernel will
1867 be linked for and stored to. This address is dependent on your
1871 bool "Kexec system call (EXPERIMENTAL)"
1872 depends on EXPERIMENTAL
1874 kexec is a system call that implements the ability to shutdown your
1875 current kernel, and to start another kernel. It is like a reboot
1876 but it is independent of the system firmware. And like a reboot
1877 you can start any kernel with it, not just Linux.
1879 It is an ongoing process to be certain the hardware in a machine
1880 is properly shutdown, so do not be surprised if this code does not
1881 initially work for you. It may help to enable device hotplugging
1885 bool "Export atags in procfs"
1889 Should the atags used to boot the kernel be exported in an "atags"
1890 file in procfs. Useful with kexec.
1893 bool "Build kdump crash kernel (EXPERIMENTAL)"
1894 depends on EXPERIMENTAL
1896 Generate crash dump after being started by kexec. This should
1897 be normally only set in special crash dump kernels which are
1898 loaded in the main kernel with kexec-tools into a specially
1899 reserved region and then later executed after a crash by
1900 kdump/kexec. The crash dump kernel must be compiled to a
1901 memory address not used by the main kernel
1903 For more details see Documentation/kdump/kdump.txt
1905 config AUTO_ZRELADDR
1906 bool "Auto calculation of the decompressed kernel image address"
1907 depends on !ZBOOT_ROM && !ARCH_U300
1909 ZRELADDR is the physical address where the decompressed kernel
1910 image will be placed. If AUTO_ZRELADDR is selected, the address
1911 will be determined at run-time by masking the current IP with
1912 0xf8000000. This assumes the zImage being placed in the first 128MB
1913 from start of memory.
1917 menu "CPU Power Management"
1921 source "drivers/cpufreq/Kconfig"
1924 tristate "CPUfreq driver for i.MX CPUs"
1925 depends on ARCH_MXC && CPU_FREQ
1927 This enables the CPUfreq driver for i.MX CPUs.
1929 config CPU_FREQ_SA1100
1932 config CPU_FREQ_SA1110
1935 config CPU_FREQ_INTEGRATOR
1936 tristate "CPUfreq driver for ARM Integrator CPUs"
1937 depends on ARCH_INTEGRATOR && CPU_FREQ
1940 This enables the CPUfreq driver for ARM Integrator CPUs.
1942 For details, take a look at <file:Documentation/cpu-freq>.
1948 depends on CPU_FREQ && ARCH_PXA && PXA25x
1950 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1955 Internal configuration node for common cpufreq on Samsung SoC
1957 config CPU_FREQ_S3C24XX
1958 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1959 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1962 This enables the CPUfreq driver for the Samsung S3C24XX family
1965 For details, take a look at <file:Documentation/cpu-freq>.
1969 config CPU_FREQ_S3C24XX_PLL
1970 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1971 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1973 Compile in support for changing the PLL frequency from the
1974 S3C24XX series CPUfreq driver. The PLL takes time to settle
1975 after a frequency change, so by default it is not enabled.
1977 This also means that the PLL tables for the selected CPU(s) will
1978 be built which may increase the size of the kernel image.
1980 config CPU_FREQ_S3C24XX_DEBUG
1981 bool "Debug CPUfreq Samsung driver core"
1982 depends on CPU_FREQ_S3C24XX
1984 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1986 config CPU_FREQ_S3C24XX_IODEBUG
1987 bool "Debug CPUfreq Samsung driver IO timing"
1988 depends on CPU_FREQ_S3C24XX
1990 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1992 config CPU_FREQ_S3C24XX_DEBUGFS
1993 bool "Export debugfs for CPUFreq"
1994 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1996 Export status information via debugfs.
2000 source "drivers/cpuidle/Kconfig"
2004 menu "Floating point emulation"
2006 comment "At least one emulation must be selected"
2009 bool "NWFPE math emulation"
2010 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2012 Say Y to include the NWFPE floating point emulator in the kernel.
2013 This is necessary to run most binaries. Linux does not currently
2014 support floating point hardware so you need to say Y here even if
2015 your machine has an FPA or floating point co-processor podule.
2017 You may say N here if you are going to load the Acorn FPEmulator
2018 early in the bootup.
2021 bool "Support extended precision"
2022 depends on FPE_NWFPE
2024 Say Y to include 80-bit support in the kernel floating-point
2025 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2026 Note that gcc does not generate 80-bit operations by default,
2027 so in most cases this option only enlarges the size of the
2028 floating point emulator without any good reason.
2030 You almost surely want to say N here.
2033 bool "FastFPE math emulation (EXPERIMENTAL)"
2034 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2036 Say Y here to include the FAST floating point emulator in the kernel.
2037 This is an experimental much faster emulator which now also has full
2038 precision for the mantissa. It does not support any exceptions.
2039 It is very simple, and approximately 3-6 times faster than NWFPE.
2041 It should be sufficient for most programs. It may be not suitable
2042 for scientific calculations, but you have to check this for yourself.
2043 If you do not feel you need a faster FP emulation you should better
2047 bool "VFP-format floating point maths"
2048 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2050 Say Y to include VFP support code in the kernel. This is needed
2051 if your hardware includes a VFP unit.
2053 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2054 release notes and additional status information.
2056 Say N if your target does not have VFP hardware.
2064 bool "Advanced SIMD (NEON) Extension support"
2065 depends on VFPv3 && CPU_V7
2067 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2072 menu "Userspace binary formats"
2074 source "fs/Kconfig.binfmt"
2077 tristate "RISC OS personality"
2080 Say Y here to include the kernel code necessary if you want to run
2081 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2082 experimental; if this sounds frightening, say N and sleep in peace.
2083 You can also say M here to compile this support as a module (which
2084 will be called arthur).
2088 menu "Power management options"
2090 source "kernel/power/Kconfig"
2092 config ARCH_SUSPEND_POSSIBLE
2093 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2094 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2095 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2100 source "net/Kconfig"
2102 source "drivers/Kconfig"
2106 source "arch/arm/Kconfig.debug"
2108 source "security/Kconfig"
2110 source "crypto/Kconfig"
2112 source "lib/Kconfig"