5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 source "init/Kconfig"
231 source "kernel/Kconfig.freezer"
236 bool "MMU-based Paged Memory Management Support"
239 Select if you want MMU-based virtualised addressing space
240 support by paged memory management. If unsure, say 'Y'.
243 # The "ARM system type" choice list is ordered alphabetically by option
244 # text. Please add new entries in the option alphabetic order.
247 prompt "ARM system type"
248 default ARCH_VERSATILE
250 config ARCH_INTEGRATOR
251 bool "ARM Ltd. Integrator family"
253 select ARCH_HAS_CPUFREQ
255 select HAVE_MACH_CLKDEV
257 select GENERIC_CLOCKEVENTS
258 select PLAT_VERSATILE
259 select PLAT_VERSATILE_FPGA_IRQ
260 select NEED_MACH_MEMORY_H
262 Support for ARM's Integrator platform.
265 bool "ARM Ltd. RealView family"
268 select HAVE_MACH_CLKDEV
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select ARM_TIMER_SP804
275 select GPIO_PL061 if GPIOLIB
276 select NEED_MACH_MEMORY_H
278 This enables support for ARM Ltd RealView boards.
280 config ARCH_VERSATILE
281 bool "ARM Ltd. Versatile family"
285 select HAVE_MACH_CLKDEV
287 select GENERIC_CLOCKEVENTS
288 select ARCH_WANT_OPTIONAL_GPIOLIB
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
291 select PLAT_VERSATILE_FPGA_IRQ
292 select ARM_TIMER_SP804
294 This enables support for ARM Ltd Versatile board.
297 bool "ARM Ltd. Versatile Express family"
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select ARM_TIMER_SP804
302 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
305 select HAVE_PATA_PLATFORM
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
310 This enables support for the ARM Ltd Versatile Express boards.
314 select ARCH_REQUIRE_GPIOLIB
318 This enables support for systems based on the Atmel AT91RM9200,
319 AT91SAM9 and AT91CAP9 processors.
322 bool "Broadcom BCMRING"
326 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 Support for Broadcom's BCMRing platform.
334 bool "Calxeda Highbank-based"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
345 Support for the Calxeda Highbank SoC based boards.
348 bool "Cirrus Logic CLPS711x/EP721x-based"
350 select ARCH_USES_GETTIMEOFFSET
351 select NEED_MACH_MEMORY_H
353 Support for Cirrus Logic 711x/721x based boards.
356 bool "Cavium Networks CNS3XXX family"
358 select GENERIC_CLOCKEVENTS
360 select MIGHT_HAVE_PCI
361 select PCI_DOMAINS if PCI
363 Support for Cavium Networks CNS3XXX platform.
366 bool "Cortina Systems Gemini"
368 select ARCH_REQUIRE_GPIOLIB
369 select ARCH_USES_GETTIMEOFFSET
371 Support for the Cortina Systems Gemini family SoCs
374 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
378 select GENERIC_CLOCKEVENTS
380 select GENERIC_IRQ_CHIP
384 Support for CSR SiRFSoC ARM Cortex A9 Platform
391 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_MEMORY_H
394 This is an evaluation board for the StrongARM processor available
395 from Digital. It has limited hardware on-board, including an
396 Ethernet interface, two PCMCIA sockets, two serial ports and a
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_HAS_HOLES_MEMORYMODEL
407 select ARCH_USES_GETTIMEOFFSET
410 This enables support for the Cirrus EP93xx series of CPUs.
412 config ARCH_FOOTBRIDGE
416 select GENERIC_CLOCKEVENTS
417 select NEED_MACH_MEMORY_H
419 Support for systems based on the DC21285 companion chip
420 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
423 bool "Freescale MXC/iMX-based"
424 select GENERIC_CLOCKEVENTS
425 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_IRQ_CHIP
429 select HAVE_SCHED_CLOCK
431 Support for Freescale MXC/iMX-based family of processors
434 bool "Freescale MXS-based"
435 select GENERIC_CLOCKEVENTS
436 select ARCH_REQUIRE_GPIOLIB
440 Support for Freescale MXS-based family of processors
443 bool "Hilscher NetX based"
447 select GENERIC_CLOCKEVENTS
449 This enables support for systems based on the Hilscher NetX Soc
452 bool "Hynix HMS720x-based"
455 select ARCH_USES_GETTIMEOFFSET
457 This enables support for systems based on the Hynix HMS720x
465 select ARCH_SUPPORTS_MSI
467 select NEED_MACH_MEMORY_H
469 Support for Intel's IOP13XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
479 Support for Intel's 80219 and IOP32X (XScale) family of
488 select ARCH_REQUIRE_GPIOLIB
490 Support for Intel's IOP33X (XScale) family of processors.
497 select ARCH_USES_GETTIMEOFFSET
498 select NEED_MACH_MEMORY_H
500 Support for Intel's IXP23xx (XScale) family of processors.
503 bool "IXP2400/2800-based"
507 select ARCH_USES_GETTIMEOFFSET
508 select NEED_MACH_MEMORY_H
510 Support for Intel's IXP2400/2800 (XScale) family of processors.
518 select GENERIC_CLOCKEVENTS
519 select HAVE_SCHED_CLOCK
520 select MIGHT_HAVE_PCI
521 select DMABOUNCE if PCI
523 Support for Intel's IXP4XX (XScale) family of processors.
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 Support for the Marvell Dove SoC 88AP510
536 bool "Marvell Kirkwood"
539 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
543 Support for the following Marvell Kirkwood series SoCs:
544 88F6180, 88F6192 and 88F6281.
550 select ARCH_REQUIRE_GPIOLIB
553 select USB_ARCH_HAS_OHCI
556 select GENERIC_CLOCKEVENTS
558 Support for the NXP LPC32XX family of processors
561 bool "Marvell MV78xx0"
564 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
568 Support for the following Marvell MV78xx0 series SoCs:
576 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
590 select HAVE_SCHED_CLOCK
595 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
601 select ARCH_USES_GETTIMEOFFSET
602 select NEED_MACH_MEMORY_H
604 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
605 System-on-Chip devices.
608 bool "Nuvoton W90X900 CPU"
610 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_CLOCKEVENTS
615 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
616 At present, the w90x900 has been renamed nuc900, regarding
617 the ARM series product line, you can login the following
618 link address to know more.
620 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
621 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
624 bool "Nuvoton NUC93X CPU"
628 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
629 low-power and high performance MPEG-4/JPEG multimedia controller chip.
636 select GENERIC_CLOCKEVENTS
639 select HAVE_SCHED_CLOCK
640 select ARCH_HAS_CPUFREQ
642 This enables support for NVIDIA Tegra based systems (Tegra APX,
643 Tegra 6xx and Tegra 2 series).
646 bool "Philips Nexperia PNX4008 Mobile"
649 select ARCH_USES_GETTIMEOFFSET
651 This enables support for Philips PNX4008 mobile platform.
654 bool "PXA2xx/PXA3xx-based"
657 select ARCH_HAS_CPUFREQ
660 select ARCH_REQUIRE_GPIOLIB
661 select GENERIC_CLOCKEVENTS
662 select HAVE_SCHED_CLOCK
667 select MULTI_IRQ_HANDLER
669 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
674 select GENERIC_CLOCKEVENTS
675 select ARCH_REQUIRE_GPIOLIB
678 Support for Qualcomm MSM/QSD based systems. This runs on the
679 apps processor of the MSM/QSD and depends on a shared memory
680 interface to the modem processor which runs the baseband
681 stack and controls some vital subsystems
682 (clock and power control, etc).
685 bool "Renesas SH-Mobile / R-Mobile"
688 select HAVE_MACH_CLKDEV
689 select GENERIC_CLOCKEVENTS
692 select MULTI_IRQ_HANDLER
693 select PM_GENERIC_DOMAINS if PM
694 select NEED_MACH_MEMORY_H
696 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
703 select ARCH_MAY_HAVE_PC_FDC
704 select HAVE_PATA_PLATFORM
707 select ARCH_SPARSEMEM_ENABLE
708 select ARCH_USES_GETTIMEOFFSET
709 select NEED_MACH_MEMORY_H
711 On the Acorn Risc-PC, Linux can support the internal IDE disk and
712 CD-ROM interface, serial and parallel port, and the floppy drive.
719 select ARCH_SPARSEMEM_ENABLE
721 select ARCH_HAS_CPUFREQ
723 select GENERIC_CLOCKEVENTS
725 select HAVE_SCHED_CLOCK
727 select ARCH_REQUIRE_GPIOLIB
728 select NEED_MACH_MEMORY_H
730 Support for StrongARM 11x0 based boards.
733 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
735 select ARCH_HAS_CPUFREQ
738 select ARCH_USES_GETTIMEOFFSET
739 select HAVE_S3C2410_I2C if I2C
741 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
742 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
743 the Samsung SMDK2410 development board (and derivatives).
745 Note, the S3C2416 and the S3C2450 are so close that they even share
746 the same SoC ID code. This means that there is no separate machine
747 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
750 bool "Samsung S3C64XX"
757 select ARCH_USES_GETTIMEOFFSET
758 select ARCH_HAS_CPUFREQ
759 select ARCH_REQUIRE_GPIOLIB
760 select SAMSUNG_CLKSRC
761 select SAMSUNG_IRQ_VIC_TIMER
762 select SAMSUNG_IRQ_UART
763 select S3C_GPIO_TRACK
764 select S3C_GPIO_PULL_UPDOWN
765 select S3C_GPIO_CFG_S3C24XX
766 select S3C_GPIO_CFG_S3C64XX
768 select USB_ARCH_HAS_OHCI
769 select SAMSUNG_GPIOLIB_4BIT
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
773 Samsung S3C64XX series based systems
776 bool "Samsung S5P6440 S5P6450"
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 select GENERIC_CLOCKEVENTS
784 select HAVE_SCHED_CLOCK
785 select HAVE_S3C2410_I2C if I2C
786 select HAVE_S3C_RTC if RTC_CLASS
788 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
792 bool "Samsung S5PC100"
797 select ARM_L1_CACHE_SHIFT_6
798 select ARCH_USES_GETTIMEOFFSET
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C_RTC if RTC_CLASS
801 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 Samsung S5PC100 series based systems
806 bool "Samsung S5PV210/S5PC110"
808 select ARCH_SPARSEMEM_ENABLE
809 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARM_L1_CACHE_SHIFT_6
815 select ARCH_HAS_CPUFREQ
816 select GENERIC_CLOCKEVENTS
817 select HAVE_SCHED_CLOCK
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C_RTC if RTC_CLASS
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 select NEED_MACH_MEMORY_H
823 Samsung S5PV210/S5PC110 series based systems
826 bool "Samsung EXYNOS4"
828 select ARCH_SPARSEMEM_ENABLE
829 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_HAS_CPUFREQ
834 select GENERIC_CLOCKEVENTS
835 select HAVE_S3C_RTC if RTC_CLASS
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
838 select NEED_MACH_MEMORY_H
840 Samsung EXYNOS4 series based systems
849 select ARCH_USES_GETTIMEOFFSET
850 select NEED_MACH_MEMORY_H
852 Support for the StrongARM based Digital DNARD machine, also known
853 as "Shark" (<http://www.shark-linux.de/shark.html>).
856 bool "Telechips TCC ARM926-based systems"
861 select GENERIC_CLOCKEVENTS
863 Support for Telechips TCC ARM926-based systems.
866 bool "ST-Ericsson U300 Series"
870 select HAVE_SCHED_CLOCK
874 select GENERIC_CLOCKEVENTS
876 select HAVE_MACH_CLKDEV
878 select ARCH_REQUIRE_GPIOLIB
879 select NEED_MACH_MEMORY_H
881 Support for ST-Ericsson U300 series mobile platforms.
884 bool "ST-Ericsson U8500 Series"
887 select GENERIC_CLOCKEVENTS
889 select ARCH_REQUIRE_GPIOLIB
890 select ARCH_HAS_CPUFREQ
892 Support for ST-Ericsson's Ux500 architecture
895 bool "STMicroelectronics Nomadik"
900 select GENERIC_CLOCKEVENTS
901 select ARCH_REQUIRE_GPIOLIB
903 Support for the Nomadik platform by ST-Ericsson
907 select GENERIC_CLOCKEVENTS
908 select ARCH_REQUIRE_GPIOLIB
912 select GENERIC_ALLOCATOR
913 select GENERIC_IRQ_CHIP
914 select ARCH_HAS_HOLES_MEMORYMODEL
916 Support for TI's DaVinci platform.
921 select ARCH_REQUIRE_GPIOLIB
922 select ARCH_HAS_CPUFREQ
924 select GENERIC_CLOCKEVENTS
925 select HAVE_SCHED_CLOCK
926 select ARCH_HAS_HOLES_MEMORYMODEL
928 Support for TI's OMAP platform (OMAP1/2/3/4).
933 select ARCH_REQUIRE_GPIOLIB
936 select GENERIC_CLOCKEVENTS
939 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
942 bool "VIA/WonderMedia 85xx"
945 select ARCH_HAS_CPUFREQ
946 select GENERIC_CLOCKEVENTS
947 select ARCH_REQUIRE_GPIOLIB
950 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
953 bool "Xilinx Zynq ARM Cortex A9 Platform"
956 select GENERIC_CLOCKEVENTS
963 Support for Xilinx Zynq ARM Cortex A9 Platform
967 # This is sorted alphabetically by mach-* pathname. However, plat-*
968 # Kconfigs may be included either alphabetically (according to the
969 # plat- suffix) or along side the corresponding mach-* source.
971 source "arch/arm/mach-at91/Kconfig"
973 source "arch/arm/mach-bcmring/Kconfig"
975 source "arch/arm/mach-clps711x/Kconfig"
977 source "arch/arm/mach-cns3xxx/Kconfig"
979 source "arch/arm/mach-davinci/Kconfig"
981 source "arch/arm/mach-dove/Kconfig"
983 source "arch/arm/mach-ep93xx/Kconfig"
985 source "arch/arm/mach-footbridge/Kconfig"
987 source "arch/arm/mach-gemini/Kconfig"
989 source "arch/arm/mach-h720x/Kconfig"
991 source "arch/arm/mach-integrator/Kconfig"
993 source "arch/arm/mach-iop32x/Kconfig"
995 source "arch/arm/mach-iop33x/Kconfig"
997 source "arch/arm/mach-iop13xx/Kconfig"
999 source "arch/arm/mach-ixp4xx/Kconfig"
1001 source "arch/arm/mach-ixp2000/Kconfig"
1003 source "arch/arm/mach-ixp23xx/Kconfig"
1005 source "arch/arm/mach-kirkwood/Kconfig"
1007 source "arch/arm/mach-ks8695/Kconfig"
1009 source "arch/arm/mach-lpc32xx/Kconfig"
1011 source "arch/arm/mach-msm/Kconfig"
1013 source "arch/arm/mach-mv78xx0/Kconfig"
1015 source "arch/arm/plat-mxc/Kconfig"
1017 source "arch/arm/mach-mxs/Kconfig"
1019 source "arch/arm/mach-netx/Kconfig"
1021 source "arch/arm/mach-nomadik/Kconfig"
1022 source "arch/arm/plat-nomadik/Kconfig"
1024 source "arch/arm/mach-nuc93x/Kconfig"
1026 source "arch/arm/plat-omap/Kconfig"
1028 source "arch/arm/mach-omap1/Kconfig"
1030 source "arch/arm/mach-omap2/Kconfig"
1032 source "arch/arm/mach-orion5x/Kconfig"
1034 source "arch/arm/mach-pxa/Kconfig"
1035 source "arch/arm/plat-pxa/Kconfig"
1037 source "arch/arm/mach-mmp/Kconfig"
1039 source "arch/arm/mach-realview/Kconfig"
1041 source "arch/arm/mach-sa1100/Kconfig"
1043 source "arch/arm/plat-samsung/Kconfig"
1044 source "arch/arm/plat-s3c24xx/Kconfig"
1045 source "arch/arm/plat-s5p/Kconfig"
1047 source "arch/arm/plat-spear/Kconfig"
1049 source "arch/arm/plat-tcc/Kconfig"
1052 source "arch/arm/mach-s3c2410/Kconfig"
1053 source "arch/arm/mach-s3c2412/Kconfig"
1054 source "arch/arm/mach-s3c2416/Kconfig"
1055 source "arch/arm/mach-s3c2440/Kconfig"
1056 source "arch/arm/mach-s3c2443/Kconfig"
1060 source "arch/arm/mach-s3c64xx/Kconfig"
1063 source "arch/arm/mach-s5p64x0/Kconfig"
1065 source "arch/arm/mach-s5pc100/Kconfig"
1067 source "arch/arm/mach-s5pv210/Kconfig"
1069 source "arch/arm/mach-exynos4/Kconfig"
1071 source "arch/arm/mach-shmobile/Kconfig"
1073 source "arch/arm/mach-tegra/Kconfig"
1075 source "arch/arm/mach-u300/Kconfig"
1077 source "arch/arm/mach-ux500/Kconfig"
1079 source "arch/arm/mach-versatile/Kconfig"
1081 source "arch/arm/mach-vexpress/Kconfig"
1082 source "arch/arm/plat-versatile/Kconfig"
1084 source "arch/arm/mach-vt8500/Kconfig"
1086 source "arch/arm/mach-w90x900/Kconfig"
1088 # Definitions to make life easier
1094 select GENERIC_CLOCKEVENTS
1095 select HAVE_SCHED_CLOCK
1100 select GENERIC_IRQ_CHIP
1101 select HAVE_SCHED_CLOCK
1106 config PLAT_VERSATILE
1109 config ARM_TIMER_SP804
1113 source arch/arm/mm/Kconfig
1116 bool "Enable iWMMXt support"
1117 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1118 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1120 Enable support for iWMMXt context switching at run time if
1121 running on a CPU that supports it.
1123 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1126 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1130 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1131 (!ARCH_OMAP3 || OMAP3_EMU)
1135 config MULTI_IRQ_HANDLER
1138 Allow each machine to specify it's own IRQ handler at run time.
1141 source "arch/arm/Kconfig-nommu"
1144 config ARM_ERRATA_411920
1145 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1146 depends on CPU_V6 || CPU_V6K
1148 Invalidation of the Instruction Cache operation can
1149 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1150 It does not affect the MPCore. This option enables the ARM Ltd.
1151 recommended workaround.
1153 config ARM_ERRATA_430973
1154 bool "ARM errata: Stale prediction on replaced interworking branch"
1157 This option enables the workaround for the 430973 Cortex-A8
1158 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1159 interworking branch is replaced with another code sequence at the
1160 same virtual address, whether due to self-modifying code or virtual
1161 to physical address re-mapping, Cortex-A8 does not recover from the
1162 stale interworking branch prediction. This results in Cortex-A8
1163 executing the new code sequence in the incorrect ARM or Thumb state.
1164 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1165 and also flushes the branch target cache at every context switch.
1166 Note that setting specific bits in the ACTLR register may not be
1167 available in non-secure mode.
1169 config ARM_ERRATA_458693
1170 bool "ARM errata: Processor deadlock when a false hazard is created"
1173 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1174 erratum. For very specific sequences of memory operations, it is
1175 possible for a hazard condition intended for a cache line to instead
1176 be incorrectly associated with a different cache line. This false
1177 hazard might then cause a processor deadlock. The workaround enables
1178 the L1 caching of the NEON accesses and disables the PLD instruction
1179 in the ACTLR register. Note that setting specific bits in the ACTLR
1180 register may not be available in non-secure mode.
1182 config ARM_ERRATA_460075
1183 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1186 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1187 erratum. Any asynchronous access to the L2 cache may encounter a
1188 situation in which recent store transactions to the L2 cache are lost
1189 and overwritten with stale memory contents from external memory. The
1190 workaround disables the write-allocate mode for the L2 cache via the
1191 ACTLR register. Note that setting specific bits in the ACTLR register
1192 may not be available in non-secure mode.
1194 config ARM_ERRATA_742230
1195 bool "ARM errata: DMB operation may be faulty"
1196 depends on CPU_V7 && SMP
1198 This option enables the workaround for the 742230 Cortex-A9
1199 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1200 between two write operations may not ensure the correct visibility
1201 ordering of the two writes. This workaround sets a specific bit in
1202 the diagnostic register of the Cortex-A9 which causes the DMB
1203 instruction to behave as a DSB, ensuring the correct behaviour of
1206 config ARM_ERRATA_742231
1207 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for the 742231 Cortex-A9
1211 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1212 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1213 accessing some data located in the same cache line, may get corrupted
1214 data due to bad handling of the address hazard when the line gets
1215 replaced from one of the CPUs at the same time as another CPU is
1216 accessing it. This workaround sets specific bits in the diagnostic
1217 register of the Cortex-A9 which reduces the linefill issuing
1218 capabilities of the processor.
1220 config PL310_ERRATA_588369
1221 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1222 depends on CACHE_L2X0
1224 The PL310 L2 cache controller implements three types of Clean &
1225 Invalidate maintenance operations: by Physical Address
1226 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1227 They are architecturally defined to behave as the execution of a
1228 clean operation followed immediately by an invalidate operation,
1229 both performing to the same memory location. This functionality
1230 is not correctly implemented in PL310 as clean lines are not
1231 invalidated as a result of these operations.
1233 config ARM_ERRATA_720789
1234 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for the 720789 Cortex-A9 (prior to
1238 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1239 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1240 As a consequence of this erratum, some TLB entries which should be
1241 invalidated are not, resulting in an incoherency in the system page
1242 tables. The workaround changes the TLB flushing routines to invalidate
1243 entries regardless of the ASID.
1245 config PL310_ERRATA_727915
1246 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1247 depends on CACHE_L2X0
1249 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1250 operation (offset 0x7FC). This operation runs in background so that
1251 PL310 can handle normal accesses while it is in progress. Under very
1252 rare circumstances, due to this erratum, write data can be lost when
1253 PL310 treats a cacheable write transaction during a Clean &
1254 Invalidate by Way operation.
1256 config ARM_ERRATA_743622
1257 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1260 This option enables the workaround for the 743622 Cortex-A9
1261 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1262 optimisation in the Cortex-A9 Store Buffer may lead to data
1263 corruption. This workaround sets a specific bit in the diagnostic
1264 register of the Cortex-A9 which disables the Store Buffer
1265 optimisation, preventing the defect from occurring. This has no
1266 visible impact on the overall performance or power consumption of the
1269 config ARM_ERRATA_751472
1270 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1271 depends on CPU_V7 && SMP
1273 This option enables the workaround for the 751472 Cortex-A9 (prior
1274 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1275 completion of a following broadcasted operation if the second
1276 operation is received by a CPU before the ICIALLUIS has completed,
1277 potentially leading to corrupted entries in the cache or TLB.
1279 config ARM_ERRATA_753970
1280 bool "ARM errata: cache sync operation may be faulty"
1281 depends on CACHE_PL310
1283 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1285 Under some condition the effect of cache sync operation on
1286 the store buffer still remains when the operation completes.
1287 This means that the store buffer is always asked to drain and
1288 this prevents it from merging any further writes. The workaround
1289 is to replace the normal offset of cache sync operation (0x730)
1290 by another offset targeting an unmapped PL310 register 0x740.
1291 This has the same effect as the cache sync operation: store buffer
1292 drain and waiting for all buffers empty.
1294 config ARM_ERRATA_754322
1295 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1298 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1299 r3p*) erratum. A speculative memory access may cause a page table walk
1300 which starts prior to an ASID switch but completes afterwards. This
1301 can populate the micro-TLB with a stale entry which may be hit with
1302 the new ASID. This workaround places two dsb instructions in the mm
1303 switching code so that no page table walks can cross the ASID switch.
1305 config ARM_ERRATA_754327
1306 bool "ARM errata: no automatic Store Buffer drain"
1307 depends on CPU_V7 && SMP
1309 This option enables the workaround for the 754327 Cortex-A9 (prior to
1310 r2p0) erratum. The Store Buffer does not have any automatic draining
1311 mechanism and therefore a livelock may occur if an external agent
1312 continuously polls a memory location waiting to observe an update.
1313 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1314 written polling loops from denying visibility of updates to memory.
1316 config ARM_ERRATA_364296
1317 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1318 depends on CPU_V6 && !SMP
1320 This options enables the workaround for the 364296 ARM1136
1321 r0p2 erratum (possible cache data corruption with
1322 hit-under-miss enabled). It sets the undocumented bit 31 in
1323 the auxiliary control register and the FI bit in the control
1324 register, thus disabling hit-under-miss without putting the
1325 processor into full low interrupt latency mode. ARM11MPCore
1328 config ARM_ERRATA_764369
1329 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1330 depends on CPU_V7 && SMP
1332 This option enables the workaround for erratum 764369
1333 affecting Cortex-A9 MPCore with two or more processors (all
1334 current revisions). Under certain timing circumstances, a data
1335 cache line maintenance operation by MVA targeting an Inner
1336 Shareable memory region may fail to proceed up to either the
1337 Point of Coherency or to the Point of Unification of the
1338 system. This workaround adds a DSB instruction before the
1339 relevant cache maintenance functions and sets a specific bit
1340 in the diagnostic control register of the SCU.
1344 source "arch/arm/common/Kconfig"
1354 Find out whether you have ISA slots on your motherboard. ISA is the
1355 name of a bus system, i.e. the way the CPU talks to the other stuff
1356 inside your box. Other bus systems are PCI, EISA, MicroChannel
1357 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1358 newer boards don't support it. If you have ISA, say Y, otherwise N.
1360 # Select ISA DMA controller support
1365 # Select ISA DMA interface
1370 bool "PCI support" if MIGHT_HAVE_PCI
1372 Find out whether you have a PCI motherboard. PCI is the name of a
1373 bus system, i.e. the way the CPU talks to the other stuff inside
1374 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1375 VESA. If you have PCI, say Y, otherwise N.
1381 config PCI_NANOENGINE
1382 bool "BSE nanoEngine PCI support"
1383 depends on SA1100_NANOENGINE
1385 Enable PCI on the BSE nanoEngine board.
1390 # Select the host bridge type
1391 config PCI_HOST_VIA82C505
1393 depends on PCI && ARCH_SHARK
1396 config PCI_HOST_ITE8152
1398 depends on PCI && MACH_ARMCORE
1402 source "drivers/pci/Kconfig"
1404 source "drivers/pcmcia/Kconfig"
1408 menu "Kernel Features"
1410 source "kernel/time/Kconfig"
1413 bool "Symmetric Multi-Processing"
1414 depends on CPU_V6K || CPU_V7
1415 depends on GENERIC_CLOCKEVENTS
1416 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1417 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1418 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1419 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1420 select USE_GENERIC_SMP_HELPERS
1421 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1423 This enables support for systems with more than one CPU. If you have
1424 a system with only one CPU, like most personal computers, say N. If
1425 you have a system with more than one CPU, say Y.
1427 If you say N here, the kernel will run on single and multiprocessor
1428 machines, but will use only one CPU of a multiprocessor machine. If
1429 you say Y here, the kernel will run on many, but not all, single
1430 processor machines. On a single processor machine, the kernel will
1431 run faster if you say N here.
1433 See also <file:Documentation/i386/IO-APIC.txt>,
1434 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1435 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1437 If you don't know what to do here, say N.
1440 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1441 depends on EXPERIMENTAL
1442 depends on SMP && !XIP_KERNEL
1445 SMP kernels contain instructions which fail on non-SMP processors.
1446 Enabling this option allows the kernel to modify itself to make
1447 these instructions safe. Disabling it allows about 1K of space
1450 If you don't know what to do here, say Y.
1452 config ARM_CPU_TOPOLOGY
1453 bool "Support cpu topology definition"
1454 depends on SMP && CPU_V7
1457 Support ARM cpu topology definition. The MPIDR register defines
1458 affinity between processors which is then used to describe the cpu
1459 topology of an ARM System.
1462 bool "Multi-core scheduler support"
1463 depends on ARM_CPU_TOPOLOGY
1465 Multi-core scheduler support improves the CPU scheduler's decision
1466 making when dealing with multi-core CPU chips at a cost of slightly
1467 increased overhead in some places. If unsure say N here.
1470 bool "SMT scheduler support"
1471 depends on ARM_CPU_TOPOLOGY
1473 Improves the CPU scheduler's decision making when dealing with
1474 MultiThreading at a cost of slightly increased overhead in some
1475 places. If unsure say N here.
1480 This option enables support for the ARM system coherency unit
1487 This options enables support for the ARM timer and watchdog unit
1490 prompt "Memory split"
1493 Select the desired split between kernel and user memory.
1495 If you are not absolutely sure what you are doing, leave this
1499 bool "3G/1G user/kernel split"
1501 bool "2G/2G user/kernel split"
1503 bool "1G/3G user/kernel split"
1508 default 0x40000000 if VMSPLIT_1G
1509 default 0x80000000 if VMSPLIT_2G
1513 int "Maximum number of CPUs (2-32)"
1519 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1520 depends on SMP && HOTPLUG && EXPERIMENTAL
1522 Say Y here to experiment with turning CPUs off and on. CPUs
1523 can be controlled through /sys/devices/system/cpu.
1526 bool "Use local timer interrupts"
1529 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1531 Enable support for local timers on SMP platforms, rather then the
1532 legacy IPI broadcast method. Local timers allows the system
1533 accounting to be spread across the timer interval, preventing a
1534 "thundering herd" at every timer tick.
1536 source kernel/Kconfig.preempt
1540 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1541 ARCH_S5PV210 || ARCH_EXYNOS4
1542 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1543 default AT91_TIMER_HZ if ARCH_AT91
1544 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1547 config THUMB2_KERNEL
1548 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1549 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1551 select ARM_ASM_UNIFIED
1553 By enabling this option, the kernel will be compiled in
1554 Thumb-2 mode. A compiler/assembler that understand the unified
1555 ARM-Thumb syntax is needed.
1559 config THUMB2_AVOID_R_ARM_THM_JUMP11
1560 bool "Work around buggy Thumb-2 short branch relocations in gas"
1561 depends on THUMB2_KERNEL && MODULES
1564 Various binutils versions can resolve Thumb-2 branches to
1565 locally-defined, preemptible global symbols as short-range "b.n"
1566 branch instructions.
1568 This is a problem, because there's no guarantee the final
1569 destination of the symbol, or any candidate locations for a
1570 trampoline, are within range of the branch. For this reason, the
1571 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1572 relocation in modules at all, and it makes little sense to add
1575 The symptom is that the kernel fails with an "unsupported
1576 relocation" error when loading some modules.
1578 Until fixed tools are available, passing
1579 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1580 code which hits this problem, at the cost of a bit of extra runtime
1581 stack usage in some cases.
1583 The problem is described in more detail at:
1584 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1586 Only Thumb-2 kernels are affected.
1588 Unless you are sure your tools don't have this problem, say Y.
1590 config ARM_ASM_UNIFIED
1594 bool "Use the ARM EABI to compile the kernel"
1596 This option allows for the kernel to be compiled using the latest
1597 ARM ABI (aka EABI). This is only useful if you are using a user
1598 space environment that is also compiled with EABI.
1600 Since there are major incompatibilities between the legacy ABI and
1601 EABI, especially with regard to structure member alignment, this
1602 option also changes the kernel syscall calling convention to
1603 disambiguate both ABIs and allow for backward compatibility support
1604 (selected with CONFIG_OABI_COMPAT).
1606 To use this you need GCC version 4.0.0 or later.
1609 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1610 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1613 This option preserves the old syscall interface along with the
1614 new (ARM EABI) one. It also provides a compatibility layer to
1615 intercept syscalls that have structure arguments which layout
1616 in memory differs between the legacy ABI and the new ARM EABI
1617 (only for non "thumb" binaries). This option adds a tiny
1618 overhead to all syscalls and produces a slightly larger kernel.
1619 If you know you'll be using only pure EABI user space then you
1620 can say N here. If this option is not selected and you attempt
1621 to execute a legacy ABI binary then the result will be
1622 UNPREDICTABLE (in fact it can be predicted that it won't work
1623 at all). If in doubt say Y.
1625 config ARCH_HAS_HOLES_MEMORYMODEL
1628 config ARCH_SPARSEMEM_ENABLE
1631 config ARCH_SPARSEMEM_DEFAULT
1632 def_bool ARCH_SPARSEMEM_ENABLE
1634 config ARCH_SELECT_MEMORY_MODEL
1635 def_bool ARCH_SPARSEMEM_ENABLE
1637 config HAVE_ARCH_PFN_VALID
1638 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1641 bool "High Memory Support"
1644 The address space of ARM processors is only 4 Gigabytes large
1645 and it has to accommodate user address space, kernel address
1646 space as well as some memory mapped IO. That means that, if you
1647 have a large amount of physical memory and/or IO, not all of the
1648 memory can be "permanently mapped" by the kernel. The physical
1649 memory that is not permanently mapped is called "high memory".
1651 Depending on the selected kernel/user memory split, minimum
1652 vmalloc space and actual amount of RAM, you may not need this
1653 option which should result in a slightly faster kernel.
1658 bool "Allocate 2nd-level pagetables from highmem"
1661 config HW_PERF_EVENTS
1662 bool "Enable hardware performance counter support for perf events"
1663 depends on PERF_EVENTS && CPU_HAS_PMU
1666 Enable hardware performance counter support for perf events. If
1667 disabled, perf events will use software events only.
1671 config FORCE_MAX_ZONEORDER
1672 int "Maximum zone order" if ARCH_SHMOBILE
1673 range 11 64 if ARCH_SHMOBILE
1674 default "9" if SA1111
1677 The kernel memory allocator divides physically contiguous memory
1678 blocks into "zones", where each zone is a power of two number of
1679 pages. This option selects the largest power of two that the kernel
1680 keeps in the memory allocator. If you need to allocate very large
1681 blocks of physically contiguous memory, then you may need to
1682 increase this value.
1684 This config option is actually maximum order plus one. For example,
1685 a value of 11 means that the largest free memory block is 2^10 pages.
1688 bool "Timer and CPU usage LEDs"
1689 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1690 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1691 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1692 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1693 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1694 ARCH_AT91 || ARCH_DAVINCI || \
1695 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1697 If you say Y here, the LEDs on your machine will be used
1698 to provide useful information about your current system status.
1700 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1701 be able to select which LEDs are active using the options below. If
1702 you are compiling a kernel for the EBSA-110 or the LART however, the
1703 red LED will simply flash regularly to indicate that the system is
1704 still functional. It is safe to say Y here if you have a CATS
1705 system, but the driver will do nothing.
1708 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1709 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1710 || MACH_OMAP_PERSEUS2
1712 depends on !GENERIC_CLOCKEVENTS
1713 default y if ARCH_EBSA110
1715 If you say Y here, one of the system LEDs (the green one on the
1716 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1717 will flash regularly to indicate that the system is still
1718 operational. This is mainly useful to kernel hackers who are
1719 debugging unstable kernels.
1721 The LART uses the same LED for both Timer LED and CPU usage LED
1722 functions. You may choose to use both, but the Timer LED function
1723 will overrule the CPU usage LED.
1726 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1728 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1729 || MACH_OMAP_PERSEUS2
1732 If you say Y here, the red LED will be used to give a good real
1733 time indication of CPU usage, by lighting whenever the idle task
1734 is not currently executing.
1736 The LART uses the same LED for both Timer LED and CPU usage LED
1737 functions. You may choose to use both, but the Timer LED function
1738 will overrule the CPU usage LED.
1740 config ALIGNMENT_TRAP
1742 depends on CPU_CP15_MMU
1743 default y if !ARCH_EBSA110
1744 select HAVE_PROC_CPU if PROC_FS
1746 ARM processors cannot fetch/store information which is not
1747 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1748 address divisible by 4. On 32-bit ARM processors, these non-aligned
1749 fetch/store instructions will be emulated in software if you say
1750 here, which has a severe performance impact. This is necessary for
1751 correct operation of some network protocols. With an IP-only
1752 configuration it is safe to say N, otherwise say Y.
1754 config UACCESS_WITH_MEMCPY
1755 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1756 depends on MMU && EXPERIMENTAL
1757 default y if CPU_FEROCEON
1759 Implement faster copy_to_user and clear_user methods for CPU
1760 cores where a 8-word STM instruction give significantly higher
1761 memory write throughput than a sequence of individual 32bit stores.
1763 A possible side effect is a slight increase in scheduling latency
1764 between threads sharing the same address space if they invoke
1765 such copy operations with large buffers.
1767 However, if the CPU data cache is using a write-allocate mode,
1768 this option is unlikely to provide any performance gain.
1772 prompt "Enable seccomp to safely compute untrusted bytecode"
1774 This kernel feature is useful for number crunching applications
1775 that may need to compute untrusted bytecode during their
1776 execution. By using pipes or other transports made available to
1777 the process as file descriptors supporting the read/write
1778 syscalls, it's possible to isolate those applications in
1779 their own address space using seccomp. Once seccomp is
1780 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1781 and the task is only allowed to execute a few safe syscalls
1782 defined by each seccomp mode.
1784 config CC_STACKPROTECTOR
1785 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1786 depends on EXPERIMENTAL
1788 This option turns on the -fstack-protector GCC feature. This
1789 feature puts, at the beginning of functions, a canary value on
1790 the stack just before the return address, and validates
1791 the value just before actually returning. Stack based buffer
1792 overflows (that need to overwrite this return address) now also
1793 overwrite the canary, which gets detected and the attack is then
1794 neutralized via a kernel panic.
1795 This feature requires gcc version 4.2 or above.
1797 config DEPRECATED_PARAM_STRUCT
1798 bool "Provide old way to pass kernel parameters"
1800 This was deprecated in 2001 and announced to live on for 5 years.
1801 Some old boot loaders still use this way.
1808 bool "Flattened Device Tree support"
1810 select OF_EARLY_FLATTREE
1813 Include support for flattened device tree machine descriptions.
1815 # Compressed boot loader in ROM. Yes, we really want to ask about
1816 # TEXT and BSS so we preserve their values in the config files.
1817 config ZBOOT_ROM_TEXT
1818 hex "Compressed ROM boot loader base address"
1821 The physical address at which the ROM-able zImage is to be
1822 placed in the target. Platforms which normally make use of
1823 ROM-able zImage formats normally set this to a suitable
1824 value in their defconfig file.
1826 If ZBOOT_ROM is not enabled, this has no effect.
1828 config ZBOOT_ROM_BSS
1829 hex "Compressed ROM boot loader BSS address"
1832 The base address of an area of read/write memory in the target
1833 for the ROM-able zImage which must be available while the
1834 decompressor is running. It must be large enough to hold the
1835 entire decompressed kernel plus an additional 128 KiB.
1836 Platforms which normally make use of ROM-able zImage formats
1837 normally set this to a suitable value in their defconfig file.
1839 If ZBOOT_ROM is not enabled, this has no effect.
1842 bool "Compressed boot loader in ROM/flash"
1843 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1845 Say Y here if you intend to execute your compressed kernel image
1846 (zImage) directly from ROM or flash. If unsure, say N.
1849 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1850 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1851 default ZBOOT_ROM_NONE
1853 Include experimental SD/MMC loading code in the ROM-able zImage.
1854 With this enabled it is possible to write the the ROM-able zImage
1855 kernel image to an MMC or SD card and boot the kernel straight
1856 from the reset vector. At reset the processor Mask ROM will load
1857 the first part of the the ROM-able zImage which in turn loads the
1858 rest the kernel image to RAM.
1860 config ZBOOT_ROM_NONE
1861 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1863 Do not load image from SD or MMC
1865 config ZBOOT_ROM_MMCIF
1866 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1868 Load image from MMCIF hardware block.
1870 config ZBOOT_ROM_SH_MOBILE_SDHI
1871 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1873 Load image from SDHI hardware block
1877 config ARM_APPENDED_DTB
1878 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1879 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1881 With this option, the boot code will look for a device tree binary
1882 (DTB) appended to zImage
1883 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1885 This is meant as a backward compatibility convenience for those
1886 systems with a bootloader that can't be upgraded to accommodate
1887 the documented boot protocol using a device tree.
1889 Beware that there is very little in terms of protection against
1890 this option being confused by leftover garbage in memory that might
1891 look like a DTB header after a reboot if no actual DTB is appended
1892 to zImage. Do not leave this option active in a production kernel
1893 if you don't intend to always append a DTB. Proper passing of the
1894 location into r2 of a bootloader provided DTB is always preferable
1897 config ARM_ATAG_DTB_COMPAT
1898 bool "Supplement the appended DTB with traditional ATAG information"
1899 depends on ARM_APPENDED_DTB
1901 Some old bootloaders can't be updated to a DTB capable one, yet
1902 they provide ATAGs with memory configuration, the ramdisk address,
1903 the kernel cmdline string, etc. Such information is dynamically
1904 provided by the bootloader and can't always be stored in a static
1905 DTB. To allow a device tree enabled kernel to be used with such
1906 bootloaders, this option allows zImage to extract the information
1907 from the ATAG list and store it at run time into the appended DTB.
1910 string "Default kernel command string"
1913 On some architectures (EBSA110 and CATS), there is currently no way
1914 for the boot loader to pass arguments to the kernel. For these
1915 architectures, you should supply some command-line options at build
1916 time by entering them here. As a minimum, you should specify the
1917 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1920 prompt "Kernel command line type" if CMDLINE != ""
1921 default CMDLINE_FROM_BOOTLOADER
1923 config CMDLINE_FROM_BOOTLOADER
1924 bool "Use bootloader kernel arguments if available"
1926 Uses the command-line options passed by the boot loader. If
1927 the boot loader doesn't provide any, the default kernel command
1928 string provided in CMDLINE will be used.
1930 config CMDLINE_EXTEND
1931 bool "Extend bootloader kernel arguments"
1933 The command-line arguments provided by the boot loader will be
1934 appended to the default kernel command string.
1936 config CMDLINE_FORCE
1937 bool "Always use the default kernel command string"
1939 Always use the default kernel command string, even if the boot
1940 loader passes other arguments to the kernel.
1941 This is useful if you cannot or don't want to change the
1942 command-line options your boot loader passes to the kernel.
1946 bool "Kernel Execute-In-Place from ROM"
1947 depends on !ZBOOT_ROM
1949 Execute-In-Place allows the kernel to run from non-volatile storage
1950 directly addressable by the CPU, such as NOR flash. This saves RAM
1951 space since the text section of the kernel is not loaded from flash
1952 to RAM. Read-write sections, such as the data section and stack,
1953 are still copied to RAM. The XIP kernel is not compressed since
1954 it has to run directly from flash, so it will take more space to
1955 store it. The flash address used to link the kernel object files,
1956 and for storing it, is configuration dependent. Therefore, if you
1957 say Y here, you must know the proper physical address where to
1958 store the kernel image depending on your own flash memory usage.
1960 Also note that the make target becomes "make xipImage" rather than
1961 "make zImage" or "make Image". The final kernel binary to put in
1962 ROM memory will be arch/arm/boot/xipImage.
1966 config XIP_PHYS_ADDR
1967 hex "XIP Kernel Physical Location"
1968 depends on XIP_KERNEL
1969 default "0x00080000"
1971 This is the physical address in your flash memory the kernel will
1972 be linked for and stored to. This address is dependent on your
1976 bool "Kexec system call (EXPERIMENTAL)"
1977 depends on EXPERIMENTAL
1979 kexec is a system call that implements the ability to shutdown your
1980 current kernel, and to start another kernel. It is like a reboot
1981 but it is independent of the system firmware. And like a reboot
1982 you can start any kernel with it, not just Linux.
1984 It is an ongoing process to be certain the hardware in a machine
1985 is properly shutdown, so do not be surprised if this code does not
1986 initially work for you. It may help to enable device hotplugging
1990 bool "Export atags in procfs"
1994 Should the atags used to boot the kernel be exported in an "atags"
1995 file in procfs. Useful with kexec.
1998 bool "Build kdump crash kernel (EXPERIMENTAL)"
1999 depends on EXPERIMENTAL
2001 Generate crash dump after being started by kexec. This should
2002 be normally only set in special crash dump kernels which are
2003 loaded in the main kernel with kexec-tools into a specially
2004 reserved region and then later executed after a crash by
2005 kdump/kexec. The crash dump kernel must be compiled to a
2006 memory address not used by the main kernel
2008 For more details see Documentation/kdump/kdump.txt
2010 config AUTO_ZRELADDR
2011 bool "Auto calculation of the decompressed kernel image address"
2012 depends on !ZBOOT_ROM && !ARCH_U300
2014 ZRELADDR is the physical address where the decompressed kernel
2015 image will be placed. If AUTO_ZRELADDR is selected, the address
2016 will be determined at run-time by masking the current IP with
2017 0xf8000000. This assumes the zImage being placed in the first 128MB
2018 from start of memory.
2022 menu "CPU Power Management"
2026 source "drivers/cpufreq/Kconfig"
2029 tristate "CPUfreq driver for i.MX CPUs"
2030 depends on ARCH_MXC && CPU_FREQ
2032 This enables the CPUfreq driver for i.MX CPUs.
2034 config CPU_FREQ_SA1100
2037 config CPU_FREQ_SA1110
2040 config CPU_FREQ_INTEGRATOR
2041 tristate "CPUfreq driver for ARM Integrator CPUs"
2042 depends on ARCH_INTEGRATOR && CPU_FREQ
2045 This enables the CPUfreq driver for ARM Integrator CPUs.
2047 For details, take a look at <file:Documentation/cpu-freq>.
2053 depends on CPU_FREQ && ARCH_PXA && PXA25x
2055 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2060 Internal configuration node for common cpufreq on Samsung SoC
2062 config CPU_FREQ_S3C24XX
2063 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2064 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2067 This enables the CPUfreq driver for the Samsung S3C24XX family
2070 For details, take a look at <file:Documentation/cpu-freq>.
2074 config CPU_FREQ_S3C24XX_PLL
2075 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2076 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2078 Compile in support for changing the PLL frequency from the
2079 S3C24XX series CPUfreq driver. The PLL takes time to settle
2080 after a frequency change, so by default it is not enabled.
2082 This also means that the PLL tables for the selected CPU(s) will
2083 be built which may increase the size of the kernel image.
2085 config CPU_FREQ_S3C24XX_DEBUG
2086 bool "Debug CPUfreq Samsung driver core"
2087 depends on CPU_FREQ_S3C24XX
2089 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2091 config CPU_FREQ_S3C24XX_IODEBUG
2092 bool "Debug CPUfreq Samsung driver IO timing"
2093 depends on CPU_FREQ_S3C24XX
2095 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2097 config CPU_FREQ_S3C24XX_DEBUGFS
2098 bool "Export debugfs for CPUFreq"
2099 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2101 Export status information via debugfs.
2105 source "drivers/cpuidle/Kconfig"
2109 menu "Floating point emulation"
2111 comment "At least one emulation must be selected"
2114 bool "NWFPE math emulation"
2115 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2117 Say Y to include the NWFPE floating point emulator in the kernel.
2118 This is necessary to run most binaries. Linux does not currently
2119 support floating point hardware so you need to say Y here even if
2120 your machine has an FPA or floating point co-processor podule.
2122 You may say N here if you are going to load the Acorn FPEmulator
2123 early in the bootup.
2126 bool "Support extended precision"
2127 depends on FPE_NWFPE
2129 Say Y to include 80-bit support in the kernel floating-point
2130 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2131 Note that gcc does not generate 80-bit operations by default,
2132 so in most cases this option only enlarges the size of the
2133 floating point emulator without any good reason.
2135 You almost surely want to say N here.
2138 bool "FastFPE math emulation (EXPERIMENTAL)"
2139 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2141 Say Y here to include the FAST floating point emulator in the kernel.
2142 This is an experimental much faster emulator which now also has full
2143 precision for the mantissa. It does not support any exceptions.
2144 It is very simple, and approximately 3-6 times faster than NWFPE.
2146 It should be sufficient for most programs. It may be not suitable
2147 for scientific calculations, but you have to check this for yourself.
2148 If you do not feel you need a faster FP emulation you should better
2152 bool "VFP-format floating point maths"
2153 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2155 Say Y to include VFP support code in the kernel. This is needed
2156 if your hardware includes a VFP unit.
2158 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2159 release notes and additional status information.
2161 Say N if your target does not have VFP hardware.
2169 bool "Advanced SIMD (NEON) Extension support"
2170 depends on VFPv3 && CPU_V7
2172 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2177 menu "Userspace binary formats"
2179 source "fs/Kconfig.binfmt"
2182 tristate "RISC OS personality"
2185 Say Y here to include the kernel code necessary if you want to run
2186 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2187 experimental; if this sounds frightening, say N and sleep in peace.
2188 You can also say M here to compile this support as a module (which
2189 will be called arthur).
2193 menu "Power management options"
2195 source "kernel/power/Kconfig"
2197 config ARCH_SUSPEND_POSSIBLE
2198 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2199 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2200 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2205 source "net/Kconfig"
2207 source "drivers/Kconfig"
2211 source "arch/arm/Kconfig.debug"
2213 source "security/Kconfig"
2215 source "crypto/Kconfig"
2217 source "lib/Kconfig"