5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config ARCH_HAS_DMA_SET_COHERENT_MASK
184 config GENERIC_ISA_DMA
195 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
196 default DRAM_BASE if REMAP_VECTORS_TO_RAM
199 The base address of exception vectors.
201 config ARM_PATCH_PHYS_VIRT
202 bool "Patch physical to virtual translations at runtime" if EMBEDDED
204 depends on !XIP_KERNEL && MMU
205 depends on !ARCH_REALVIEW || !SPARSEMEM
207 Patch phys-to-virt and virt-to-phys translation functions at
208 boot and module load time according to the position of the
209 kernel in system memory.
211 This can only be used with non-XIP MMU kernels where the base
212 of physical memory is at a 16MB boundary.
214 Only disable this option if you know that you do not require
215 this feature (eg, building a kernel for a single machine) and
216 you need to shrink the kernel to the minimal size.
218 config NEED_MACH_MEMORY_H
221 Select this when mach/memory.h is required to provide special
222 definitions for this platform. The need for mach/memory.h should
223 be avoided when possible.
226 hex "Physical address of main memory" if MMU
227 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
228 default DRAM_BASE if !MMU
230 Please provide the physical address corresponding to the
231 location of main memory in your system.
237 source "init/Kconfig"
239 source "kernel/Kconfig.freezer"
244 bool "MMU-based Paged Memory Management Support"
247 Select if you want MMU-based virtualised addressing space
248 support by paged memory management. If unsure, say 'Y'.
251 # The "ARM system type" choice list is ordered alphabetically by option
252 # text. Please add new entries in the option alphabetic order.
255 prompt "ARM system type"
256 default ARCH_VERSATILE
258 config ARCH_INTEGRATOR
259 bool "ARM Ltd. Integrator family"
261 select ARCH_HAS_CPUFREQ
263 select HAVE_MACH_CLKDEV
265 select GENERIC_CLOCKEVENTS
266 select PLAT_VERSATILE
267 select PLAT_VERSATILE_FPGA_IRQ
268 select NEED_MACH_MEMORY_H
270 Support for ARM's Integrator platform.
273 bool "ARM Ltd. RealView family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLCD
282 select ARM_TIMER_SP804
283 select GPIO_PL061 if GPIOLIB
284 select NEED_MACH_MEMORY_H
286 This enables support for ARM Ltd RealView boards.
288 config ARCH_VERSATILE
289 bool "ARM Ltd. Versatile family"
293 select HAVE_MACH_CLKDEV
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804
302 This enables support for ARM Ltd Versatile board.
305 bool "ARM Ltd. Versatile Express family"
306 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_TIMER_SP804
310 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
313 select HAVE_PATA_PLATFORM
315 select PLAT_VERSATILE
316 select PLAT_VERSATILE_CLCD
318 This enables support for the ARM Ltd Versatile Express boards.
322 select ARCH_REQUIRE_GPIOLIB
326 This enables support for systems based on the Atmel AT91RM9200,
327 AT91SAM9 and AT91CAP9 processors.
330 bool "Broadcom BCMRING"
334 select ARM_TIMER_SP804
336 select GENERIC_CLOCKEVENTS
337 select ARCH_WANT_OPTIONAL_GPIOLIB
339 Support for Broadcom's BCMRing platform.
342 bool "Calxeda Highbank-based"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
346 select ARM_TIMER_SP804
349 select GENERIC_CLOCKEVENTS
353 Support for the Calxeda Highbank SoC based boards.
356 bool "Cirrus Logic CLPS711x/EP721x-based"
358 select ARCH_USES_GETTIMEOFFSET
359 select NEED_MACH_MEMORY_H
361 Support for Cirrus Logic 711x/721x based boards.
364 bool "Cavium Networks CNS3XXX family"
366 select GENERIC_CLOCKEVENTS
368 select MIGHT_HAVE_PCI
369 select PCI_DOMAINS if PCI
371 Support for Cavium Networks CNS3XXX platform.
374 bool "Cortina Systems Gemini"
376 select ARCH_REQUIRE_GPIOLIB
377 select ARCH_USES_GETTIMEOFFSET
379 Support for the Cortina Systems Gemini family SoCs
382 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
385 select GENERIC_CLOCKEVENTS
387 select GENERIC_IRQ_CHIP
391 Support for CSR SiRFSoC ARM Cortex A9 Platform
398 select ARCH_USES_GETTIMEOFFSET
399 select NEED_MACH_MEMORY_H
401 This is an evaluation board for the StrongARM processor available
402 from Digital. It has limited hardware on-board, including an
403 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_HAS_HOLES_MEMORYMODEL
414 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_MEMORY_H
417 This enables support for the Cirrus EP93xx series of CPUs.
419 config ARCH_FOOTBRIDGE
423 select GENERIC_CLOCKEVENTS
425 select NEED_MACH_MEMORY_H
427 Support for systems based on the DC21285 companion chip
428 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
431 bool "Freescale MXC/iMX-based"
432 select GENERIC_CLOCKEVENTS
433 select ARCH_REQUIRE_GPIOLIB
436 select GENERIC_IRQ_CHIP
437 select HAVE_SCHED_CLOCK
438 select MULTI_IRQ_HANDLER
440 Support for Freescale MXC/iMX-based family of processors
443 bool "Freescale MXS-based"
444 select GENERIC_CLOCKEVENTS
445 select ARCH_REQUIRE_GPIOLIB
449 Support for Freescale MXS-based family of processors
452 bool "Hilscher NetX based"
456 select GENERIC_CLOCKEVENTS
458 This enables support for systems based on the Hilscher NetX Soc
461 bool "Hynix HMS720x-based"
464 select ARCH_USES_GETTIMEOFFSET
466 This enables support for systems based on the Hynix HMS720x
474 select ARCH_SUPPORTS_MSI
476 select NEED_MACH_MEMORY_H
478 Support for Intel's IOP13XX (XScale) family of processors.
486 select ARCH_REQUIRE_GPIOLIB
488 Support for Intel's 80219 and IOP32X (XScale) family of
497 select ARCH_REQUIRE_GPIOLIB
499 Support for Intel's IOP33X (XScale) family of processors.
506 select ARCH_USES_GETTIMEOFFSET
507 select NEED_MACH_MEMORY_H
509 Support for Intel's IXP23xx (XScale) family of processors.
512 bool "IXP2400/2800-based"
516 select ARCH_USES_GETTIMEOFFSET
517 select NEED_MACH_MEMORY_H
519 Support for Intel's IXP2400/2800 (XScale) family of processors.
524 select ARCH_HAS_DMA_SET_COHERENT_MASK
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select HAVE_SCHED_CLOCK
530 select MIGHT_HAVE_PCI
531 select DMABOUNCE if PCI
533 Support for Intel's IXP4XX (XScale) family of processors.
539 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
543 Support for the Marvell Dove SoC 88AP510
546 bool "Marvell Kirkwood"
550 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 Support for the following Marvell Kirkwood series SoCs:
555 88F6180, 88F6192 and 88F6281.
561 select ARCH_REQUIRE_GPIOLIB
564 select USB_ARCH_HAS_OHCI
566 select GENERIC_CLOCKEVENTS
568 Support for the NXP LPC32XX family of processors
571 bool "Marvell MV78xx0"
574 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
578 Support for the following Marvell MV78xx0 series SoCs:
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
590 Support for the following Marvell Orion 5x series SoCs:
591 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
592 Orion-2 (5281), Orion-1-90 (6183).
595 bool "Marvell PXA168/910/MMP2"
597 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
600 select HAVE_SCHED_CLOCK
604 select GENERIC_ALLOCATOR
606 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
609 bool "Micrel/Kendin KS8695"
611 select ARCH_REQUIRE_GPIOLIB
612 select ARCH_USES_GETTIMEOFFSET
613 select NEED_MACH_MEMORY_H
615 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
616 System-on-Chip devices.
619 bool "Nuvoton W90X900 CPU"
621 select ARCH_REQUIRE_GPIOLIB
624 select GENERIC_CLOCKEVENTS
626 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
627 At present, the w90x900 has been renamed nuc900, regarding
628 the ARM series product line, you can login the following
629 link address to know more.
631 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
632 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
638 select GENERIC_CLOCKEVENTS
641 select HAVE_SCHED_CLOCK
642 select ARCH_HAS_CPUFREQ
644 This enables support for NVIDIA Tegra based systems (Tegra APX,
645 Tegra 6xx and Tegra 2 series).
647 config ARCH_PICOXCELL
648 bool "Picochip picoXcell"
649 select ARCH_REQUIRE_GPIOLIB
650 select ARM_PATCH_PHYS_VIRT
654 select GENERIC_CLOCKEVENTS
656 select HAVE_SCHED_CLOCK
661 This enables support for systems based on the Picochip picoXcell
662 family of Femtocell devices. The picoxcell support requires device tree
666 bool "Philips Nexperia PNX4008 Mobile"
669 select ARCH_USES_GETTIMEOFFSET
671 This enables support for Philips PNX4008 mobile platform.
674 bool "PXA2xx/PXA3xx-based"
677 select ARCH_HAS_CPUFREQ
680 select ARCH_REQUIRE_GPIOLIB
681 select GENERIC_CLOCKEVENTS
682 select HAVE_SCHED_CLOCK
687 select MULTI_IRQ_HANDLER
688 select ARM_CPU_SUSPEND if PM
691 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
696 select GENERIC_CLOCKEVENTS
697 select ARCH_REQUIRE_GPIOLIB
700 Support for Qualcomm MSM/QSD based systems. This runs on the
701 apps processor of the MSM/QSD and depends on a shared memory
702 interface to the modem processor which runs the baseband
703 stack and controls some vital subsystems
704 (clock and power control, etc).
707 bool "Renesas SH-Mobile / R-Mobile"
710 select HAVE_MACH_CLKDEV
711 select GENERIC_CLOCKEVENTS
714 select MULTI_IRQ_HANDLER
715 select PM_GENERIC_DOMAINS if PM
716 select NEED_MACH_MEMORY_H
718 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
725 select ARCH_MAY_HAVE_PC_FDC
726 select HAVE_PATA_PLATFORM
729 select ARCH_SPARSEMEM_ENABLE
730 select ARCH_USES_GETTIMEOFFSET
732 select NEED_MACH_MEMORY_H
734 On the Acorn Risc-PC, Linux can support the internal IDE disk and
735 CD-ROM interface, serial and parallel port, and the floppy drive.
742 select ARCH_SPARSEMEM_ENABLE
744 select ARCH_HAS_CPUFREQ
746 select GENERIC_CLOCKEVENTS
748 select HAVE_SCHED_CLOCK
750 select ARCH_REQUIRE_GPIOLIB
752 select NEED_MACH_MEMORY_H
754 Support for StrongARM 11x0 based boards.
757 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
759 select ARCH_HAS_CPUFREQ
762 select ARCH_USES_GETTIMEOFFSET
763 select HAVE_S3C2410_I2C if I2C
765 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
766 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
767 the Samsung SMDK2410 development board (and derivatives).
769 Note, the S3C2416 and the S3C2450 are so close that they even share
770 the same SoC ID code. This means that there is no separate machine
771 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
774 bool "Samsung S3C64XX"
782 select ARCH_USES_GETTIMEOFFSET
783 select ARCH_HAS_CPUFREQ
784 select ARCH_REQUIRE_GPIOLIB
785 select SAMSUNG_CLKSRC
786 select SAMSUNG_IRQ_VIC_TIMER
787 select S3C_GPIO_TRACK
789 select USB_ARCH_HAS_OHCI
790 select SAMSUNG_GPIOLIB_4BIT
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 Samsung S3C64XX series based systems
797 bool "Samsung S5P6440 S5P6450"
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select GENERIC_CLOCKEVENTS
805 select HAVE_SCHED_CLOCK
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C_RTC if RTC_CLASS
809 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
813 bool "Samsung S5PC100"
818 select ARM_L1_CACHE_SHIFT_6
819 select ARCH_USES_GETTIMEOFFSET
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C_RTC if RTC_CLASS
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 Samsung S5PC100 series based systems
827 bool "Samsung S5PV210/S5PC110"
829 select ARCH_SPARSEMEM_ENABLE
830 select ARCH_HAS_HOLES_MEMORYMODEL
835 select ARM_L1_CACHE_SHIFT_6
836 select ARCH_HAS_CPUFREQ
837 select GENERIC_CLOCKEVENTS
838 select HAVE_SCHED_CLOCK
839 select HAVE_S3C2410_I2C if I2C
840 select HAVE_S3C_RTC if RTC_CLASS
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
842 select NEED_MACH_MEMORY_H
844 Samsung S5PV210/S5PC110 series based systems
847 bool "SAMSUNG EXYNOS"
849 select ARCH_SPARSEMEM_ENABLE
850 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_HAS_CPUFREQ
855 select GENERIC_CLOCKEVENTS
856 select HAVE_S3C_RTC if RTC_CLASS
857 select HAVE_S3C2410_I2C if I2C
858 select HAVE_S3C2410_WATCHDOG if WATCHDOG
859 select NEED_MACH_MEMORY_H
861 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
870 select ARCH_USES_GETTIMEOFFSET
871 select NEED_MACH_MEMORY_H
873 Support for the StrongARM based Digital DNARD machine, also known
874 as "Shark" (<http://www.shark-linux.de/shark.html>).
877 bool "Telechips TCC ARM926-based systems"
882 select GENERIC_CLOCKEVENTS
884 Support for Telechips TCC ARM926-based systems.
887 bool "ST-Ericsson U300 Series"
891 select HAVE_SCHED_CLOCK
894 select ARM_PATCH_PHYS_VIRT
896 select GENERIC_CLOCKEVENTS
898 select HAVE_MACH_CLKDEV
900 select ARCH_REQUIRE_GPIOLIB
901 select NEED_MACH_MEMORY_H
903 Support for ST-Ericsson U300 series mobile platforms.
906 bool "ST-Ericsson U8500 Series"
909 select GENERIC_CLOCKEVENTS
911 select ARCH_REQUIRE_GPIOLIB
912 select ARCH_HAS_CPUFREQ
914 Support for ST-Ericsson's Ux500 architecture
917 bool "STMicroelectronics Nomadik"
922 select GENERIC_CLOCKEVENTS
923 select ARCH_REQUIRE_GPIOLIB
925 Support for the Nomadik platform by ST-Ericsson
929 select GENERIC_CLOCKEVENTS
930 select ARCH_REQUIRE_GPIOLIB
934 select GENERIC_ALLOCATOR
935 select GENERIC_IRQ_CHIP
936 select ARCH_HAS_HOLES_MEMORYMODEL
938 Support for TI's DaVinci platform.
943 select ARCH_REQUIRE_GPIOLIB
944 select ARCH_HAS_CPUFREQ
946 select GENERIC_CLOCKEVENTS
947 select HAVE_SCHED_CLOCK
948 select ARCH_HAS_HOLES_MEMORYMODEL
950 Support for TI's OMAP platform (OMAP1/2/3/4).
955 select ARCH_REQUIRE_GPIOLIB
958 select GENERIC_CLOCKEVENTS
961 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
964 bool "VIA/WonderMedia 85xx"
967 select ARCH_HAS_CPUFREQ
968 select GENERIC_CLOCKEVENTS
969 select ARCH_REQUIRE_GPIOLIB
972 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
975 bool "Xilinx Zynq ARM Cortex A9 Platform"
977 select GENERIC_CLOCKEVENTS
984 Support for Xilinx Zynq ARM Cortex A9 Platform
988 # This is sorted alphabetically by mach-* pathname. However, plat-*
989 # Kconfigs may be included either alphabetically (according to the
990 # plat- suffix) or along side the corresponding mach-* source.
992 source "arch/arm/mach-at91/Kconfig"
994 source "arch/arm/mach-bcmring/Kconfig"
996 source "arch/arm/mach-clps711x/Kconfig"
998 source "arch/arm/mach-cns3xxx/Kconfig"
1000 source "arch/arm/mach-davinci/Kconfig"
1002 source "arch/arm/mach-dove/Kconfig"
1004 source "arch/arm/mach-ep93xx/Kconfig"
1006 source "arch/arm/mach-footbridge/Kconfig"
1008 source "arch/arm/mach-gemini/Kconfig"
1010 source "arch/arm/mach-h720x/Kconfig"
1012 source "arch/arm/mach-integrator/Kconfig"
1014 source "arch/arm/mach-iop32x/Kconfig"
1016 source "arch/arm/mach-iop33x/Kconfig"
1018 source "arch/arm/mach-iop13xx/Kconfig"
1020 source "arch/arm/mach-ixp4xx/Kconfig"
1022 source "arch/arm/mach-ixp2000/Kconfig"
1024 source "arch/arm/mach-ixp23xx/Kconfig"
1026 source "arch/arm/mach-kirkwood/Kconfig"
1028 source "arch/arm/mach-ks8695/Kconfig"
1030 source "arch/arm/mach-lpc32xx/Kconfig"
1032 source "arch/arm/mach-msm/Kconfig"
1034 source "arch/arm/mach-mv78xx0/Kconfig"
1036 source "arch/arm/plat-mxc/Kconfig"
1038 source "arch/arm/mach-mxs/Kconfig"
1040 source "arch/arm/mach-netx/Kconfig"
1042 source "arch/arm/mach-nomadik/Kconfig"
1043 source "arch/arm/plat-nomadik/Kconfig"
1045 source "arch/arm/plat-omap/Kconfig"
1047 source "arch/arm/mach-omap1/Kconfig"
1049 source "arch/arm/mach-omap2/Kconfig"
1051 source "arch/arm/mach-orion5x/Kconfig"
1053 source "arch/arm/mach-pxa/Kconfig"
1054 source "arch/arm/plat-pxa/Kconfig"
1056 source "arch/arm/mach-mmp/Kconfig"
1058 source "arch/arm/mach-realview/Kconfig"
1060 source "arch/arm/mach-sa1100/Kconfig"
1062 source "arch/arm/plat-samsung/Kconfig"
1063 source "arch/arm/plat-s3c24xx/Kconfig"
1064 source "arch/arm/plat-s5p/Kconfig"
1066 source "arch/arm/plat-spear/Kconfig"
1068 source "arch/arm/plat-tcc/Kconfig"
1071 source "arch/arm/mach-s3c2410/Kconfig"
1072 source "arch/arm/mach-s3c2412/Kconfig"
1073 source "arch/arm/mach-s3c2416/Kconfig"
1074 source "arch/arm/mach-s3c2440/Kconfig"
1075 source "arch/arm/mach-s3c2443/Kconfig"
1079 source "arch/arm/mach-s3c64xx/Kconfig"
1082 source "arch/arm/mach-s5p64x0/Kconfig"
1084 source "arch/arm/mach-s5pc100/Kconfig"
1086 source "arch/arm/mach-s5pv210/Kconfig"
1088 source "arch/arm/mach-exynos/Kconfig"
1090 source "arch/arm/mach-shmobile/Kconfig"
1092 source "arch/arm/mach-tegra/Kconfig"
1094 source "arch/arm/mach-u300/Kconfig"
1096 source "arch/arm/mach-ux500/Kconfig"
1098 source "arch/arm/mach-versatile/Kconfig"
1100 source "arch/arm/mach-vexpress/Kconfig"
1101 source "arch/arm/plat-versatile/Kconfig"
1103 source "arch/arm/mach-vt8500/Kconfig"
1105 source "arch/arm/mach-w90x900/Kconfig"
1107 # Definitions to make life easier
1113 select GENERIC_CLOCKEVENTS
1114 select HAVE_SCHED_CLOCK
1119 select GENERIC_IRQ_CHIP
1120 select HAVE_SCHED_CLOCK
1125 config PLAT_VERSATILE
1128 config ARM_TIMER_SP804
1132 source arch/arm/mm/Kconfig
1135 bool "Enable iWMMXt support"
1136 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1137 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1139 Enable support for iWMMXt context switching at run time if
1140 running on a CPU that supports it.
1142 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1145 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1149 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1150 (!ARCH_OMAP3 || OMAP3_EMU)
1154 config MULTI_IRQ_HANDLER
1157 Allow each machine to specify it's own IRQ handler at run time.
1160 source "arch/arm/Kconfig-nommu"
1163 config ARM_ERRATA_326103
1164 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1167 Executing a SWP instruction to read-only memory does not set bit 11
1168 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1169 treat the access as a read, preventing a COW from occurring and
1170 causing the faulting task to livelock.
1172 config ARM_ERRATA_411920
1173 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1174 depends on CPU_V6 || CPU_V6K
1176 Invalidation of the Instruction Cache operation can
1177 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1178 It does not affect the MPCore. This option enables the ARM Ltd.
1179 recommended workaround.
1181 config ARM_ERRATA_430973
1182 bool "ARM errata: Stale prediction on replaced interworking branch"
1185 This option enables the workaround for the 430973 Cortex-A8
1186 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1187 interworking branch is replaced with another code sequence at the
1188 same virtual address, whether due to self-modifying code or virtual
1189 to physical address re-mapping, Cortex-A8 does not recover from the
1190 stale interworking branch prediction. This results in Cortex-A8
1191 executing the new code sequence in the incorrect ARM or Thumb state.
1192 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1193 and also flushes the branch target cache at every context switch.
1194 Note that setting specific bits in the ACTLR register may not be
1195 available in non-secure mode.
1197 config ARM_ERRATA_458693
1198 bool "ARM errata: Processor deadlock when a false hazard is created"
1201 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1202 erratum. For very specific sequences of memory operations, it is
1203 possible for a hazard condition intended for a cache line to instead
1204 be incorrectly associated with a different cache line. This false
1205 hazard might then cause a processor deadlock. The workaround enables
1206 the L1 caching of the NEON accesses and disables the PLD instruction
1207 in the ACTLR register. Note that setting specific bits in the ACTLR
1208 register may not be available in non-secure mode.
1210 config ARM_ERRATA_460075
1211 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1214 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1215 erratum. Any asynchronous access to the L2 cache may encounter a
1216 situation in which recent store transactions to the L2 cache are lost
1217 and overwritten with stale memory contents from external memory. The
1218 workaround disables the write-allocate mode for the L2 cache via the
1219 ACTLR register. Note that setting specific bits in the ACTLR register
1220 may not be available in non-secure mode.
1222 config ARM_ERRATA_742230
1223 bool "ARM errata: DMB operation may be faulty"
1224 depends on CPU_V7 && SMP
1226 This option enables the workaround for the 742230 Cortex-A9
1227 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1228 between two write operations may not ensure the correct visibility
1229 ordering of the two writes. This workaround sets a specific bit in
1230 the diagnostic register of the Cortex-A9 which causes the DMB
1231 instruction to behave as a DSB, ensuring the correct behaviour of
1234 config ARM_ERRATA_742231
1235 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1236 depends on CPU_V7 && SMP
1238 This option enables the workaround for the 742231 Cortex-A9
1239 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1240 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1241 accessing some data located in the same cache line, may get corrupted
1242 data due to bad handling of the address hazard when the line gets
1243 replaced from one of the CPUs at the same time as another CPU is
1244 accessing it. This workaround sets specific bits in the diagnostic
1245 register of the Cortex-A9 which reduces the linefill issuing
1246 capabilities of the processor.
1248 config PL310_ERRATA_588369
1249 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1250 depends on CACHE_L2X0
1252 The PL310 L2 cache controller implements three types of Clean &
1253 Invalidate maintenance operations: by Physical Address
1254 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1255 They are architecturally defined to behave as the execution of a
1256 clean operation followed immediately by an invalidate operation,
1257 both performing to the same memory location. This functionality
1258 is not correctly implemented in PL310 as clean lines are not
1259 invalidated as a result of these operations.
1261 config ARM_ERRATA_720789
1262 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1265 This option enables the workaround for the 720789 Cortex-A9 (prior to
1266 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1267 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1268 As a consequence of this erratum, some TLB entries which should be
1269 invalidated are not, resulting in an incoherency in the system page
1270 tables. The workaround changes the TLB flushing routines to invalidate
1271 entries regardless of the ASID.
1273 config PL310_ERRATA_727915
1274 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1275 depends on CACHE_L2X0
1277 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1278 operation (offset 0x7FC). This operation runs in background so that
1279 PL310 can handle normal accesses while it is in progress. Under very
1280 rare circumstances, due to this erratum, write data can be lost when
1281 PL310 treats a cacheable write transaction during a Clean &
1282 Invalidate by Way operation.
1284 config ARM_ERRATA_743622
1285 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1288 This option enables the workaround for the 743622 Cortex-A9
1289 (r2p*) erratum. Under very rare conditions, a faulty
1290 optimisation in the Cortex-A9 Store Buffer may lead to data
1291 corruption. This workaround sets a specific bit in the diagnostic
1292 register of the Cortex-A9 which disables the Store Buffer
1293 optimisation, preventing the defect from occurring. This has no
1294 visible impact on the overall performance or power consumption of the
1297 config ARM_ERRATA_751472
1298 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1301 This option enables the workaround for the 751472 Cortex-A9 (prior
1302 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1303 completion of a following broadcasted operation if the second
1304 operation is received by a CPU before the ICIALLUIS has completed,
1305 potentially leading to corrupted entries in the cache or TLB.
1307 config PL310_ERRATA_753970
1308 bool "PL310 errata: cache sync operation may be faulty"
1309 depends on CACHE_PL310
1311 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1313 Under some condition the effect of cache sync operation on
1314 the store buffer still remains when the operation completes.
1315 This means that the store buffer is always asked to drain and
1316 this prevents it from merging any further writes. The workaround
1317 is to replace the normal offset of cache sync operation (0x730)
1318 by another offset targeting an unmapped PL310 register 0x740.
1319 This has the same effect as the cache sync operation: store buffer
1320 drain and waiting for all buffers empty.
1322 config ARM_ERRATA_754322
1323 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1326 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1327 r3p*) erratum. A speculative memory access may cause a page table walk
1328 which starts prior to an ASID switch but completes afterwards. This
1329 can populate the micro-TLB with a stale entry which may be hit with
1330 the new ASID. This workaround places two dsb instructions in the mm
1331 switching code so that no page table walks can cross the ASID switch.
1333 config ARM_ERRATA_754327
1334 bool "ARM errata: no automatic Store Buffer drain"
1335 depends on CPU_V7 && SMP
1337 This option enables the workaround for the 754327 Cortex-A9 (prior to
1338 r2p0) erratum. The Store Buffer does not have any automatic draining
1339 mechanism and therefore a livelock may occur if an external agent
1340 continuously polls a memory location waiting to observe an update.
1341 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1342 written polling loops from denying visibility of updates to memory.
1344 config ARM_ERRATA_364296
1345 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1346 depends on CPU_V6 && !SMP
1348 This options enables the workaround for the 364296 ARM1136
1349 r0p2 erratum (possible cache data corruption with
1350 hit-under-miss enabled). It sets the undocumented bit 31 in
1351 the auxiliary control register and the FI bit in the control
1352 register, thus disabling hit-under-miss without putting the
1353 processor into full low interrupt latency mode. ARM11MPCore
1356 config ARM_ERRATA_764369
1357 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1358 depends on CPU_V7 && SMP
1360 This option enables the workaround for erratum 764369
1361 affecting Cortex-A9 MPCore with two or more processors (all
1362 current revisions). Under certain timing circumstances, a data
1363 cache line maintenance operation by MVA targeting an Inner
1364 Shareable memory region may fail to proceed up to either the
1365 Point of Coherency or to the Point of Unification of the
1366 system. This workaround adds a DSB instruction before the
1367 relevant cache maintenance functions and sets a specific bit
1368 in the diagnostic control register of the SCU.
1370 config PL310_ERRATA_769419
1371 bool "PL310 errata: no automatic Store Buffer drain"
1372 depends on CACHE_L2X0
1374 On revisions of the PL310 prior to r3p2, the Store Buffer does
1375 not automatically drain. This can cause normal, non-cacheable
1376 writes to be retained when the memory system is idle, leading
1377 to suboptimal I/O performance for drivers using coherent DMA.
1378 This option adds a write barrier to the cpu_idle loop so that,
1379 on systems with an outer cache, the store buffer is drained
1384 source "arch/arm/common/Kconfig"
1394 Find out whether you have ISA slots on your motherboard. ISA is the
1395 name of a bus system, i.e. the way the CPU talks to the other stuff
1396 inside your box. Other bus systems are PCI, EISA, MicroChannel
1397 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1398 newer boards don't support it. If you have ISA, say Y, otherwise N.
1400 # Select ISA DMA controller support
1405 # Select ISA DMA interface
1410 bool "PCI support" if MIGHT_HAVE_PCI
1412 Find out whether you have a PCI motherboard. PCI is the name of a
1413 bus system, i.e. the way the CPU talks to the other stuff inside
1414 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1415 VESA. If you have PCI, say Y, otherwise N.
1421 config PCI_NANOENGINE
1422 bool "BSE nanoEngine PCI support"
1423 depends on SA1100_NANOENGINE
1425 Enable PCI on the BSE nanoEngine board.
1430 # Select the host bridge type
1431 config PCI_HOST_VIA82C505
1433 depends on PCI && ARCH_SHARK
1436 config PCI_HOST_ITE8152
1438 depends on PCI && MACH_ARMCORE
1442 source "drivers/pci/Kconfig"
1444 source "drivers/pcmcia/Kconfig"
1448 menu "Kernel Features"
1450 source "kernel/time/Kconfig"
1453 bool "Symmetric Multi-Processing"
1454 depends on CPU_V6K || CPU_V7
1455 depends on GENERIC_CLOCKEVENTS
1456 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1457 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1458 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1459 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1461 select USE_GENERIC_SMP_HELPERS
1462 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1464 This enables support for systems with more than one CPU. If you have
1465 a system with only one CPU, like most personal computers, say N. If
1466 you have a system with more than one CPU, say Y.
1468 If you say N here, the kernel will run on single and multiprocessor
1469 machines, but will use only one CPU of a multiprocessor machine. If
1470 you say Y here, the kernel will run on many, but not all, single
1471 processor machines. On a single processor machine, the kernel will
1472 run faster if you say N here.
1474 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1475 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1476 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1478 If you don't know what to do here, say N.
1481 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1482 depends on EXPERIMENTAL
1483 depends on SMP && !XIP_KERNEL
1486 SMP kernels contain instructions which fail on non-SMP processors.
1487 Enabling this option allows the kernel to modify itself to make
1488 these instructions safe. Disabling it allows about 1K of space
1491 If you don't know what to do here, say Y.
1493 config ARM_CPU_TOPOLOGY
1494 bool "Support cpu topology definition"
1495 depends on SMP && CPU_V7
1498 Support ARM cpu topology definition. The MPIDR register defines
1499 affinity between processors which is then used to describe the cpu
1500 topology of an ARM System.
1503 bool "Multi-core scheduler support"
1504 depends on ARM_CPU_TOPOLOGY
1506 Multi-core scheduler support improves the CPU scheduler's decision
1507 making when dealing with multi-core CPU chips at a cost of slightly
1508 increased overhead in some places. If unsure say N here.
1511 bool "SMT scheduler support"
1512 depends on ARM_CPU_TOPOLOGY
1514 Improves the CPU scheduler's decision making when dealing with
1515 MultiThreading at a cost of slightly increased overhead in some
1516 places. If unsure say N here.
1521 This option enables support for the ARM system coherency unit
1528 This options enables support for the ARM timer and watchdog unit
1531 prompt "Memory split"
1534 Select the desired split between kernel and user memory.
1536 If you are not absolutely sure what you are doing, leave this
1540 bool "3G/1G user/kernel split"
1542 bool "2G/2G user/kernel split"
1544 bool "1G/3G user/kernel split"
1549 default 0x40000000 if VMSPLIT_1G
1550 default 0x80000000 if VMSPLIT_2G
1554 int "Maximum number of CPUs (2-32)"
1560 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1561 depends on SMP && HOTPLUG && EXPERIMENTAL
1563 Say Y here to experiment with turning CPUs off and on. CPUs
1564 can be controlled through /sys/devices/system/cpu.
1567 bool "Use local timer interrupts"
1570 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1572 Enable support for local timers on SMP platforms, rather then the
1573 legacy IPI broadcast method. Local timers allows the system
1574 accounting to be spread across the timer interval, preventing a
1575 "thundering herd" at every timer tick.
1577 source kernel/Kconfig.preempt
1581 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1582 ARCH_S5PV210 || ARCH_EXYNOS4
1583 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1584 default AT91_TIMER_HZ if ARCH_AT91
1585 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1588 config THUMB2_KERNEL
1589 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1590 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1592 select ARM_ASM_UNIFIED
1595 By enabling this option, the kernel will be compiled in
1596 Thumb-2 mode. A compiler/assembler that understand the unified
1597 ARM-Thumb syntax is needed.
1601 config THUMB2_AVOID_R_ARM_THM_JUMP11
1602 bool "Work around buggy Thumb-2 short branch relocations in gas"
1603 depends on THUMB2_KERNEL && MODULES
1606 Various binutils versions can resolve Thumb-2 branches to
1607 locally-defined, preemptible global symbols as short-range "b.n"
1608 branch instructions.
1610 This is a problem, because there's no guarantee the final
1611 destination of the symbol, or any candidate locations for a
1612 trampoline, are within range of the branch. For this reason, the
1613 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1614 relocation in modules at all, and it makes little sense to add
1617 The symptom is that the kernel fails with an "unsupported
1618 relocation" error when loading some modules.
1620 Until fixed tools are available, passing
1621 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1622 code which hits this problem, at the cost of a bit of extra runtime
1623 stack usage in some cases.
1625 The problem is described in more detail at:
1626 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1628 Only Thumb-2 kernels are affected.
1630 Unless you are sure your tools don't have this problem, say Y.
1632 config ARM_ASM_UNIFIED
1636 bool "Use the ARM EABI to compile the kernel"
1638 This option allows for the kernel to be compiled using the latest
1639 ARM ABI (aka EABI). This is only useful if you are using a user
1640 space environment that is also compiled with EABI.
1642 Since there are major incompatibilities between the legacy ABI and
1643 EABI, especially with regard to structure member alignment, this
1644 option also changes the kernel syscall calling convention to
1645 disambiguate both ABIs and allow for backward compatibility support
1646 (selected with CONFIG_OABI_COMPAT).
1648 To use this you need GCC version 4.0.0 or later.
1651 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1652 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1655 This option preserves the old syscall interface along with the
1656 new (ARM EABI) one. It also provides a compatibility layer to
1657 intercept syscalls that have structure arguments which layout
1658 in memory differs between the legacy ABI and the new ARM EABI
1659 (only for non "thumb" binaries). This option adds a tiny
1660 overhead to all syscalls and produces a slightly larger kernel.
1661 If you know you'll be using only pure EABI user space then you
1662 can say N here. If this option is not selected and you attempt
1663 to execute a legacy ABI binary then the result will be
1664 UNPREDICTABLE (in fact it can be predicted that it won't work
1665 at all). If in doubt say Y.
1667 config ARCH_HAS_HOLES_MEMORYMODEL
1670 config ARCH_SPARSEMEM_ENABLE
1673 config ARCH_SPARSEMEM_DEFAULT
1674 def_bool ARCH_SPARSEMEM_ENABLE
1676 config ARCH_SELECT_MEMORY_MODEL
1677 def_bool ARCH_SPARSEMEM_ENABLE
1679 config HAVE_ARCH_PFN_VALID
1680 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1683 bool "High Memory Support"
1686 The address space of ARM processors is only 4 Gigabytes large
1687 and it has to accommodate user address space, kernel address
1688 space as well as some memory mapped IO. That means that, if you
1689 have a large amount of physical memory and/or IO, not all of the
1690 memory can be "permanently mapped" by the kernel. The physical
1691 memory that is not permanently mapped is called "high memory".
1693 Depending on the selected kernel/user memory split, minimum
1694 vmalloc space and actual amount of RAM, you may not need this
1695 option which should result in a slightly faster kernel.
1700 bool "Allocate 2nd-level pagetables from highmem"
1703 config HW_PERF_EVENTS
1704 bool "Enable hardware performance counter support for perf events"
1705 depends on PERF_EVENTS && CPU_HAS_PMU
1708 Enable hardware performance counter support for perf events. If
1709 disabled, perf events will use software events only.
1711 config SYS_SUPPORTS_HUGETLBFS
1713 depends on ARM_LPAE || (!CPU_USE_DOMAINS && !MEMORY_FAILURE)
1715 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1717 depends on SYS_SUPPORTS_HUGETLBFS
1721 config FORCE_MAX_ZONEORDER
1722 int "Maximum zone order" if ARCH_SHMOBILE
1723 range 11 64 if ARCH_SHMOBILE
1724 default "9" if SA1111
1727 The kernel memory allocator divides physically contiguous memory
1728 blocks into "zones", where each zone is a power of two number of
1729 pages. This option selects the largest power of two that the kernel
1730 keeps in the memory allocator. If you need to allocate very large
1731 blocks of physically contiguous memory, then you may need to
1732 increase this value.
1734 This config option is actually maximum order plus one. For example,
1735 a value of 11 means that the largest free memory block is 2^10 pages.
1738 bool "Timer and CPU usage LEDs"
1739 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1740 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1741 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1742 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1743 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1744 ARCH_AT91 || ARCH_DAVINCI || \
1745 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1747 If you say Y here, the LEDs on your machine will be used
1748 to provide useful information about your current system status.
1750 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1751 be able to select which LEDs are active using the options below. If
1752 you are compiling a kernel for the EBSA-110 or the LART however, the
1753 red LED will simply flash regularly to indicate that the system is
1754 still functional. It is safe to say Y here if you have a CATS
1755 system, but the driver will do nothing.
1758 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1759 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1760 || MACH_OMAP_PERSEUS2
1762 depends on !GENERIC_CLOCKEVENTS
1763 default y if ARCH_EBSA110
1765 If you say Y here, one of the system LEDs (the green one on the
1766 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1767 will flash regularly to indicate that the system is still
1768 operational. This is mainly useful to kernel hackers who are
1769 debugging unstable kernels.
1771 The LART uses the same LED for both Timer LED and CPU usage LED
1772 functions. You may choose to use both, but the Timer LED function
1773 will overrule the CPU usage LED.
1776 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1778 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1779 || MACH_OMAP_PERSEUS2
1782 If you say Y here, the red LED will be used to give a good real
1783 time indication of CPU usage, by lighting whenever the idle task
1784 is not currently executing.
1786 The LART uses the same LED for both Timer LED and CPU usage LED
1787 functions. You may choose to use both, but the Timer LED function
1788 will overrule the CPU usage LED.
1790 config ALIGNMENT_TRAP
1791 bool "Enable alignment trap"
1792 depends on CPU_CP15_MMU
1793 default y if !ARCH_EBSA110
1794 select HAVE_PROC_CPU if PROC_FS
1796 ARM processors cannot fetch/store information which is not
1797 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1798 address divisible by 4. On 32-bit ARM processors, these non-aligned
1799 fetch/store instructions will be emulated in software if you say
1800 here, which has a severe performance impact. This is necessary for
1801 correct operation of some network protocols. With an IP-only
1802 configuration it is safe to say N, otherwise say Y.
1804 config UACCESS_WITH_MEMCPY
1805 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1806 depends on MMU && EXPERIMENTAL
1807 default y if CPU_FEROCEON
1809 Implement faster copy_to_user and clear_user methods for CPU
1810 cores where a 8-word STM instruction give significantly higher
1811 memory write throughput than a sequence of individual 32bit stores.
1813 A possible side effect is a slight increase in scheduling latency
1814 between threads sharing the same address space if they invoke
1815 such copy operations with large buffers.
1817 However, if the CPU data cache is using a write-allocate mode,
1818 this option is unlikely to provide any performance gain.
1822 prompt "Enable seccomp to safely compute untrusted bytecode"
1824 This kernel feature is useful for number crunching applications
1825 that may need to compute untrusted bytecode during their
1826 execution. By using pipes or other transports made available to
1827 the process as file descriptors supporting the read/write
1828 syscalls, it's possible to isolate those applications in
1829 their own address space using seccomp. Once seccomp is
1830 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1831 and the task is only allowed to execute a few safe syscalls
1832 defined by each seccomp mode.
1834 config CC_STACKPROTECTOR
1835 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1836 depends on EXPERIMENTAL
1838 This option turns on the -fstack-protector GCC feature. This
1839 feature puts, at the beginning of functions, a canary value on
1840 the stack just before the return address, and validates
1841 the value just before actually returning. Stack based buffer
1842 overflows (that need to overwrite this return address) now also
1843 overwrite the canary, which gets detected and the attack is then
1844 neutralized via a kernel panic.
1845 This feature requires gcc version 4.2 or above.
1847 config DEPRECATED_PARAM_STRUCT
1848 bool "Provide old way to pass kernel parameters"
1850 This was deprecated in 2001 and announced to live on for 5 years.
1851 Some old boot loaders still use this way.
1855 depends on CPU_V7 && SYSFS
1863 bool "Flattened Device Tree support"
1865 select OF_EARLY_FLATTREE
1868 Include support for flattened device tree machine descriptions.
1870 # Compressed boot loader in ROM. Yes, we really want to ask about
1871 # TEXT and BSS so we preserve their values in the config files.
1872 config ZBOOT_ROM_TEXT
1873 hex "Compressed ROM boot loader base address"
1876 The physical address at which the ROM-able zImage is to be
1877 placed in the target. Platforms which normally make use of
1878 ROM-able zImage formats normally set this to a suitable
1879 value in their defconfig file.
1881 If ZBOOT_ROM is not enabled, this has no effect.
1883 config ZBOOT_ROM_BSS
1884 hex "Compressed ROM boot loader BSS address"
1887 The base address of an area of read/write memory in the target
1888 for the ROM-able zImage which must be available while the
1889 decompressor is running. It must be large enough to hold the
1890 entire decompressed kernel plus an additional 128 KiB.
1891 Platforms which normally make use of ROM-able zImage formats
1892 normally set this to a suitable value in their defconfig file.
1894 If ZBOOT_ROM is not enabled, this has no effect.
1897 bool "Compressed boot loader in ROM/flash"
1898 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1900 Say Y here if you intend to execute your compressed kernel image
1901 (zImage) directly from ROM or flash. If unsure, say N.
1904 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1905 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1906 default ZBOOT_ROM_NONE
1908 Include experimental SD/MMC loading code in the ROM-able zImage.
1909 With this enabled it is possible to write the the ROM-able zImage
1910 kernel image to an MMC or SD card and boot the kernel straight
1911 from the reset vector. At reset the processor Mask ROM will load
1912 the first part of the the ROM-able zImage which in turn loads the
1913 rest the kernel image to RAM.
1915 config ZBOOT_ROM_NONE
1916 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1918 Do not load image from SD or MMC
1920 config ZBOOT_ROM_MMCIF
1921 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1923 Load image from MMCIF hardware block.
1925 config ZBOOT_ROM_SH_MOBILE_SDHI
1926 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1928 Load image from SDHI hardware block
1932 config ARM_APPENDED_DTB
1933 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1934 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1936 With this option, the boot code will look for a device tree binary
1937 (DTB) appended to zImage
1938 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1940 This is meant as a backward compatibility convenience for those
1941 systems with a bootloader that can't be upgraded to accommodate
1942 the documented boot protocol using a device tree.
1944 Beware that there is very little in terms of protection against
1945 this option being confused by leftover garbage in memory that might
1946 look like a DTB header after a reboot if no actual DTB is appended
1947 to zImage. Do not leave this option active in a production kernel
1948 if you don't intend to always append a DTB. Proper passing of the
1949 location into r2 of a bootloader provided DTB is always preferable
1952 config ARM_ATAG_DTB_COMPAT
1953 bool "Supplement the appended DTB with traditional ATAG information"
1954 depends on ARM_APPENDED_DTB
1956 Some old bootloaders can't be updated to a DTB capable one, yet
1957 they provide ATAGs with memory configuration, the ramdisk address,
1958 the kernel cmdline string, etc. Such information is dynamically
1959 provided by the bootloader and can't always be stored in a static
1960 DTB. To allow a device tree enabled kernel to be used with such
1961 bootloaders, this option allows zImage to extract the information
1962 from the ATAG list and store it at run time into the appended DTB.
1965 string "Default kernel command string"
1968 On some architectures (EBSA110 and CATS), there is currently no way
1969 for the boot loader to pass arguments to the kernel. For these
1970 architectures, you should supply some command-line options at build
1971 time by entering them here. As a minimum, you should specify the
1972 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1975 prompt "Kernel command line type" if CMDLINE != ""
1976 default CMDLINE_FROM_BOOTLOADER
1978 config CMDLINE_FROM_BOOTLOADER
1979 bool "Use bootloader kernel arguments if available"
1981 Uses the command-line options passed by the boot loader. If
1982 the boot loader doesn't provide any, the default kernel command
1983 string provided in CMDLINE will be used.
1985 config CMDLINE_EXTEND
1986 bool "Extend bootloader kernel arguments"
1988 The command-line arguments provided by the boot loader will be
1989 appended to the default kernel command string.
1991 config CMDLINE_FORCE
1992 bool "Always use the default kernel command string"
1994 Always use the default kernel command string, even if the boot
1995 loader passes other arguments to the kernel.
1996 This is useful if you cannot or don't want to change the
1997 command-line options your boot loader passes to the kernel.
2001 bool "Kernel Execute-In-Place from ROM"
2002 depends on !ZBOOT_ROM && !ARM_LPAE
2004 Execute-In-Place allows the kernel to run from non-volatile storage
2005 directly addressable by the CPU, such as NOR flash. This saves RAM
2006 space since the text section of the kernel is not loaded from flash
2007 to RAM. Read-write sections, such as the data section and stack,
2008 are still copied to RAM. The XIP kernel is not compressed since
2009 it has to run directly from flash, so it will take more space to
2010 store it. The flash address used to link the kernel object files,
2011 and for storing it, is configuration dependent. Therefore, if you
2012 say Y here, you must know the proper physical address where to
2013 store the kernel image depending on your own flash memory usage.
2015 Also note that the make target becomes "make xipImage" rather than
2016 "make zImage" or "make Image". The final kernel binary to put in
2017 ROM memory will be arch/arm/boot/xipImage.
2021 config XIP_PHYS_ADDR
2022 hex "XIP Kernel Physical Location"
2023 depends on XIP_KERNEL
2024 default "0x00080000"
2026 This is the physical address in your flash memory the kernel will
2027 be linked for and stored to. This address is dependent on your
2031 bool "Kexec system call (EXPERIMENTAL)"
2032 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2034 kexec is a system call that implements the ability to shutdown your
2035 current kernel, and to start another kernel. It is like a reboot
2036 but it is independent of the system firmware. And like a reboot
2037 you can start any kernel with it, not just Linux.
2039 It is an ongoing process to be certain the hardware in a machine
2040 is properly shutdown, so do not be surprised if this code does not
2041 initially work for you. It may help to enable device hotplugging
2045 bool "Export atags in procfs"
2049 Should the atags used to boot the kernel be exported in an "atags"
2050 file in procfs. Useful with kexec.
2053 bool "Build kdump crash kernel (EXPERIMENTAL)"
2054 depends on EXPERIMENTAL
2056 Generate crash dump after being started by kexec. This should
2057 be normally only set in special crash dump kernels which are
2058 loaded in the main kernel with kexec-tools into a specially
2059 reserved region and then later executed after a crash by
2060 kdump/kexec. The crash dump kernel must be compiled to a
2061 memory address not used by the main kernel
2063 For more details see Documentation/kdump/kdump.txt
2065 config AUTO_ZRELADDR
2066 bool "Auto calculation of the decompressed kernel image address"
2067 depends on !ZBOOT_ROM && !ARCH_U300
2069 ZRELADDR is the physical address where the decompressed kernel
2070 image will be placed. If AUTO_ZRELADDR is selected, the address
2071 will be determined at run-time by masking the current IP with
2072 0xf8000000. This assumes the zImage being placed in the first 128MB
2073 from start of memory.
2077 menu "CPU Power Management"
2081 source "drivers/cpufreq/Kconfig"
2084 tristate "CPUfreq driver for i.MX CPUs"
2085 depends on ARCH_MXC && CPU_FREQ
2086 select CPU_FREQ_TABLE
2088 This enables the CPUfreq driver for i.MX CPUs.
2090 config CPU_FREQ_SA1100
2093 config CPU_FREQ_SA1110
2096 config CPU_FREQ_INTEGRATOR
2097 tristate "CPUfreq driver for ARM Integrator CPUs"
2098 depends on ARCH_INTEGRATOR && CPU_FREQ
2101 This enables the CPUfreq driver for ARM Integrator CPUs.
2103 For details, take a look at <file:Documentation/cpu-freq>.
2109 depends on CPU_FREQ && ARCH_PXA && PXA25x
2111 select CPU_FREQ_TABLE
2112 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2117 Internal configuration node for common cpufreq on Samsung SoC
2119 config CPU_FREQ_S3C24XX
2120 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2121 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2124 This enables the CPUfreq driver for the Samsung S3C24XX family
2127 For details, take a look at <file:Documentation/cpu-freq>.
2131 config CPU_FREQ_S3C24XX_PLL
2132 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2133 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2135 Compile in support for changing the PLL frequency from the
2136 S3C24XX series CPUfreq driver. The PLL takes time to settle
2137 after a frequency change, so by default it is not enabled.
2139 This also means that the PLL tables for the selected CPU(s) will
2140 be built which may increase the size of the kernel image.
2142 config CPU_FREQ_S3C24XX_DEBUG
2143 bool "Debug CPUfreq Samsung driver core"
2144 depends on CPU_FREQ_S3C24XX
2146 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2148 config CPU_FREQ_S3C24XX_IODEBUG
2149 bool "Debug CPUfreq Samsung driver IO timing"
2150 depends on CPU_FREQ_S3C24XX
2152 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2154 config CPU_FREQ_S3C24XX_DEBUGFS
2155 bool "Export debugfs for CPUFreq"
2156 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2158 Export status information via debugfs.
2162 source "drivers/cpuidle/Kconfig"
2166 menu "Floating point emulation"
2168 comment "At least one emulation must be selected"
2171 bool "NWFPE math emulation"
2172 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2174 Say Y to include the NWFPE floating point emulator in the kernel.
2175 This is necessary to run most binaries. Linux does not currently
2176 support floating point hardware so you need to say Y here even if
2177 your machine has an FPA or floating point co-processor podule.
2179 You may say N here if you are going to load the Acorn FPEmulator
2180 early in the bootup.
2183 bool "Support extended precision"
2184 depends on FPE_NWFPE
2186 Say Y to include 80-bit support in the kernel floating-point
2187 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2188 Note that gcc does not generate 80-bit operations by default,
2189 so in most cases this option only enlarges the size of the
2190 floating point emulator without any good reason.
2192 You almost surely want to say N here.
2195 bool "FastFPE math emulation (EXPERIMENTAL)"
2196 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2198 Say Y here to include the FAST floating point emulator in the kernel.
2199 This is an experimental much faster emulator which now also has full
2200 precision for the mantissa. It does not support any exceptions.
2201 It is very simple, and approximately 3-6 times faster than NWFPE.
2203 It should be sufficient for most programs. It may be not suitable
2204 for scientific calculations, but you have to check this for yourself.
2205 If you do not feel you need a faster FP emulation you should better
2209 bool "VFP-format floating point maths"
2210 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2212 Say Y to include VFP support code in the kernel. This is needed
2213 if your hardware includes a VFP unit.
2215 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2216 release notes and additional status information.
2218 Say N if your target does not have VFP hardware.
2226 bool "Advanced SIMD (NEON) Extension support"
2227 depends on VFPv3 && CPU_V7
2229 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2234 menu "Userspace binary formats"
2236 source "fs/Kconfig.binfmt"
2239 tristate "RISC OS personality"
2242 Say Y here to include the kernel code necessary if you want to run
2243 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2244 experimental; if this sounds frightening, say N and sleep in peace.
2245 You can also say M here to compile this support as a module (which
2246 will be called arthur).
2250 menu "Power management options"
2252 source "kernel/power/Kconfig"
2254 config ARCH_SUSPEND_POSSIBLE
2255 depends on !ARCH_S5PC100
2256 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2257 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2260 config ARM_CPU_SUSPEND
2265 source "net/Kconfig"
2267 source "drivers/Kconfig"
2271 source "arch/arm/Kconfig.debug"
2273 source "security/Kconfig"
2275 source "crypto/Kconfig"
2277 source "lib/Kconfig"