4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
69 select MODULES_USE_ELF_REL
72 select OLD_SIGSUSPEND3
73 select PERF_USE_VMALLOC
75 select SYS_SUPPORTS_APM_EMULATION
76 # Above selects are sorted alphabetically; please add new ones
77 # according to that. Thanks.
79 The ARM series is a line of low-power-consumption RISC chip designs
80 licensed by ARM Ltd and targeted at embedded applications and
81 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
82 manufactured, but legacy ARM-based PC hardware remains popular in
83 Europe. There is an ARM Linux project with a web page at
84 <http://www.arm.linux.org.uk/>.
86 config ARM_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_BANDGAP
182 config GENERIC_HWEIGHT
186 config GENERIC_CALIBRATE_DELAY
190 config ARCH_MAY_HAVE_PC_FDC
196 config NEED_DMA_MAP_STATE
199 config ARCH_SUPPORTS_UPROBES
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_GPIO_H
246 Select this when mach/gpio.h is required to provide special
247 definitions for this platform. The need for mach/gpio.h should
248 be avoided when possible.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
267 default DRAM_BASE if !MMU
269 Please provide the physical address corresponding to the
270 location of main memory in your system.
276 source "init/Kconfig"
278 source "kernel/Kconfig.freezer"
283 bool "MMU-based Paged Memory Management Support"
286 Select if you want MMU-based virtualised addressing space
287 support by paged memory management. If unsure, say 'Y'.
290 # The "ARM system type" choice list is ordered alphabetically by option
291 # text. Please add new entries in the option alphabetic order.
294 prompt "ARM system type"
295 default ARCH_VERSATILE if !MMU
296 default ARCH_MULTIPLATFORM if MMU
298 config ARCH_MULTIPLATFORM
299 bool "Allow multiple platforms to be selected"
301 select ARCH_WANT_OPTIONAL_GPIOLIB
302 select ARM_HAS_SG_CHAIN
303 select ARM_PATCH_PHYS_VIRT
307 select GENERIC_CLOCKEVENTS
308 select MIGHT_HAVE_PCI
309 select MULTI_IRQ_HANDLER
313 config ARCH_INTEGRATOR
314 bool "ARM Ltd. Integrator family"
316 select ARM_PATCH_PHYS_VIRT
319 select COMMON_CLK_VERSATILE
320 select GENERIC_CLOCKEVENTS
323 select MULTI_IRQ_HANDLER
324 select NEED_MACH_MEMORY_H
325 select PLAT_VERSATILE
328 select VERSATILE_FPGA_IRQ
330 Support for ARM's Integrator platform.
333 bool "ARM Ltd. RealView family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_TIMER_SP804
338 select COMMON_CLK_VERSATILE
339 select GENERIC_CLOCKEVENTS
340 select GPIO_PL061 if GPIOLIB
342 select NEED_MACH_MEMORY_H
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
346 This enables support for ARM Ltd RealView boards.
348 config ARCH_VERSATILE
349 bool "ARM Ltd. Versatile family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select HAVE_MACH_CLKDEV
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_CLCD
360 select PLAT_VERSATILE_CLOCK
361 select VERSATILE_FPGA_IRQ
363 This enables support for ARM Ltd Versatile board.
367 select ARCH_REQUIRE_GPIOLIB
370 select NEED_MACH_IO_H if PCCARD
372 select PINCTRL_AT91 if USE_OF
374 This enables support for systems based on Atmel
375 AT91RM9200 and AT91SAM9* processors.
378 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
379 select ARCH_REQUIRE_GPIOLIB
384 select GENERIC_CLOCKEVENTS
387 Support for Cirrus Logic 711x/721x/731x based boards.
390 bool "Cortina Systems Gemini"
391 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
396 Support for the Cortina Systems Gemini family SoCs
400 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_IO_H
404 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
413 bool "Energy Micro efm32"
415 select ARCH_REQUIRE_GPIOLIB
421 select GENERIC_CLOCKEVENTS
427 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
432 select ARCH_HAS_HOLES_MEMORYMODEL
433 select ARCH_REQUIRE_GPIOLIB
434 select ARCH_USES_GETTIMEOFFSET
439 select NEED_MACH_MEMORY_H
441 This enables support for the Cirrus EP93xx series of CPUs.
443 config ARCH_FOOTBRIDGE
447 select GENERIC_CLOCKEVENTS
449 select NEED_MACH_IO_H if !MMU
450 select NEED_MACH_MEMORY_H
452 Support for systems based on the DC21285 companion chip
453 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
456 bool "Hilscher NetX based"
460 select GENERIC_CLOCKEVENTS
462 This enables support for systems based on the Hilscher NetX Soc
468 select NEED_MACH_MEMORY_H
469 select NEED_RET_TO_USER
475 Support for Intel's IOP13XX (XScale) family of processors.
480 select ARCH_REQUIRE_GPIOLIB
483 select NEED_RET_TO_USER
487 Support for Intel's 80219 and IOP32X (XScale) family of
493 select ARCH_REQUIRE_GPIOLIB
496 select NEED_RET_TO_USER
500 Support for Intel's IOP33X (XScale) family of processors.
505 select ARCH_HAS_DMA_SET_COHERENT_MASK
506 select ARCH_REQUIRE_GPIOLIB
507 select ARCH_SUPPORTS_BIG_ENDIAN
510 select DMABOUNCE if PCI
511 select GENERIC_CLOCKEVENTS
512 select MIGHT_HAVE_PCI
513 select NEED_MACH_IO_H
514 select USB_EHCI_BIG_ENDIAN_DESC
515 select USB_EHCI_BIG_ENDIAN_MMIO
517 Support for Intel's IXP4XX (XScale) family of processors.
521 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
524 select MIGHT_HAVE_PCI
528 select PLAT_ORION_LEGACY
530 Support for the Marvell Dove SoC 88AP510
533 bool "Marvell MV78xx0"
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION_LEGACY
541 Support for the following Marvell MV78xx0 series SoCs:
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell Orion 5x series SoCs:
555 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
556 Orion-2 (5281), Orion-1-90 (6183).
559 bool "Marvell PXA168/910/MMP2"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_ALLOCATOR
564 select GENERIC_CLOCKEVENTS
567 select MULTI_IRQ_HANDLER
572 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
575 bool "Micrel/Kendin KS8695"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_MEMORY_H
582 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
583 System-on-Chip devices.
586 bool "Nuvoton W90X900 CPU"
587 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
593 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
594 At present, the w90x900 has been renamed nuc900, regarding
595 the ARM series product line, you can login the following
596 link address to know more.
598 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
599 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
603 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
612 Support for the NXP LPC32XX family of processors
615 bool "PXA2xx/PXA3xx-based"
618 select ARCH_REQUIRE_GPIOLIB
619 select ARM_CPU_SUSPEND if PM
623 select GENERIC_CLOCKEVENTS
626 select MULTI_IRQ_HANDLER
630 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
633 bool "Qualcomm MSM (non-multiplatform)"
634 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
638 Support for Qualcomm MSM/QSD based systems. This runs on the
639 apps processor of the MSM/QSD and depends on a shared memory
640 interface to the modem processor which runs the baseband
641 stack and controls some vital subsystems
642 (clock and power control, etc).
644 config ARCH_SHMOBILE_LEGACY
645 bool "Renesas ARM SoCs (non-multiplatform)"
647 select ARM_PATCH_PHYS_VIRT
649 select GENERIC_CLOCKEVENTS
650 select HAVE_ARM_SCU if SMP
651 select HAVE_ARM_TWD if SMP
652 select HAVE_MACH_CLKDEV
654 select MIGHT_HAVE_CACHE_L2X0
655 select MULTI_IRQ_HANDLER
658 select PM_GENERIC_DOMAINS if PM
661 Support for Renesas ARM SoC platforms using a non-multiplatform
662 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
668 select ARCH_MAY_HAVE_PC_FDC
669 select ARCH_SPARSEMEM_ENABLE
670 select ARCH_USES_GETTIMEOFFSET
674 select HAVE_PATA_PLATFORM
676 select NEED_MACH_IO_H
677 select NEED_MACH_MEMORY_H
681 On the Acorn Risc-PC, Linux can support the internal IDE disk and
682 CD-ROM interface, serial and parallel port, and the floppy drive.
687 select ARCH_REQUIRE_GPIOLIB
688 select ARCH_SPARSEMEM_ENABLE
693 select GENERIC_CLOCKEVENTS
696 select NEED_MACH_MEMORY_H
699 Support for StrongARM 11x0 based boards.
702 bool "Samsung S3C24XX SoCs"
703 select ARCH_REQUIRE_GPIOLIB
706 select CLKSRC_SAMSUNG_PWM
707 select GENERIC_CLOCKEVENTS
709 select HAVE_S3C2410_I2C if I2C
710 select HAVE_S3C2410_WATCHDOG if WATCHDOG
711 select HAVE_S3C_RTC if RTC_CLASS
712 select MULTI_IRQ_HANDLER
713 select NEED_MACH_IO_H
716 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
717 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
718 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
719 Samsung SMDK2410 development board (and derivatives).
722 bool "Samsung S3C64XX"
723 select ARCH_REQUIRE_GPIOLIB
728 select CLKSRC_SAMSUNG_PWM
729 select COMMON_CLK_SAMSUNG
731 select GENERIC_CLOCKEVENTS
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select PM_GENERIC_DOMAINS if PM
740 select S3C_GPIO_TRACK
742 select SAMSUNG_WAKEMASK
743 select SAMSUNG_WDT_RESET
745 Samsung S3C64XX series based systems
749 select ARCH_HAS_HOLES_MEMORYMODEL
750 select ARCH_REQUIRE_GPIOLIB
752 select GENERIC_ALLOCATOR
753 select GENERIC_CLOCKEVENTS
754 select GENERIC_IRQ_CHIP
760 Support for TI's DaVinci platform.
765 select ARCH_HAS_HOLES_MEMORYMODEL
767 select ARCH_REQUIRE_GPIOLIB
770 select GENERIC_CLOCKEVENTS
771 select GENERIC_IRQ_CHIP
774 select NEED_MACH_IO_H if PCCARD
775 select NEED_MACH_MEMORY_H
777 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
781 menu "Multiple platform selection"
782 depends on ARCH_MULTIPLATFORM
784 comment "CPU Core family selection"
787 bool "ARMv4 based platforms (FA526)"
788 depends on !ARCH_MULTI_V6_V7
789 select ARCH_MULTI_V4_V5
792 config ARCH_MULTI_V4T
793 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
794 depends on !ARCH_MULTI_V6_V7
795 select ARCH_MULTI_V4_V5
796 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
797 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
798 CPU_ARM925T || CPU_ARM940T)
801 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
802 depends on !ARCH_MULTI_V6_V7
803 select ARCH_MULTI_V4_V5
804 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
805 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
806 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
808 config ARCH_MULTI_V4_V5
812 bool "ARMv6 based platforms (ARM11)"
813 select ARCH_MULTI_V6_V7
817 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
819 select ARCH_MULTI_V6_V7
823 config ARCH_MULTI_V6_V7
825 select MIGHT_HAVE_CACHE_L2X0
827 config ARCH_MULTI_CPU_AUTO
828 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
834 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
838 select HAVE_ARM_ARCH_TIMER
841 # This is sorted alphabetically by mach-* pathname. However, plat-*
842 # Kconfigs may be included either alphabetically (according to the
843 # plat- suffix) or along side the corresponding mach-* source.
845 source "arch/arm/mach-mvebu/Kconfig"
847 source "arch/arm/mach-at91/Kconfig"
849 source "arch/arm/mach-axxia/Kconfig"
851 source "arch/arm/mach-bcm/Kconfig"
853 source "arch/arm/mach-berlin/Kconfig"
855 source "arch/arm/mach-clps711x/Kconfig"
857 source "arch/arm/mach-cns3xxx/Kconfig"
859 source "arch/arm/mach-davinci/Kconfig"
861 source "arch/arm/mach-dove/Kconfig"
863 source "arch/arm/mach-ep93xx/Kconfig"
865 source "arch/arm/mach-footbridge/Kconfig"
867 source "arch/arm/mach-gemini/Kconfig"
869 source "arch/arm/mach-highbank/Kconfig"
871 source "arch/arm/mach-hisi/Kconfig"
873 source "arch/arm/mach-integrator/Kconfig"
875 source "arch/arm/mach-iop32x/Kconfig"
877 source "arch/arm/mach-iop33x/Kconfig"
879 source "arch/arm/mach-iop13xx/Kconfig"
881 source "arch/arm/mach-ixp4xx/Kconfig"
883 source "arch/arm/mach-keystone/Kconfig"
885 source "arch/arm/mach-ks8695/Kconfig"
887 source "arch/arm/mach-msm/Kconfig"
889 source "arch/arm/mach-moxart/Kconfig"
891 source "arch/arm/mach-mv78xx0/Kconfig"
893 source "arch/arm/mach-imx/Kconfig"
895 source "arch/arm/mach-mediatek/Kconfig"
897 source "arch/arm/mach-mxs/Kconfig"
899 source "arch/arm/mach-netx/Kconfig"
901 source "arch/arm/mach-nomadik/Kconfig"
903 source "arch/arm/mach-nspire/Kconfig"
905 source "arch/arm/plat-omap/Kconfig"
907 source "arch/arm/mach-omap1/Kconfig"
909 source "arch/arm/mach-omap2/Kconfig"
911 source "arch/arm/mach-orion5x/Kconfig"
913 source "arch/arm/mach-picoxcell/Kconfig"
915 source "arch/arm/mach-pxa/Kconfig"
916 source "arch/arm/plat-pxa/Kconfig"
918 source "arch/arm/mach-mmp/Kconfig"
920 source "arch/arm/mach-qcom/Kconfig"
922 source "arch/arm/mach-realview/Kconfig"
924 source "arch/arm/mach-rockchip/Kconfig"
926 source "arch/arm/mach-sa1100/Kconfig"
928 source "arch/arm/mach-socfpga/Kconfig"
930 source "arch/arm/mach-spear/Kconfig"
932 source "arch/arm/mach-sti/Kconfig"
934 source "arch/arm/mach-s3c24xx/Kconfig"
936 source "arch/arm/mach-s3c64xx/Kconfig"
938 source "arch/arm/mach-s5pv210/Kconfig"
940 source "arch/arm/mach-exynos/Kconfig"
941 source "arch/arm/plat-samsung/Kconfig"
943 source "arch/arm/mach-shmobile/Kconfig"
945 source "arch/arm/mach-sunxi/Kconfig"
947 source "arch/arm/mach-prima2/Kconfig"
949 source "arch/arm/mach-tegra/Kconfig"
951 source "arch/arm/mach-u300/Kconfig"
953 source "arch/arm/mach-ux500/Kconfig"
955 source "arch/arm/mach-versatile/Kconfig"
957 source "arch/arm/mach-vexpress/Kconfig"
958 source "arch/arm/plat-versatile/Kconfig"
960 source "arch/arm/mach-vt8500/Kconfig"
962 source "arch/arm/mach-w90x900/Kconfig"
964 source "arch/arm/mach-zynq/Kconfig"
966 # Definitions to make life easier
972 select GENERIC_CLOCKEVENTS
978 select GENERIC_IRQ_CHIP
981 config PLAT_ORION_LEGACY
988 config PLAT_VERSATILE
991 config ARM_TIMER_SP804
994 select CLKSRC_OF if OF
996 source "arch/arm/firmware/Kconfig"
998 source arch/arm/mm/Kconfig
1001 bool "Enable iWMMXt support"
1002 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1003 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1005 Enable support for iWMMXt context switching at run time if
1006 running on a CPU that supports it.
1008 config MULTI_IRQ_HANDLER
1011 Allow each machine to specify it's own IRQ handler at run time.
1014 source "arch/arm/Kconfig-nommu"
1017 config PJ4B_ERRATA_4742
1018 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1019 depends on CPU_PJ4B && MACH_ARMADA_370
1022 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1023 Event (WFE) IDLE states, a specific timing sensitivity exists between
1024 the retiring WFI/WFE instructions and the newly issued subsequent
1025 instructions. This sensitivity can result in a CPU hang scenario.
1027 The software must insert either a Data Synchronization Barrier (DSB)
1028 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1031 config ARM_ERRATA_326103
1032 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1035 Executing a SWP instruction to read-only memory does not set bit 11
1036 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1037 treat the access as a read, preventing a COW from occurring and
1038 causing the faulting task to livelock.
1040 config ARM_ERRATA_411920
1041 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1042 depends on CPU_V6 || CPU_V6K
1044 Invalidation of the Instruction Cache operation can
1045 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1046 It does not affect the MPCore. This option enables the ARM Ltd.
1047 recommended workaround.
1049 config ARM_ERRATA_430973
1050 bool "ARM errata: Stale prediction on replaced interworking branch"
1053 This option enables the workaround for the 430973 Cortex-A8
1054 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1055 interworking branch is replaced with another code sequence at the
1056 same virtual address, whether due to self-modifying code or virtual
1057 to physical address re-mapping, Cortex-A8 does not recover from the
1058 stale interworking branch prediction. This results in Cortex-A8
1059 executing the new code sequence in the incorrect ARM or Thumb state.
1060 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1061 and also flushes the branch target cache at every context switch.
1062 Note that setting specific bits in the ACTLR register may not be
1063 available in non-secure mode.
1065 config ARM_ERRATA_458693
1066 bool "ARM errata: Processor deadlock when a false hazard is created"
1068 depends on !ARCH_MULTIPLATFORM
1070 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1071 erratum. For very specific sequences of memory operations, it is
1072 possible for a hazard condition intended for a cache line to instead
1073 be incorrectly associated with a different cache line. This false
1074 hazard might then cause a processor deadlock. The workaround enables
1075 the L1 caching of the NEON accesses and disables the PLD instruction
1076 in the ACTLR register. Note that setting specific bits in the ACTLR
1077 register may not be available in non-secure mode.
1079 config ARM_ERRATA_460075
1080 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1082 depends on !ARCH_MULTIPLATFORM
1084 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1085 erratum. Any asynchronous access to the L2 cache may encounter a
1086 situation in which recent store transactions to the L2 cache are lost
1087 and overwritten with stale memory contents from external memory. The
1088 workaround disables the write-allocate mode for the L2 cache via the
1089 ACTLR register. Note that setting specific bits in the ACTLR register
1090 may not be available in non-secure mode.
1092 config ARM_ERRATA_742230
1093 bool "ARM errata: DMB operation may be faulty"
1094 depends on CPU_V7 && SMP
1095 depends on !ARCH_MULTIPLATFORM
1097 This option enables the workaround for the 742230 Cortex-A9
1098 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1099 between two write operations may not ensure the correct visibility
1100 ordering of the two writes. This workaround sets a specific bit in
1101 the diagnostic register of the Cortex-A9 which causes the DMB
1102 instruction to behave as a DSB, ensuring the correct behaviour of
1105 config ARM_ERRATA_742231
1106 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1107 depends on CPU_V7 && SMP
1108 depends on !ARCH_MULTIPLATFORM
1110 This option enables the workaround for the 742231 Cortex-A9
1111 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1112 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1113 accessing some data located in the same cache line, may get corrupted
1114 data due to bad handling of the address hazard when the line gets
1115 replaced from one of the CPUs at the same time as another CPU is
1116 accessing it. This workaround sets specific bits in the diagnostic
1117 register of the Cortex-A9 which reduces the linefill issuing
1118 capabilities of the processor.
1120 config ARM_ERRATA_643719
1121 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1122 depends on CPU_V7 && SMP
1124 This option enables the workaround for the 643719 Cortex-A9 (prior to
1125 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1126 register returns zero when it should return one. The workaround
1127 corrects this value, ensuring cache maintenance operations which use
1128 it behave as intended and avoiding data corruption.
1130 config ARM_ERRATA_720789
1131 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1134 This option enables the workaround for the 720789 Cortex-A9 (prior to
1135 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1136 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1137 As a consequence of this erratum, some TLB entries which should be
1138 invalidated are not, resulting in an incoherency in the system page
1139 tables. The workaround changes the TLB flushing routines to invalidate
1140 entries regardless of the ASID.
1142 config ARM_ERRATA_743622
1143 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1145 depends on !ARCH_MULTIPLATFORM
1147 This option enables the workaround for the 743622 Cortex-A9
1148 (r2p*) erratum. Under very rare conditions, a faulty
1149 optimisation in the Cortex-A9 Store Buffer may lead to data
1150 corruption. This workaround sets a specific bit in the diagnostic
1151 register of the Cortex-A9 which disables the Store Buffer
1152 optimisation, preventing the defect from occurring. This has no
1153 visible impact on the overall performance or power consumption of the
1156 config ARM_ERRATA_751472
1157 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1159 depends on !ARCH_MULTIPLATFORM
1161 This option enables the workaround for the 751472 Cortex-A9 (prior
1162 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1163 completion of a following broadcasted operation if the second
1164 operation is received by a CPU before the ICIALLUIS has completed,
1165 potentially leading to corrupted entries in the cache or TLB.
1167 config ARM_ERRATA_754322
1168 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1171 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1172 r3p*) erratum. A speculative memory access may cause a page table walk
1173 which starts prior to an ASID switch but completes afterwards. This
1174 can populate the micro-TLB with a stale entry which may be hit with
1175 the new ASID. This workaround places two dsb instructions in the mm
1176 switching code so that no page table walks can cross the ASID switch.
1178 config ARM_ERRATA_754327
1179 bool "ARM errata: no automatic Store Buffer drain"
1180 depends on CPU_V7 && SMP
1182 This option enables the workaround for the 754327 Cortex-A9 (prior to
1183 r2p0) erratum. The Store Buffer does not have any automatic draining
1184 mechanism and therefore a livelock may occur if an external agent
1185 continuously polls a memory location waiting to observe an update.
1186 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1187 written polling loops from denying visibility of updates to memory.
1189 config ARM_ERRATA_364296
1190 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1193 This options enables the workaround for the 364296 ARM1136
1194 r0p2 erratum (possible cache data corruption with
1195 hit-under-miss enabled). It sets the undocumented bit 31 in
1196 the auxiliary control register and the FI bit in the control
1197 register, thus disabling hit-under-miss without putting the
1198 processor into full low interrupt latency mode. ARM11MPCore
1201 config ARM_ERRATA_764369
1202 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1203 depends on CPU_V7 && SMP
1205 This option enables the workaround for erratum 764369
1206 affecting Cortex-A9 MPCore with two or more processors (all
1207 current revisions). Under certain timing circumstances, a data
1208 cache line maintenance operation by MVA targeting an Inner
1209 Shareable memory region may fail to proceed up to either the
1210 Point of Coherency or to the Point of Unification of the
1211 system. This workaround adds a DSB instruction before the
1212 relevant cache maintenance functions and sets a specific bit
1213 in the diagnostic control register of the SCU.
1215 config ARM_ERRATA_775420
1216 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1219 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1220 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1221 operation aborts with MMU exception, it might cause the processor
1222 to deadlock. This workaround puts DSB before executing ISB if
1223 an abort may occur on cache maintenance.
1225 config ARM_ERRATA_798181
1226 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1227 depends on CPU_V7 && SMP
1229 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1230 adequately shooting down all use of the old entries. This
1231 option enables the Linux kernel workaround for this erratum
1232 which sends an IPI to the CPUs that are running the same ASID
1233 as the one being invalidated.
1235 config ARM_ERRATA_773022
1236 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1239 This option enables the workaround for the 773022 Cortex-A15
1240 (up to r0p4) erratum. In certain rare sequences of code, the
1241 loop buffer may deliver incorrect instructions. This
1242 workaround disables the loop buffer to avoid the erratum.
1246 source "arch/arm/common/Kconfig"
1256 Find out whether you have ISA slots on your motherboard. ISA is the
1257 name of a bus system, i.e. the way the CPU talks to the other stuff
1258 inside your box. Other bus systems are PCI, EISA, MicroChannel
1259 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1260 newer boards don't support it. If you have ISA, say Y, otherwise N.
1262 # Select ISA DMA controller support
1267 # Select ISA DMA interface
1272 bool "PCI support" if MIGHT_HAVE_PCI
1274 Find out whether you have a PCI motherboard. PCI is the name of a
1275 bus system, i.e. the way the CPU talks to the other stuff inside
1276 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1277 VESA. If you have PCI, say Y, otherwise N.
1283 config PCI_NANOENGINE
1284 bool "BSE nanoEngine PCI support"
1285 depends on SA1100_NANOENGINE
1287 Enable PCI on the BSE nanoEngine board.
1292 config PCI_HOST_ITE8152
1294 depends on PCI && MACH_ARMCORE
1298 source "drivers/pci/Kconfig"
1299 source "drivers/pci/pcie/Kconfig"
1301 source "drivers/pcmcia/Kconfig"
1305 menu "Kernel Features"
1310 This option should be selected by machines which have an SMP-
1313 The only effect of this option is to make the SMP-related
1314 options available to the user for configuration.
1317 bool "Symmetric Multi-Processing"
1318 depends on CPU_V6K || CPU_V7
1319 depends on GENERIC_CLOCKEVENTS
1321 depends on MMU || ARM_MPU
1323 This enables support for systems with more than one CPU. If you have
1324 a system with only one CPU, say N. If you have a system with more
1325 than one CPU, say Y.
1327 If you say N here, the kernel will run on uni- and multiprocessor
1328 machines, but will use only one CPU of a multiprocessor machine. If
1329 you say Y here, the kernel will run on many, but not all,
1330 uniprocessor machines. On a uniprocessor machine, the kernel
1331 will run faster if you say N here.
1333 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1334 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1335 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1337 If you don't know what to do here, say N.
1340 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1341 depends on SMP && !XIP_KERNEL && MMU
1344 SMP kernels contain instructions which fail on non-SMP processors.
1345 Enabling this option allows the kernel to modify itself to make
1346 these instructions safe. Disabling it allows about 1K of space
1349 If you don't know what to do here, say Y.
1351 config ARM_CPU_TOPOLOGY
1352 bool "Support cpu topology definition"
1353 depends on SMP && CPU_V7
1356 Support ARM cpu topology definition. The MPIDR register defines
1357 affinity between processors which is then used to describe the cpu
1358 topology of an ARM System.
1361 bool "Multi-core scheduler support"
1362 depends on ARM_CPU_TOPOLOGY
1364 Multi-core scheduler support improves the CPU scheduler's decision
1365 making when dealing with multi-core CPU chips at a cost of slightly
1366 increased overhead in some places. If unsure say N here.
1369 bool "SMT scheduler support"
1370 depends on ARM_CPU_TOPOLOGY
1372 Improves the CPU scheduler's decision making when dealing with
1373 MultiThreading at a cost of slightly increased overhead in some
1374 places. If unsure say N here.
1379 This option enables support for the ARM system coherency unit
1381 config HAVE_ARM_ARCH_TIMER
1382 bool "Architected timer support"
1384 select ARM_ARCH_TIMER
1385 select GENERIC_CLOCKEVENTS
1387 This option enables support for the ARM architected timer
1392 select CLKSRC_OF if OF
1394 This options enables support for the ARM timer and watchdog unit
1397 bool "Multi-Cluster Power Management"
1398 depends on CPU_V7 && SMP
1400 This option provides the common power management infrastructure
1401 for (multi-)cluster based systems, such as big.LITTLE based
1405 bool "big.LITTLE support (Experimental)"
1406 depends on CPU_V7 && SMP
1409 This option enables support selections for the big.LITTLE
1410 system architecture.
1413 bool "big.LITTLE switcher support"
1414 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1415 select ARM_CPU_SUSPEND
1418 The big.LITTLE "switcher" provides the core functionality to
1419 transparently handle transition between a cluster of A15's
1420 and a cluster of A7's in a big.LITTLE system.
1422 config BL_SWITCHER_DUMMY_IF
1423 tristate "Simple big.LITTLE switcher user interface"
1424 depends on BL_SWITCHER && DEBUG_KERNEL
1426 This is a simple and dummy char dev interface to control
1427 the big.LITTLE switcher core code. It is meant for
1428 debugging purposes only.
1431 prompt "Memory split"
1435 Select the desired split between kernel and user memory.
1437 If you are not absolutely sure what you are doing, leave this
1441 bool "3G/1G user/kernel split"
1443 bool "2G/2G user/kernel split"
1445 bool "1G/3G user/kernel split"
1450 default PHYS_OFFSET if !MMU
1451 default 0x40000000 if VMSPLIT_1G
1452 default 0x80000000 if VMSPLIT_2G
1456 int "Maximum number of CPUs (2-32)"
1462 bool "Support for hot-pluggable CPUs"
1465 Say Y here to experiment with turning CPUs off and on. CPUs
1466 can be controlled through /sys/devices/system/cpu.
1469 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1472 Say Y here if you want Linux to communicate with system firmware
1473 implementing the PSCI specification for CPU-centric power
1474 management operations described in ARM document number ARM DEN
1475 0022A ("Power State Coordination Interface System Software on
1478 # The GPIO number here must be sorted by descending number. In case of
1479 # a multiplatform kernel, we just want the highest value required by the
1480 # selected platforms.
1483 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1484 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1485 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1486 default 416 if ARCH_SUNXI
1487 default 392 if ARCH_U8500
1488 default 352 if ARCH_VT8500
1489 default 264 if MACH_H4700
1492 Maximum number of GPIOs in the system.
1494 If unsure, leave the default value.
1496 source kernel/Kconfig.preempt
1500 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1501 ARCH_S5PV210 || ARCH_EXYNOS4
1502 default AT91_TIMER_HZ if ARCH_AT91
1503 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1507 depends on HZ_FIXED = 0
1508 prompt "Timer frequency"
1532 default HZ_FIXED if HZ_FIXED != 0
1533 default 100 if HZ_100
1534 default 200 if HZ_200
1535 default 250 if HZ_250
1536 default 300 if HZ_300
1537 default 500 if HZ_500
1541 def_bool HIGH_RES_TIMERS
1543 config THUMB2_KERNEL
1544 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1545 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1546 default y if CPU_THUMBONLY
1548 select ARM_ASM_UNIFIED
1551 By enabling this option, the kernel will be compiled in
1552 Thumb-2 mode. A compiler/assembler that understand the unified
1553 ARM-Thumb syntax is needed.
1557 config THUMB2_AVOID_R_ARM_THM_JUMP11
1558 bool "Work around buggy Thumb-2 short branch relocations in gas"
1559 depends on THUMB2_KERNEL && MODULES
1562 Various binutils versions can resolve Thumb-2 branches to
1563 locally-defined, preemptible global symbols as short-range "b.n"
1564 branch instructions.
1566 This is a problem, because there's no guarantee the final
1567 destination of the symbol, or any candidate locations for a
1568 trampoline, are within range of the branch. For this reason, the
1569 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1570 relocation in modules at all, and it makes little sense to add
1573 The symptom is that the kernel fails with an "unsupported
1574 relocation" error when loading some modules.
1576 Until fixed tools are available, passing
1577 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1578 code which hits this problem, at the cost of a bit of extra runtime
1579 stack usage in some cases.
1581 The problem is described in more detail at:
1582 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1584 Only Thumb-2 kernels are affected.
1586 Unless you are sure your tools don't have this problem, say Y.
1588 config ARM_ASM_UNIFIED
1592 bool "Use the ARM EABI to compile the kernel"
1594 This option allows for the kernel to be compiled using the latest
1595 ARM ABI (aka EABI). This is only useful if you are using a user
1596 space environment that is also compiled with EABI.
1598 Since there are major incompatibilities between the legacy ABI and
1599 EABI, especially with regard to structure member alignment, this
1600 option also changes the kernel syscall calling convention to
1601 disambiguate both ABIs and allow for backward compatibility support
1602 (selected with CONFIG_OABI_COMPAT).
1604 To use this you need GCC version 4.0.0 or later.
1607 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1608 depends on AEABI && !THUMB2_KERNEL
1610 This option preserves the old syscall interface along with the
1611 new (ARM EABI) one. It also provides a compatibility layer to
1612 intercept syscalls that have structure arguments which layout
1613 in memory differs between the legacy ABI and the new ARM EABI
1614 (only for non "thumb" binaries). This option adds a tiny
1615 overhead to all syscalls and produces a slightly larger kernel.
1617 The seccomp filter system will not be available when this is
1618 selected, since there is no way yet to sensibly distinguish
1619 between calling conventions during filtering.
1621 If you know you'll be using only pure EABI user space then you
1622 can say N here. If this option is not selected and you attempt
1623 to execute a legacy ABI binary then the result will be
1624 UNPREDICTABLE (in fact it can be predicted that it won't work
1625 at all). If in doubt say N.
1627 config ARCH_HAS_HOLES_MEMORYMODEL
1630 config ARCH_SPARSEMEM_ENABLE
1633 config ARCH_SPARSEMEM_DEFAULT
1634 def_bool ARCH_SPARSEMEM_ENABLE
1636 config ARCH_SELECT_MEMORY_MODEL
1637 def_bool ARCH_SPARSEMEM_ENABLE
1639 config HAVE_ARCH_PFN_VALID
1640 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1643 bool "High Memory Support"
1646 The address space of ARM processors is only 4 Gigabytes large
1647 and it has to accommodate user address space, kernel address
1648 space as well as some memory mapped IO. That means that, if you
1649 have a large amount of physical memory and/or IO, not all of the
1650 memory can be "permanently mapped" by the kernel. The physical
1651 memory that is not permanently mapped is called "high memory".
1653 Depending on the selected kernel/user memory split, minimum
1654 vmalloc space and actual amount of RAM, you may not need this
1655 option which should result in a slightly faster kernel.
1660 bool "Allocate 2nd-level pagetables from highmem"
1663 config HW_PERF_EVENTS
1664 bool "Enable hardware performance counter support for perf events"
1665 depends on PERF_EVENTS
1668 Enable hardware performance counter support for perf events. If
1669 disabled, perf events will use software events only.
1671 config SYS_SUPPORTS_HUGETLBFS
1675 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1679 config ARCH_WANT_GENERAL_HUGETLB
1684 config FORCE_MAX_ZONEORDER
1685 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1686 range 11 64 if ARCH_SHMOBILE_LEGACY
1687 default "12" if SOC_AM33XX
1688 default "9" if SA1111 || ARCH_EFM32
1691 The kernel memory allocator divides physically contiguous memory
1692 blocks into "zones", where each zone is a power of two number of
1693 pages. This option selects the largest power of two that the kernel
1694 keeps in the memory allocator. If you need to allocate very large
1695 blocks of physically contiguous memory, then you may need to
1696 increase this value.
1698 This config option is actually maximum order plus one. For example,
1699 a value of 11 means that the largest free memory block is 2^10 pages.
1701 config ALIGNMENT_TRAP
1703 depends on CPU_CP15_MMU
1704 default y if !ARCH_EBSA110
1705 select HAVE_PROC_CPU if PROC_FS
1707 ARM processors cannot fetch/store information which is not
1708 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1709 address divisible by 4. On 32-bit ARM processors, these non-aligned
1710 fetch/store instructions will be emulated in software if you say
1711 here, which has a severe performance impact. This is necessary for
1712 correct operation of some network protocols. With an IP-only
1713 configuration it is safe to say N, otherwise say Y.
1715 config UACCESS_WITH_MEMCPY
1716 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1718 default y if CPU_FEROCEON
1720 Implement faster copy_to_user and clear_user methods for CPU
1721 cores where a 8-word STM instruction give significantly higher
1722 memory write throughput than a sequence of individual 32bit stores.
1724 A possible side effect is a slight increase in scheduling latency
1725 between threads sharing the same address space if they invoke
1726 such copy operations with large buffers.
1728 However, if the CPU data cache is using a write-allocate mode,
1729 this option is unlikely to provide any performance gain.
1733 prompt "Enable seccomp to safely compute untrusted bytecode"
1735 This kernel feature is useful for number crunching applications
1736 that may need to compute untrusted bytecode during their
1737 execution. By using pipes or other transports made available to
1738 the process as file descriptors supporting the read/write
1739 syscalls, it's possible to isolate those applications in
1740 their own address space using seccomp. Once seccomp is
1741 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1742 and the task is only allowed to execute a few safe syscalls
1743 defined by each seccomp mode.
1756 bool "Xen guest support on ARM (EXPERIMENTAL)"
1757 depends on ARM && AEABI && OF
1758 depends on CPU_V7 && !CPU_V6
1759 depends on !GENERIC_ATOMIC64
1761 select ARCH_DMA_ADDR_T_64BIT
1765 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1772 bool "Flattened Device Tree support"
1775 select OF_EARLY_FLATTREE
1776 select OF_RESERVED_MEM
1778 Include support for flattened device tree machine descriptions.
1781 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1784 This is the traditional way of passing data to the kernel at boot
1785 time. If you are solely relying on the flattened device tree (or
1786 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1787 to remove ATAGS support from your kernel binary. If unsure,
1790 config DEPRECATED_PARAM_STRUCT
1791 bool "Provide old way to pass kernel parameters"
1794 This was deprecated in 2001 and announced to live on for 5 years.
1795 Some old boot loaders still use this way.
1797 # Compressed boot loader in ROM. Yes, we really want to ask about
1798 # TEXT and BSS so we preserve their values in the config files.
1799 config ZBOOT_ROM_TEXT
1800 hex "Compressed ROM boot loader base address"
1803 The physical address at which the ROM-able zImage is to be
1804 placed in the target. Platforms which normally make use of
1805 ROM-able zImage formats normally set this to a suitable
1806 value in their defconfig file.
1808 If ZBOOT_ROM is not enabled, this has no effect.
1810 config ZBOOT_ROM_BSS
1811 hex "Compressed ROM boot loader BSS address"
1814 The base address of an area of read/write memory in the target
1815 for the ROM-able zImage which must be available while the
1816 decompressor is running. It must be large enough to hold the
1817 entire decompressed kernel plus an additional 128 KiB.
1818 Platforms which normally make use of ROM-able zImage formats
1819 normally set this to a suitable value in their defconfig file.
1821 If ZBOOT_ROM is not enabled, this has no effect.
1824 bool "Compressed boot loader in ROM/flash"
1825 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1826 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1828 Say Y here if you intend to execute your compressed kernel image
1829 (zImage) directly from ROM or flash. If unsure, say N.
1832 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1833 depends on ZBOOT_ROM && ARCH_SH7372
1834 default ZBOOT_ROM_NONE
1836 Include experimental SD/MMC loading code in the ROM-able zImage.
1837 With this enabled it is possible to write the ROM-able zImage
1838 kernel image to an MMC or SD card and boot the kernel straight
1839 from the reset vector. At reset the processor Mask ROM will load
1840 the first part of the ROM-able zImage which in turn loads the
1841 rest the kernel image to RAM.
1843 config ZBOOT_ROM_NONE
1844 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1846 Do not load image from SD or MMC
1848 config ZBOOT_ROM_MMCIF
1849 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1851 Load image from MMCIF hardware block.
1853 config ZBOOT_ROM_SH_MOBILE_SDHI
1854 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1856 Load image from SDHI hardware block
1860 config ARM_APPENDED_DTB
1861 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1864 With this option, the boot code will look for a device tree binary
1865 (DTB) appended to zImage
1866 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1868 This is meant as a backward compatibility convenience for those
1869 systems with a bootloader that can't be upgraded to accommodate
1870 the documented boot protocol using a device tree.
1872 Beware that there is very little in terms of protection against
1873 this option being confused by leftover garbage in memory that might
1874 look like a DTB header after a reboot if no actual DTB is appended
1875 to zImage. Do not leave this option active in a production kernel
1876 if you don't intend to always append a DTB. Proper passing of the
1877 location into r2 of a bootloader provided DTB is always preferable
1880 config ARM_ATAG_DTB_COMPAT
1881 bool "Supplement the appended DTB with traditional ATAG information"
1882 depends on ARM_APPENDED_DTB
1884 Some old bootloaders can't be updated to a DTB capable one, yet
1885 they provide ATAGs with memory configuration, the ramdisk address,
1886 the kernel cmdline string, etc. Such information is dynamically
1887 provided by the bootloader and can't always be stored in a static
1888 DTB. To allow a device tree enabled kernel to be used with such
1889 bootloaders, this option allows zImage to extract the information
1890 from the ATAG list and store it at run time into the appended DTB.
1893 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1894 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1896 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1897 bool "Use bootloader kernel arguments if available"
1899 Uses the command-line options passed by the boot loader instead of
1900 the device tree bootargs property. If the boot loader doesn't provide
1901 any, the device tree bootargs property will be used.
1903 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1904 bool "Extend with bootloader kernel arguments"
1906 The command-line arguments provided by the boot loader will be
1907 appended to the the device tree bootargs property.
1912 string "Default kernel command string"
1915 On some architectures (EBSA110 and CATS), there is currently no way
1916 for the boot loader to pass arguments to the kernel. For these
1917 architectures, you should supply some command-line options at build
1918 time by entering them here. As a minimum, you should specify the
1919 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1922 prompt "Kernel command line type" if CMDLINE != ""
1923 default CMDLINE_FROM_BOOTLOADER
1926 config CMDLINE_FROM_BOOTLOADER
1927 bool "Use bootloader kernel arguments if available"
1929 Uses the command-line options passed by the boot loader. If
1930 the boot loader doesn't provide any, the default kernel command
1931 string provided in CMDLINE will be used.
1933 config CMDLINE_EXTEND
1934 bool "Extend bootloader kernel arguments"
1936 The command-line arguments provided by the boot loader will be
1937 appended to the default kernel command string.
1939 config CMDLINE_FORCE
1940 bool "Always use the default kernel command string"
1942 Always use the default kernel command string, even if the boot
1943 loader passes other arguments to the kernel.
1944 This is useful if you cannot or don't want to change the
1945 command-line options your boot loader passes to the kernel.
1949 bool "Kernel Execute-In-Place from ROM"
1950 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1952 Execute-In-Place allows the kernel to run from non-volatile storage
1953 directly addressable by the CPU, such as NOR flash. This saves RAM
1954 space since the text section of the kernel is not loaded from flash
1955 to RAM. Read-write sections, such as the data section and stack,
1956 are still copied to RAM. The XIP kernel is not compressed since
1957 it has to run directly from flash, so it will take more space to
1958 store it. The flash address used to link the kernel object files,
1959 and for storing it, is configuration dependent. Therefore, if you
1960 say Y here, you must know the proper physical address where to
1961 store the kernel image depending on your own flash memory usage.
1963 Also note that the make target becomes "make xipImage" rather than
1964 "make zImage" or "make Image". The final kernel binary to put in
1965 ROM memory will be arch/arm/boot/xipImage.
1969 config XIP_PHYS_ADDR
1970 hex "XIP Kernel Physical Location"
1971 depends on XIP_KERNEL
1972 default "0x00080000"
1974 This is the physical address in your flash memory the kernel will
1975 be linked for and stored to. This address is dependent on your
1979 bool "Kexec system call (EXPERIMENTAL)"
1980 depends on (!SMP || PM_SLEEP_SMP)
1982 kexec is a system call that implements the ability to shutdown your
1983 current kernel, and to start another kernel. It is like a reboot
1984 but it is independent of the system firmware. And like a reboot
1985 you can start any kernel with it, not just Linux.
1987 It is an ongoing process to be certain the hardware in a machine
1988 is properly shutdown, so do not be surprised if this code does not
1989 initially work for you.
1992 bool "Export atags in procfs"
1993 depends on ATAGS && KEXEC
1996 Should the atags used to boot the kernel be exported in an "atags"
1997 file in procfs. Useful with kexec.
2000 bool "Build kdump crash kernel (EXPERIMENTAL)"
2002 Generate crash dump after being started by kexec. This should
2003 be normally only set in special crash dump kernels which are
2004 loaded in the main kernel with kexec-tools into a specially
2005 reserved region and then later executed after a crash by
2006 kdump/kexec. The crash dump kernel must be compiled to a
2007 memory address not used by the main kernel
2009 For more details see Documentation/kdump/kdump.txt
2011 config AUTO_ZRELADDR
2012 bool "Auto calculation of the decompressed kernel image address"
2014 ZRELADDR is the physical address where the decompressed kernel
2015 image will be placed. If AUTO_ZRELADDR is selected, the address
2016 will be determined at run-time by masking the current IP with
2017 0xf8000000. This assumes the zImage being placed in the first 128MB
2018 from start of memory.
2022 menu "CPU Power Management"
2024 source "drivers/cpufreq/Kconfig"
2026 source "drivers/cpuidle/Kconfig"
2030 menu "Floating point emulation"
2032 comment "At least one emulation must be selected"
2035 bool "NWFPE math emulation"
2036 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2038 Say Y to include the NWFPE floating point emulator in the kernel.
2039 This is necessary to run most binaries. Linux does not currently
2040 support floating point hardware so you need to say Y here even if
2041 your machine has an FPA or floating point co-processor podule.
2043 You may say N here if you are going to load the Acorn FPEmulator
2044 early in the bootup.
2047 bool "Support extended precision"
2048 depends on FPE_NWFPE
2050 Say Y to include 80-bit support in the kernel floating-point
2051 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2052 Note that gcc does not generate 80-bit operations by default,
2053 so in most cases this option only enlarges the size of the
2054 floating point emulator without any good reason.
2056 You almost surely want to say N here.
2059 bool "FastFPE math emulation (EXPERIMENTAL)"
2060 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2062 Say Y here to include the FAST floating point emulator in the kernel.
2063 This is an experimental much faster emulator which now also has full
2064 precision for the mantissa. It does not support any exceptions.
2065 It is very simple, and approximately 3-6 times faster than NWFPE.
2067 It should be sufficient for most programs. It may be not suitable
2068 for scientific calculations, but you have to check this for yourself.
2069 If you do not feel you need a faster FP emulation you should better
2073 bool "VFP-format floating point maths"
2074 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2076 Say Y to include VFP support code in the kernel. This is needed
2077 if your hardware includes a VFP unit.
2079 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2080 release notes and additional status information.
2082 Say N if your target does not have VFP hardware.
2090 bool "Advanced SIMD (NEON) Extension support"
2091 depends on VFPv3 && CPU_V7
2093 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2096 config KERNEL_MODE_NEON
2097 bool "Support for NEON in kernel mode"
2098 depends on NEON && AEABI
2100 Say Y to include support for NEON in kernel mode.
2104 menu "Userspace binary formats"
2106 source "fs/Kconfig.binfmt"
2109 tristate "RISC OS personality"
2112 Say Y here to include the kernel code necessary if you want to run
2113 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2114 experimental; if this sounds frightening, say N and sleep in peace.
2115 You can also say M here to compile this support as a module (which
2116 will be called arthur).
2120 menu "Power management options"
2122 source "kernel/power/Kconfig"
2124 config ARCH_SUSPEND_POSSIBLE
2125 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2126 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2129 config ARM_CPU_SUSPEND
2132 config ARCH_HIBERNATION_POSSIBLE
2135 default y if ARCH_SUSPEND_POSSIBLE
2139 source "net/Kconfig"
2141 source "drivers/Kconfig"
2145 source "arch/arm/Kconfig.debug"
2147 source "security/Kconfig"
2149 source "crypto/Kconfig"
2151 source "lib/Kconfig"
2153 source "arch/arm/kvm/Kconfig"