5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
68 select GENERIC_ALLOCATOR
79 The Extended Industry Standard Architecture (EISA) bus was
80 developed as an open alternative to the IBM MicroChannel bus.
82 The EISA bus provided some of the features of the IBM MicroChannel
83 bus while maintaining backward compatibility with cards made for
84 the older ISA bus. The EISA bus saw limited use between 1988 and
85 1995 when it was made obsolete by the PCI bus.
87 Say Y here if you are building a kernel for an EISA-based machine.
97 MicroChannel Architecture is found in some IBM PS/2 machines and
98 laptops. It is a bus system similar to PCI or ISA. See
99 <file:Documentation/mca.txt> (and especially the web page given
100 there) before attempting to build an MCA bus kernel.
102 config STACKTRACE_SUPPORT
106 config HAVE_LATENCYTOP_SUPPORT
111 config LOCKDEP_SUPPORT
115 config TRACE_IRQFLAGS_SUPPORT
119 config HARDIRQS_SW_RESEND
123 config GENERIC_IRQ_PROBE
127 config GENERIC_LOCKBREAK
130 depends on SMP && PREEMPT
132 config RWSEM_GENERIC_SPINLOCK
136 config RWSEM_XCHGADD_ALGORITHM
139 config ARCH_HAS_ILOG2_U32
142 config ARCH_HAS_ILOG2_U64
145 config ARCH_HAS_CPUFREQ
148 Internal node to signify that the ARCH has CPUFREQ support
149 and that the relevant menu configurations are displayed for
152 config ARCH_HAS_CPU_IDLE_WAIT
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config GENERIC_ISA_DMA
181 config ARM_L1_CACHE_SHIFT_6
184 Setting ARM L1 cache line size to 64 Bytes.
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 source "init/Kconfig"
196 source "kernel/Kconfig.freezer"
201 bool "MMU-based Paged Memory Management Support"
204 Select if you want MMU-based virtualised addressing space
205 support by paged memory management. If unsure, say 'Y'.
208 # The "ARM system type" choice list is ordered alphabetically by option
209 # text. Please add new entries in the option alphabetic order.
212 prompt "ARM system type"
213 default ARCH_VERSATILE
215 config ARCH_INTEGRATOR
216 bool "ARM Ltd. Integrator family"
218 select ARCH_HAS_CPUFREQ
221 select GENERIC_CLOCKEVENTS
222 select PLAT_VERSATILE
224 Support for ARM's Integrator platform.
227 bool "ARM Ltd. RealView family"
230 select HAVE_SCHED_CLOCK
232 select GENERIC_CLOCKEVENTS
233 select ARCH_WANT_OPTIONAL_GPIOLIB
234 select PLAT_VERSATILE
235 select ARM_TIMER_SP804
236 select GPIO_PL061 if GPIOLIB
238 This enables support for ARM Ltd RealView boards.
240 config ARCH_VERSATILE
241 bool "ARM Ltd. Versatile family"
245 select HAVE_SCHED_CLOCK
247 select GENERIC_CLOCKEVENTS
248 select ARCH_WANT_OPTIONAL_GPIOLIB
249 select PLAT_VERSATILE
250 select ARM_TIMER_SP804
252 This enables support for ARM Ltd Versatile board.
255 bool "ARM Ltd. Versatile Express family"
256 select ARCH_WANT_OPTIONAL_GPIOLIB
258 select ARM_TIMER_SP804
260 select GENERIC_CLOCKEVENTS
262 select HAVE_SCHED_CLOCK
264 select PLAT_VERSATILE
266 This enables support for the ARM Ltd Versatile Express boards.
270 select ARCH_REQUIRE_GPIOLIB
273 This enables support for systems based on the Atmel AT91RM9200,
274 AT91SAM9 and AT91CAP9 processors.
277 bool "Broadcom BCMRING"
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
285 Support for Broadcom's BCMRing platform.
288 bool "Cirrus Logic CLPS711x/EP721x-based"
290 select ARCH_USES_GETTIMEOFFSET
292 Support for Cirrus Logic 711x/721x based boards.
295 bool "Cavium Networks CNS3XXX family"
297 select GENERIC_CLOCKEVENTS
299 select MIGHT_HAVE_PCI
300 select PCI_DOMAINS if PCI
302 Support for Cavium Networks CNS3XXX platform.
305 bool "Cortina Systems Gemini"
307 select ARCH_REQUIRE_GPIOLIB
308 select ARCH_USES_GETTIMEOFFSET
310 Support for the Cortina Systems Gemini family SoCs
317 select ARCH_USES_GETTIMEOFFSET
319 This is an evaluation board for the StrongARM processor available
320 from Digital. It has limited hardware on-board, including an
321 Ethernet interface, two PCMCIA sockets, two serial ports and a
330 select ARCH_REQUIRE_GPIOLIB
331 select ARCH_HAS_HOLES_MEMORYMODEL
332 select ARCH_USES_GETTIMEOFFSET
334 This enables support for the Cirrus EP93xx series of CPUs.
336 config ARCH_FOOTBRIDGE
340 select ARCH_USES_GETTIMEOFFSET
342 Support for systems based on the DC21285 companion chip
343 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
346 bool "Freescale MXC/iMX-based"
347 select GENERIC_CLOCKEVENTS
348 select ARCH_REQUIRE_GPIOLIB
351 Support for Freescale MXC/iMX-based family of processors
354 bool "Freescale MXS-based"
355 select GENERIC_CLOCKEVENTS
356 select ARCH_REQUIRE_GPIOLIB
359 Support for Freescale MXS-based family of processors
362 bool "Freescale STMP3xxx"
365 select ARCH_REQUIRE_GPIOLIB
366 select GENERIC_CLOCKEVENTS
367 select USB_ARCH_HAS_EHCI
369 Support for systems based on the Freescale 3xxx CPUs.
372 bool "Hilscher NetX based"
375 select GENERIC_CLOCKEVENTS
377 This enables support for systems based on the Hilscher NetX Soc
380 bool "Hynix HMS720x-based"
383 select ARCH_USES_GETTIMEOFFSET
385 This enables support for systems based on the Hynix HMS720x
393 select ARCH_SUPPORTS_MSI
396 Support for Intel's IOP13XX (XScale) family of processors.
404 select ARCH_REQUIRE_GPIOLIB
406 Support for Intel's 80219 and IOP32X (XScale) family of
415 select ARCH_REQUIRE_GPIOLIB
417 Support for Intel's IOP33X (XScale) family of processors.
424 select ARCH_USES_GETTIMEOFFSET
426 Support for Intel's IXP23xx (XScale) family of processors.
429 bool "IXP2400/2800-based"
433 select ARCH_USES_GETTIMEOFFSET
435 Support for Intel's IXP2400/2800 (XScale) family of processors.
442 select GENERIC_CLOCKEVENTS
443 select HAVE_SCHED_CLOCK
444 select MIGHT_HAVE_PCI
445 select DMABOUNCE if PCI
447 Support for Intel's IXP4XX (XScale) family of processors.
452 select ARCH_REQUIRE_GPIOLIB
453 select GENERIC_CLOCKEVENTS
456 Support for the Marvell Dove SoC 88AP510
459 bool "Marvell Kirkwood"
462 select ARCH_REQUIRE_GPIOLIB
463 select GENERIC_CLOCKEVENTS
466 Support for the following Marvell Kirkwood series SoCs:
467 88F6180, 88F6192 and 88F6281.
470 bool "Marvell Loki (88RC8480)"
472 select GENERIC_CLOCKEVENTS
475 Support for the Marvell Loki (88RC8480) SoC.
480 select ARCH_REQUIRE_GPIOLIB
483 select USB_ARCH_HAS_OHCI
486 select GENERIC_CLOCKEVENTS
488 Support for the NXP LPC32XX family of processors
491 bool "Marvell MV78xx0"
494 select ARCH_REQUIRE_GPIOLIB
495 select GENERIC_CLOCKEVENTS
498 Support for the following Marvell MV78xx0 series SoCs:
506 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
510 Support for the following Marvell Orion 5x series SoCs:
511 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
512 Orion-2 (5281), Orion-1-90 (6183).
515 bool "Marvell PXA168/910/MMP2"
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
520 select HAVE_SCHED_CLOCK
525 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
528 bool "Micrel/Kendin KS8695"
530 select ARCH_REQUIRE_GPIOLIB
531 select ARCH_USES_GETTIMEOFFSET
533 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
534 System-on-Chip devices.
537 bool "NetSilicon NS9xxx"
540 select GENERIC_CLOCKEVENTS
543 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
546 <http://www.digi.com/products/microprocessors/index.jsp>
549 bool "Nuvoton W90X900 CPU"
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
555 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
556 At present, the w90x900 has been renamed nuc900, regarding
557 the ARM series product line, you can login the following
558 link address to know more.
560 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
561 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
564 bool "Nuvoton NUC93X CPU"
568 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
569 low-power and high performance MPEG-4/JPEG multimedia controller chip.
575 select GENERIC_CLOCKEVENTS
578 select HAVE_SCHED_CLOCK
579 select ARCH_HAS_BARRIERS if CACHE_L2X0
580 select ARCH_HAS_CPUFREQ
582 This enables support for NVIDIA Tegra based systems (Tegra APX,
583 Tegra 6xx and Tegra 2 series).
586 bool "Philips Nexperia PNX4008 Mobile"
589 select ARCH_USES_GETTIMEOFFSET
591 This enables support for Philips PNX4008 mobile platform.
594 bool "PXA2xx/PXA3xx-based"
597 select ARCH_HAS_CPUFREQ
599 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
601 select HAVE_SCHED_CLOCK
606 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
611 select GENERIC_CLOCKEVENTS
612 select ARCH_REQUIRE_GPIOLIB
614 Support for Qualcomm MSM/QSD based systems. This runs on the
615 apps processor of the MSM/QSD and depends on a shared memory
616 interface to the modem processor which runs the baseband
617 stack and controls some vital subsystems
618 (clock and power control, etc).
621 bool "Renesas SH-Mobile / R-Mobile"
624 select GENERIC_CLOCKEVENTS
627 select MULTI_IRQ_HANDLER
629 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
636 select ARCH_MAY_HAVE_PC_FDC
637 select HAVE_PATA_PLATFORM
640 select ARCH_SPARSEMEM_ENABLE
641 select ARCH_USES_GETTIMEOFFSET
643 On the Acorn Risc-PC, Linux can support the internal IDE disk and
644 CD-ROM interface, serial and parallel port, and the floppy drive.
650 select ARCH_SPARSEMEM_ENABLE
652 select ARCH_HAS_CPUFREQ
654 select GENERIC_CLOCKEVENTS
656 select HAVE_SCHED_CLOCK
658 select ARCH_REQUIRE_GPIOLIB
660 Support for StrongARM 11x0 based boards.
663 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
665 select ARCH_HAS_CPUFREQ
667 select ARCH_USES_GETTIMEOFFSET
668 select HAVE_S3C2410_I2C if I2C
670 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
671 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
672 the Samsung SMDK2410 development board (and derivatives).
674 Note, the S3C2416 and the S3C2450 are so close that they even share
675 the same SoC ID code. This means that there is no seperate machine
676 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
679 bool "Samsung S3C64XX"
685 select ARCH_USES_GETTIMEOFFSET
686 select ARCH_HAS_CPUFREQ
687 select ARCH_REQUIRE_GPIOLIB
688 select SAMSUNG_CLKSRC
689 select SAMSUNG_IRQ_VIC_TIMER
690 select SAMSUNG_IRQ_UART
691 select S3C_GPIO_TRACK
692 select S3C_GPIO_PULL_UPDOWN
693 select S3C_GPIO_CFG_S3C24XX
694 select S3C_GPIO_CFG_S3C64XX
696 select USB_ARCH_HAS_OHCI
697 select SAMSUNG_GPIOLIB_4BIT
698 select HAVE_S3C2410_I2C if I2C
699 select HAVE_S3C2410_WATCHDOG if WATCHDOG
701 Samsung S3C64XX series based systems
704 bool "Samsung S5P6440 S5P6450"
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
709 select ARCH_USES_GETTIMEOFFSET
710 select HAVE_S3C2410_I2C if I2C
711 select HAVE_S3C_RTC if RTC_CLASS
713 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
717 bool "Samsung S5P6442"
721 select ARCH_USES_GETTIMEOFFSET
722 select HAVE_S3C2410_WATCHDOG if WATCHDOG
724 Samsung S5P6442 CPU based systems
727 bool "Samsung S5PC100"
731 select ARM_L1_CACHE_SHIFT_6
732 select ARCH_USES_GETTIMEOFFSET
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C_RTC if RTC_CLASS
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 Samsung S5PC100 series based systems
740 bool "Samsung S5PV210/S5PC110"
742 select ARCH_SPARSEMEM_ENABLE
745 select ARM_L1_CACHE_SHIFT_6
746 select ARCH_HAS_CPUFREQ
747 select ARCH_USES_GETTIMEOFFSET
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C_RTC if RTC_CLASS
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
752 Samsung S5PV210/S5PC110 series based systems
755 bool "Samsung S5PV310/S5PC210"
757 select ARCH_SPARSEMEM_ENABLE
760 select ARCH_HAS_CPUFREQ
761 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C_RTC if RTC_CLASS
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 Samsung S5PV310 series based systems
775 select ARCH_USES_GETTIMEOFFSET
777 Support for the StrongARM based Digital DNARD machine, also known
778 as "Shark" (<http://www.shark-linux.de/shark.html>).
781 bool "Telechips TCC ARM926-based systems"
785 select GENERIC_CLOCKEVENTS
787 Support for Telechips TCC ARM926-based systems.
790 bool "ST-Ericsson U300 Series"
793 select HAVE_SCHED_CLOCK
797 select GENERIC_CLOCKEVENTS
801 Support for ST-Ericsson U300 series mobile platforms.
804 bool "ST-Ericsson U8500 Series"
807 select GENERIC_CLOCKEVENTS
809 select ARCH_REQUIRE_GPIOLIB
810 select ARCH_HAS_CPUFREQ
812 Support for ST-Ericsson's Ux500 architecture
815 bool "STMicroelectronics Nomadik"
820 select GENERIC_CLOCKEVENTS
821 select ARCH_REQUIRE_GPIOLIB
823 Support for the Nomadik platform by ST-Ericsson
827 select GENERIC_CLOCKEVENTS
828 select ARCH_REQUIRE_GPIOLIB
832 select GENERIC_ALLOCATOR
833 select ARCH_HAS_HOLES_MEMORYMODEL
835 Support for TI's DaVinci platform.
840 select ARCH_REQUIRE_GPIOLIB
841 select ARCH_HAS_CPUFREQ
842 select GENERIC_CLOCKEVENTS
843 select HAVE_SCHED_CLOCK
844 select ARCH_HAS_HOLES_MEMORYMODEL
846 Support for TI's OMAP platform (OMAP1/2/3/4).
851 select ARCH_REQUIRE_GPIOLIB
853 select GENERIC_CLOCKEVENTS
856 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
861 # This is sorted alphabetically by mach-* pathname. However, plat-*
862 # Kconfigs may be included either alphabetically (according to the
863 # plat- suffix) or along side the corresponding mach-* source.
865 source "arch/arm/mach-at91/Kconfig"
867 source "arch/arm/mach-bcmring/Kconfig"
869 source "arch/arm/mach-clps711x/Kconfig"
871 source "arch/arm/mach-cns3xxx/Kconfig"
873 source "arch/arm/mach-davinci/Kconfig"
875 source "arch/arm/mach-dove/Kconfig"
877 source "arch/arm/mach-ep93xx/Kconfig"
879 source "arch/arm/mach-footbridge/Kconfig"
881 source "arch/arm/mach-gemini/Kconfig"
883 source "arch/arm/mach-h720x/Kconfig"
885 source "arch/arm/mach-integrator/Kconfig"
887 source "arch/arm/mach-iop32x/Kconfig"
889 source "arch/arm/mach-iop33x/Kconfig"
891 source "arch/arm/mach-iop13xx/Kconfig"
893 source "arch/arm/mach-ixp4xx/Kconfig"
895 source "arch/arm/mach-ixp2000/Kconfig"
897 source "arch/arm/mach-ixp23xx/Kconfig"
899 source "arch/arm/mach-kirkwood/Kconfig"
901 source "arch/arm/mach-ks8695/Kconfig"
903 source "arch/arm/mach-loki/Kconfig"
905 source "arch/arm/mach-lpc32xx/Kconfig"
907 source "arch/arm/mach-msm/Kconfig"
909 source "arch/arm/mach-mv78xx0/Kconfig"
911 source "arch/arm/plat-mxc/Kconfig"
913 source "arch/arm/mach-mxs/Kconfig"
915 source "arch/arm/mach-netx/Kconfig"
917 source "arch/arm/mach-nomadik/Kconfig"
918 source "arch/arm/plat-nomadik/Kconfig"
920 source "arch/arm/mach-ns9xxx/Kconfig"
922 source "arch/arm/mach-nuc93x/Kconfig"
924 source "arch/arm/plat-omap/Kconfig"
926 source "arch/arm/mach-omap1/Kconfig"
928 source "arch/arm/mach-omap2/Kconfig"
930 source "arch/arm/mach-orion5x/Kconfig"
932 source "arch/arm/mach-pxa/Kconfig"
933 source "arch/arm/plat-pxa/Kconfig"
935 source "arch/arm/mach-mmp/Kconfig"
937 source "arch/arm/mach-realview/Kconfig"
939 source "arch/arm/mach-sa1100/Kconfig"
941 source "arch/arm/plat-samsung/Kconfig"
942 source "arch/arm/plat-s3c24xx/Kconfig"
943 source "arch/arm/plat-s5p/Kconfig"
945 source "arch/arm/plat-spear/Kconfig"
947 source "arch/arm/plat-tcc/Kconfig"
950 source "arch/arm/mach-s3c2400/Kconfig"
951 source "arch/arm/mach-s3c2410/Kconfig"
952 source "arch/arm/mach-s3c2412/Kconfig"
953 source "arch/arm/mach-s3c2416/Kconfig"
954 source "arch/arm/mach-s3c2440/Kconfig"
955 source "arch/arm/mach-s3c2443/Kconfig"
959 source "arch/arm/mach-s3c64xx/Kconfig"
962 source "arch/arm/mach-s5p64x0/Kconfig"
964 source "arch/arm/mach-s5p6442/Kconfig"
966 source "arch/arm/mach-s5pc100/Kconfig"
968 source "arch/arm/mach-s5pv210/Kconfig"
970 source "arch/arm/mach-s5pv310/Kconfig"
972 source "arch/arm/mach-shmobile/Kconfig"
974 source "arch/arm/plat-stmp3xxx/Kconfig"
976 source "arch/arm/mach-tegra/Kconfig"
978 source "arch/arm/mach-u300/Kconfig"
980 source "arch/arm/mach-ux500/Kconfig"
982 source "arch/arm/mach-versatile/Kconfig"
984 source "arch/arm/mach-vexpress/Kconfig"
986 source "arch/arm/mach-w90x900/Kconfig"
988 # Definitions to make life easier
994 select GENERIC_CLOCKEVENTS
995 select HAVE_SCHED_CLOCK
999 select HAVE_SCHED_CLOCK
1004 config PLAT_VERSATILE
1007 config ARM_TIMER_SP804
1010 source arch/arm/mm/Kconfig
1013 bool "Enable iWMMXt support"
1014 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1015 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1017 Enable support for iWMMXt context switching at run time if
1018 running on a CPU that supports it.
1020 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1023 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1027 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1028 (!ARCH_OMAP3 || OMAP3_EMU)
1032 config MULTI_IRQ_HANDLER
1035 Allow each machine to specify it's own IRQ handler at run time.
1038 source "arch/arm/Kconfig-nommu"
1041 config ARM_ERRATA_411920
1042 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1045 Invalidation of the Instruction Cache operation can
1046 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1047 It does not affect the MPCore. This option enables the ARM Ltd.
1048 recommended workaround.
1050 config ARM_ERRATA_430973
1051 bool "ARM errata: Stale prediction on replaced interworking branch"
1054 This option enables the workaround for the 430973 Cortex-A8
1055 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1056 interworking branch is replaced with another code sequence at the
1057 same virtual address, whether due to self-modifying code or virtual
1058 to physical address re-mapping, Cortex-A8 does not recover from the
1059 stale interworking branch prediction. This results in Cortex-A8
1060 executing the new code sequence in the incorrect ARM or Thumb state.
1061 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1062 and also flushes the branch target cache at every context switch.
1063 Note that setting specific bits in the ACTLR register may not be
1064 available in non-secure mode.
1066 config ARM_ERRATA_458693
1067 bool "ARM errata: Processor deadlock when a false hazard is created"
1070 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1071 erratum. For very specific sequences of memory operations, it is
1072 possible for a hazard condition intended for a cache line to instead
1073 be incorrectly associated with a different cache line. This false
1074 hazard might then cause a processor deadlock. The workaround enables
1075 the L1 caching of the NEON accesses and disables the PLD instruction
1076 in the ACTLR register. Note that setting specific bits in the ACTLR
1077 register may not be available in non-secure mode.
1079 config ARM_ERRATA_460075
1080 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1083 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1084 erratum. Any asynchronous access to the L2 cache may encounter a
1085 situation in which recent store transactions to the L2 cache are lost
1086 and overwritten with stale memory contents from external memory. The
1087 workaround disables the write-allocate mode for the L2 cache via the
1088 ACTLR register. Note that setting specific bits in the ACTLR register
1089 may not be available in non-secure mode.
1091 config ARM_ERRATA_742230
1092 bool "ARM errata: DMB operation may be faulty"
1093 depends on CPU_V7 && SMP
1095 This option enables the workaround for the 742230 Cortex-A9
1096 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1097 between two write operations may not ensure the correct visibility
1098 ordering of the two writes. This workaround sets a specific bit in
1099 the diagnostic register of the Cortex-A9 which causes the DMB
1100 instruction to behave as a DSB, ensuring the correct behaviour of
1103 config ARM_ERRATA_742231
1104 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1105 depends on CPU_V7 && SMP
1107 This option enables the workaround for the 742231 Cortex-A9
1108 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1109 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1110 accessing some data located in the same cache line, may get corrupted
1111 data due to bad handling of the address hazard when the line gets
1112 replaced from one of the CPUs at the same time as another CPU is
1113 accessing it. This workaround sets specific bits in the diagnostic
1114 register of the Cortex-A9 which reduces the linefill issuing
1115 capabilities of the processor.
1117 config PL310_ERRATA_588369
1118 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1119 depends on CACHE_L2X0 && ARCH_OMAP4
1121 The PL310 L2 cache controller implements three types of Clean &
1122 Invalidate maintenance operations: by Physical Address
1123 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1124 They are architecturally defined to behave as the execution of a
1125 clean operation followed immediately by an invalidate operation,
1126 both performing to the same memory location. This functionality
1127 is not correctly implemented in PL310 as clean lines are not
1128 invalidated as a result of these operations. Note that this errata
1129 uses Texas Instrument's secure monitor api.
1131 config ARM_ERRATA_720789
1132 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1133 depends on CPU_V7 && SMP
1135 This option enables the workaround for the 720789 Cortex-A9 (prior to
1136 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1137 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1138 As a consequence of this erratum, some TLB entries which should be
1139 invalidated are not, resulting in an incoherency in the system page
1140 tables. The workaround changes the TLB flushing routines to invalidate
1141 entries regardless of the ASID.
1143 config ARM_ERRATA_743622
1144 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1147 This option enables the workaround for the 743622 Cortex-A9
1148 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1149 optimisation in the Cortex-A9 Store Buffer may lead to data
1150 corruption. This workaround sets a specific bit in the diagnostic
1151 register of the Cortex-A9 which disables the Store Buffer
1152 optimisation, preventing the defect from occurring. This has no
1153 visible impact on the overall performance or power consumption of the
1158 source "arch/arm/common/Kconfig"
1168 Find out whether you have ISA slots on your motherboard. ISA is the
1169 name of a bus system, i.e. the way the CPU talks to the other stuff
1170 inside your box. Other bus systems are PCI, EISA, MicroChannel
1171 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1172 newer boards don't support it. If you have ISA, say Y, otherwise N.
1174 # Select ISA DMA controller support
1179 # Select ISA DMA interface
1184 bool "PCI support" if MIGHT_HAVE_PCI
1186 Find out whether you have a PCI motherboard. PCI is the name of a
1187 bus system, i.e. the way the CPU talks to the other stuff inside
1188 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1189 VESA. If you have PCI, say Y, otherwise N.
1195 config PCI_NANOENGINE
1196 bool "BSE nanoEngine PCI support"
1197 depends on SA1100_NANOENGINE
1199 Enable PCI on the BSE nanoEngine board.
1204 # Select the host bridge type
1205 config PCI_HOST_VIA82C505
1207 depends on PCI && ARCH_SHARK
1210 config PCI_HOST_ITE8152
1212 depends on PCI && MACH_ARMCORE
1216 source "drivers/pci/Kconfig"
1218 source "drivers/pcmcia/Kconfig"
1222 menu "Kernel Features"
1224 source "kernel/time/Kconfig"
1227 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1228 depends on EXPERIMENTAL
1229 depends on GENERIC_CLOCKEVENTS
1230 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1231 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1232 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1233 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1234 select USE_GENERIC_SMP_HELPERS
1235 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1237 This enables support for systems with more than one CPU. If you have
1238 a system with only one CPU, like most personal computers, say N. If
1239 you have a system with more than one CPU, say Y.
1241 If you say N here, the kernel will run on single and multiprocessor
1242 machines, but will use only one CPU of a multiprocessor machine. If
1243 you say Y here, the kernel will run on many, but not all, single
1244 processor machines. On a single processor machine, the kernel will
1245 run faster if you say N here.
1247 See also <file:Documentation/i386/IO-APIC.txt>,
1248 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1249 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1251 If you don't know what to do here, say N.
1254 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1255 depends on EXPERIMENTAL
1256 depends on SMP && !XIP_KERNEL
1259 SMP kernels contain instructions which fail on non-SMP processors.
1260 Enabling this option allows the kernel to modify itself to make
1261 these instructions safe. Disabling it allows about 1K of space
1264 If you don't know what to do here, say Y.
1270 This option enables support for the ARM system coherency unit
1277 This options enables support for the ARM timer and watchdog unit
1280 prompt "Memory split"
1283 Select the desired split between kernel and user memory.
1285 If you are not absolutely sure what you are doing, leave this
1289 bool "3G/1G user/kernel split"
1291 bool "2G/2G user/kernel split"
1293 bool "1G/3G user/kernel split"
1298 default 0x40000000 if VMSPLIT_1G
1299 default 0x80000000 if VMSPLIT_2G
1303 int "Maximum number of CPUs (2-32)"
1309 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1310 depends on SMP && HOTPLUG && EXPERIMENTAL
1311 depends on !ARCH_MSM
1313 Say Y here to experiment with turning CPUs off and on. CPUs
1314 can be controlled through /sys/devices/system/cpu.
1317 bool "Use local timer interrupts"
1320 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1322 Enable support for local timers on SMP platforms, rather then the
1323 legacy IPI broadcast method. Local timers allows the system
1324 accounting to be spread across the timer interval, preventing a
1325 "thundering herd" at every timer tick.
1327 source kernel/Kconfig.preempt
1331 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1332 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1333 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1334 default AT91_TIMER_HZ if ARCH_AT91
1335 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1338 config THUMB2_KERNEL
1339 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1340 depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
1342 select ARM_ASM_UNIFIED
1344 By enabling this option, the kernel will be compiled in
1345 Thumb-2 mode. A compiler/assembler that understand the unified
1346 ARM-Thumb syntax is needed.
1350 config ARM_ASM_UNIFIED
1354 bool "Use the ARM EABI to compile the kernel"
1356 This option allows for the kernel to be compiled using the latest
1357 ARM ABI (aka EABI). This is only useful if you are using a user
1358 space environment that is also compiled with EABI.
1360 Since there are major incompatibilities between the legacy ABI and
1361 EABI, especially with regard to structure member alignment, this
1362 option also changes the kernel syscall calling convention to
1363 disambiguate both ABIs and allow for backward compatibility support
1364 (selected with CONFIG_OABI_COMPAT).
1366 To use this you need GCC version 4.0.0 or later.
1369 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1370 depends on AEABI && EXPERIMENTAL
1373 This option preserves the old syscall interface along with the
1374 new (ARM EABI) one. It also provides a compatibility layer to
1375 intercept syscalls that have structure arguments which layout
1376 in memory differs between the legacy ABI and the new ARM EABI
1377 (only for non "thumb" binaries). This option adds a tiny
1378 overhead to all syscalls and produces a slightly larger kernel.
1379 If you know you'll be using only pure EABI user space then you
1380 can say N here. If this option is not selected and you attempt
1381 to execute a legacy ABI binary then the result will be
1382 UNPREDICTABLE (in fact it can be predicted that it won't work
1383 at all). If in doubt say Y.
1385 config ARCH_HAS_HOLES_MEMORYMODEL
1388 config ARCH_SPARSEMEM_ENABLE
1391 config ARCH_SPARSEMEM_DEFAULT
1392 def_bool ARCH_SPARSEMEM_ENABLE
1394 config ARCH_SELECT_MEMORY_MODEL
1395 def_bool ARCH_SPARSEMEM_ENABLE
1398 bool "High Memory Support (EXPERIMENTAL)"
1399 depends on MMU && EXPERIMENTAL
1401 The address space of ARM processors is only 4 Gigabytes large
1402 and it has to accommodate user address space, kernel address
1403 space as well as some memory mapped IO. That means that, if you
1404 have a large amount of physical memory and/or IO, not all of the
1405 memory can be "permanently mapped" by the kernel. The physical
1406 memory that is not permanently mapped is called "high memory".
1408 Depending on the selected kernel/user memory split, minimum
1409 vmalloc space and actual amount of RAM, you may not need this
1410 option which should result in a slightly faster kernel.
1415 bool "Allocate 2nd-level pagetables from highmem"
1417 depends on !OUTER_CACHE
1419 config HW_PERF_EVENTS
1420 bool "Enable hardware performance counter support for perf events"
1421 depends on PERF_EVENTS && CPU_HAS_PMU
1424 Enable hardware performance counter support for perf events. If
1425 disabled, perf events will use software events only.
1429 config FORCE_MAX_ZONEORDER
1430 int "Maximum zone order" if ARCH_SHMOBILE
1431 range 11 64 if ARCH_SHMOBILE
1432 default "9" if SA1111
1435 The kernel memory allocator divides physically contiguous memory
1436 blocks into "zones", where each zone is a power of two number of
1437 pages. This option selects the largest power of two that the kernel
1438 keeps in the memory allocator. If you need to allocate very large
1439 blocks of physically contiguous memory, then you may need to
1440 increase this value.
1442 This config option is actually maximum order plus one. For example,
1443 a value of 11 means that the largest free memory block is 2^10 pages.
1446 bool "Timer and CPU usage LEDs"
1447 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1448 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1449 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1450 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1451 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1452 ARCH_AT91 || ARCH_DAVINCI || \
1453 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1455 If you say Y here, the LEDs on your machine will be used
1456 to provide useful information about your current system status.
1458 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1459 be able to select which LEDs are active using the options below. If
1460 you are compiling a kernel for the EBSA-110 or the LART however, the
1461 red LED will simply flash regularly to indicate that the system is
1462 still functional. It is safe to say Y here if you have a CATS
1463 system, but the driver will do nothing.
1466 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1467 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1468 || MACH_OMAP_PERSEUS2
1470 depends on !GENERIC_CLOCKEVENTS
1471 default y if ARCH_EBSA110
1473 If you say Y here, one of the system LEDs (the green one on the
1474 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1475 will flash regularly to indicate that the system is still
1476 operational. This is mainly useful to kernel hackers who are
1477 debugging unstable kernels.
1479 The LART uses the same LED for both Timer LED and CPU usage LED
1480 functions. You may choose to use both, but the Timer LED function
1481 will overrule the CPU usage LED.
1484 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1486 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1487 || MACH_OMAP_PERSEUS2
1490 If you say Y here, the red LED will be used to give a good real
1491 time indication of CPU usage, by lighting whenever the idle task
1492 is not currently executing.
1494 The LART uses the same LED for both Timer LED and CPU usage LED
1495 functions. You may choose to use both, but the Timer LED function
1496 will overrule the CPU usage LED.
1498 config ALIGNMENT_TRAP
1500 depends on CPU_CP15_MMU
1501 default y if !ARCH_EBSA110
1502 select HAVE_PROC_CPU if PROC_FS
1504 ARM processors cannot fetch/store information which is not
1505 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1506 address divisible by 4. On 32-bit ARM processors, these non-aligned
1507 fetch/store instructions will be emulated in software if you say
1508 here, which has a severe performance impact. This is necessary for
1509 correct operation of some network protocols. With an IP-only
1510 configuration it is safe to say N, otherwise say Y.
1512 config UACCESS_WITH_MEMCPY
1513 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1514 depends on MMU && EXPERIMENTAL
1515 default y if CPU_FEROCEON
1517 Implement faster copy_to_user and clear_user methods for CPU
1518 cores where a 8-word STM instruction give significantly higher
1519 memory write throughput than a sequence of individual 32bit stores.
1521 A possible side effect is a slight increase in scheduling latency
1522 between threads sharing the same address space if they invoke
1523 such copy operations with large buffers.
1525 However, if the CPU data cache is using a write-allocate mode,
1526 this option is unlikely to provide any performance gain.
1530 prompt "Enable seccomp to safely compute untrusted bytecode"
1532 This kernel feature is useful for number crunching applications
1533 that may need to compute untrusted bytecode during their
1534 execution. By using pipes or other transports made available to
1535 the process as file descriptors supporting the read/write
1536 syscalls, it's possible to isolate those applications in
1537 their own address space using seccomp. Once seccomp is
1538 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1539 and the task is only allowed to execute a few safe syscalls
1540 defined by each seccomp mode.
1542 config CC_STACKPROTECTOR
1543 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1544 depends on EXPERIMENTAL
1546 This option turns on the -fstack-protector GCC feature. This
1547 feature puts, at the beginning of functions, a canary value on
1548 the stack just before the return address, and validates
1549 the value just before actually returning. Stack based buffer
1550 overflows (that need to overwrite this return address) now also
1551 overwrite the canary, which gets detected and the attack is then
1552 neutralized via a kernel panic.
1553 This feature requires gcc version 4.2 or above.
1555 config DEPRECATED_PARAM_STRUCT
1556 bool "Provide old way to pass kernel parameters"
1558 This was deprecated in 2001 and announced to live on for 5 years.
1559 Some old boot loaders still use this way.
1565 # Compressed boot loader in ROM. Yes, we really want to ask about
1566 # TEXT and BSS so we preserve their values in the config files.
1567 config ZBOOT_ROM_TEXT
1568 hex "Compressed ROM boot loader base address"
1571 The physical address at which the ROM-able zImage is to be
1572 placed in the target. Platforms which normally make use of
1573 ROM-able zImage formats normally set this to a suitable
1574 value in their defconfig file.
1576 If ZBOOT_ROM is not enabled, this has no effect.
1578 config ZBOOT_ROM_BSS
1579 hex "Compressed ROM boot loader BSS address"
1582 The base address of an area of read/write memory in the target
1583 for the ROM-able zImage which must be available while the
1584 decompressor is running. It must be large enough to hold the
1585 entire decompressed kernel plus an additional 128 KiB.
1586 Platforms which normally make use of ROM-able zImage formats
1587 normally set this to a suitable value in their defconfig file.
1589 If ZBOOT_ROM is not enabled, this has no effect.
1592 bool "Compressed boot loader in ROM/flash"
1593 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1595 Say Y here if you intend to execute your compressed kernel image
1596 (zImage) directly from ROM or flash. If unsure, say N.
1599 string "Default kernel command string"
1602 On some architectures (EBSA110 and CATS), there is currently no way
1603 for the boot loader to pass arguments to the kernel. For these
1604 architectures, you should supply some command-line options at build
1605 time by entering them here. As a minimum, you should specify the
1606 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1608 config CMDLINE_FORCE
1609 bool "Always use the default kernel command string"
1610 depends on CMDLINE != ""
1612 Always use the default kernel command string, even if the boot
1613 loader passes other arguments to the kernel.
1614 This is useful if you cannot or don't want to change the
1615 command-line options your boot loader passes to the kernel.
1620 bool "Kernel Execute-In-Place from ROM"
1621 depends on !ZBOOT_ROM
1623 Execute-In-Place allows the kernel to run from non-volatile storage
1624 directly addressable by the CPU, such as NOR flash. This saves RAM
1625 space since the text section of the kernel is not loaded from flash
1626 to RAM. Read-write sections, such as the data section and stack,
1627 are still copied to RAM. The XIP kernel is not compressed since
1628 it has to run directly from flash, so it will take more space to
1629 store it. The flash address used to link the kernel object files,
1630 and for storing it, is configuration dependent. Therefore, if you
1631 say Y here, you must know the proper physical address where to
1632 store the kernel image depending on your own flash memory usage.
1634 Also note that the make target becomes "make xipImage" rather than
1635 "make zImage" or "make Image". The final kernel binary to put in
1636 ROM memory will be arch/arm/boot/xipImage.
1640 config XIP_PHYS_ADDR
1641 hex "XIP Kernel Physical Location"
1642 depends on XIP_KERNEL
1643 default "0x00080000"
1645 This is the physical address in your flash memory the kernel will
1646 be linked for and stored to. This address is dependent on your
1650 bool "Kexec system call (EXPERIMENTAL)"
1651 depends on EXPERIMENTAL
1653 kexec is a system call that implements the ability to shutdown your
1654 current kernel, and to start another kernel. It is like a reboot
1655 but it is independent of the system firmware. And like a reboot
1656 you can start any kernel with it, not just Linux.
1658 It is an ongoing process to be certain the hardware in a machine
1659 is properly shutdown, so do not be surprised if this code does not
1660 initially work for you. It may help to enable device hotplugging
1664 bool "Export atags in procfs"
1668 Should the atags used to boot the kernel be exported in an "atags"
1669 file in procfs. Useful with kexec.
1672 bool "Build kdump crash kernel (EXPERIMENTAL)"
1673 depends on EXPERIMENTAL
1675 Generate crash dump after being started by kexec. This should
1676 be normally only set in special crash dump kernels which are
1677 loaded in the main kernel with kexec-tools into a specially
1678 reserved region and then later executed after a crash by
1679 kdump/kexec. The crash dump kernel must be compiled to a
1680 memory address not used by the main kernel
1682 For more details see Documentation/kdump/kdump.txt
1684 config AUTO_ZRELADDR
1685 bool "Auto calculation of the decompressed kernel image address"
1686 depends on !ZBOOT_ROM && !ARCH_U300
1688 ZRELADDR is the physical address where the decompressed kernel
1689 image will be placed. If AUTO_ZRELADDR is selected, the address
1690 will be determined at run-time by masking the current IP with
1691 0xf8000000. This assumes the zImage being placed in the first 128MB
1692 from start of memory.
1696 menu "CPU Power Management"
1700 source "drivers/cpufreq/Kconfig"
1703 tristate "CPUfreq driver for i.MX CPUs"
1704 depends on ARCH_MXC && CPU_FREQ
1706 This enables the CPUfreq driver for i.MX CPUs.
1708 config CPU_FREQ_SA1100
1711 config CPU_FREQ_SA1110
1714 config CPU_FREQ_INTEGRATOR
1715 tristate "CPUfreq driver for ARM Integrator CPUs"
1716 depends on ARCH_INTEGRATOR && CPU_FREQ
1719 This enables the CPUfreq driver for ARM Integrator CPUs.
1721 For details, take a look at <file:Documentation/cpu-freq>.
1727 depends on CPU_FREQ && ARCH_PXA && PXA25x
1729 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1731 config CPU_FREQ_S3C64XX
1732 bool "CPUfreq support for Samsung S3C64XX CPUs"
1733 depends on CPU_FREQ && CPU_S3C6410
1738 Internal configuration node for common cpufreq on Samsung SoC
1740 config CPU_FREQ_S3C24XX
1741 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1742 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1745 This enables the CPUfreq driver for the Samsung S3C24XX family
1748 For details, take a look at <file:Documentation/cpu-freq>.
1752 config CPU_FREQ_S3C24XX_PLL
1753 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1754 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1756 Compile in support for changing the PLL frequency from the
1757 S3C24XX series CPUfreq driver. The PLL takes time to settle
1758 after a frequency change, so by default it is not enabled.
1760 This also means that the PLL tables for the selected CPU(s) will
1761 be built which may increase the size of the kernel image.
1763 config CPU_FREQ_S3C24XX_DEBUG
1764 bool "Debug CPUfreq Samsung driver core"
1765 depends on CPU_FREQ_S3C24XX
1767 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1769 config CPU_FREQ_S3C24XX_IODEBUG
1770 bool "Debug CPUfreq Samsung driver IO timing"
1771 depends on CPU_FREQ_S3C24XX
1773 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1775 config CPU_FREQ_S3C24XX_DEBUGFS
1776 bool "Export debugfs for CPUFreq"
1777 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1779 Export status information via debugfs.
1783 source "drivers/cpuidle/Kconfig"
1787 menu "Floating point emulation"
1789 comment "At least one emulation must be selected"
1792 bool "NWFPE math emulation"
1793 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1795 Say Y to include the NWFPE floating point emulator in the kernel.
1796 This is necessary to run most binaries. Linux does not currently
1797 support floating point hardware so you need to say Y here even if
1798 your machine has an FPA or floating point co-processor podule.
1800 You may say N here if you are going to load the Acorn FPEmulator
1801 early in the bootup.
1804 bool "Support extended precision"
1805 depends on FPE_NWFPE
1807 Say Y to include 80-bit support in the kernel floating-point
1808 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1809 Note that gcc does not generate 80-bit operations by default,
1810 so in most cases this option only enlarges the size of the
1811 floating point emulator without any good reason.
1813 You almost surely want to say N here.
1816 bool "FastFPE math emulation (EXPERIMENTAL)"
1817 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1819 Say Y here to include the FAST floating point emulator in the kernel.
1820 This is an experimental much faster emulator which now also has full
1821 precision for the mantissa. It does not support any exceptions.
1822 It is very simple, and approximately 3-6 times faster than NWFPE.
1824 It should be sufficient for most programs. It may be not suitable
1825 for scientific calculations, but you have to check this for yourself.
1826 If you do not feel you need a faster FP emulation you should better
1830 bool "VFP-format floating point maths"
1831 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1833 Say Y to include VFP support code in the kernel. This is needed
1834 if your hardware includes a VFP unit.
1836 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1837 release notes and additional status information.
1839 Say N if your target does not have VFP hardware.
1847 bool "Advanced SIMD (NEON) Extension support"
1848 depends on VFPv3 && CPU_V7
1850 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1855 menu "Userspace binary formats"
1857 source "fs/Kconfig.binfmt"
1860 tristate "RISC OS personality"
1863 Say Y here to include the kernel code necessary if you want to run
1864 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1865 experimental; if this sounds frightening, say N and sleep in peace.
1866 You can also say M here to compile this support as a module (which
1867 will be called arthur).
1871 menu "Power management options"
1873 source "kernel/power/Kconfig"
1875 config ARCH_SUSPEND_POSSIBLE
1880 source "net/Kconfig"
1882 source "drivers/Kconfig"
1886 source "arch/arm/Kconfig.debug"
1888 source "security/Kconfig"
1890 source "crypto/Kconfig"
1892 source "lib/Kconfig"