5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary, or theoretically 64K
206 for the MSM machine class.
208 config ARM_PATCH_PHYS_VIRT_16BIT
210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
212 This option extends the physical to virtual translation patching
213 to allow physical memory down to a theoretical minimum of 64K
216 source "init/Kconfig"
218 source "kernel/Kconfig.freezer"
223 bool "MMU-based Paged Memory Management Support"
226 Select if you want MMU-based virtualised addressing space
227 support by paged memory management. If unsure, say 'Y'.
230 # The "ARM system type" choice list is ordered alphabetically by option
231 # text. Please add new entries in the option alphabetic order.
234 prompt "ARM system type"
235 default ARCH_VERSATILE
237 config ARCH_INTEGRATOR
238 bool "ARM Ltd. Integrator family"
240 select ARCH_HAS_CPUFREQ
243 select GENERIC_CLOCKEVENTS
244 select PLAT_VERSATILE
245 select PLAT_VERSATILE_FPGA_IRQ
247 Support for ARM's Integrator platform.
250 bool "ARM Ltd. RealView family"
254 select GENERIC_CLOCKEVENTS
255 select ARCH_WANT_OPTIONAL_GPIOLIB
256 select PLAT_VERSATILE
257 select PLAT_VERSATILE_CLCD
258 select ARM_TIMER_SP804
259 select GPIO_PL061 if GPIOLIB
261 This enables support for ARM Ltd RealView boards.
263 config ARCH_VERSATILE
264 bool "ARM Ltd. Versatile family"
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select PLAT_VERSATILE_FPGA_IRQ
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_PATA_PLATFORM
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
291 This enables support for the ARM Ltd Versatile Express boards.
295 select ARCH_REQUIRE_GPIOLIB
298 This enables support for systems based on the Atmel AT91RM9200,
299 AT91SAM9 and AT91CAP9 processors.
302 bool "Broadcom BCMRING"
307 select GENERIC_CLOCKEVENTS
308 select ARCH_WANT_OPTIONAL_GPIOLIB
310 Support for Broadcom's BCMRing platform.
313 bool "Cirrus Logic CLPS711x/EP721x-based"
315 select ARCH_USES_GETTIMEOFFSET
317 Support for Cirrus Logic 711x/721x based boards.
320 bool "Cavium Networks CNS3XXX family"
322 select GENERIC_CLOCKEVENTS
324 select MIGHT_HAVE_PCI
325 select PCI_DOMAINS if PCI
327 Support for Cavium Networks CNS3XXX platform.
330 bool "Cortina Systems Gemini"
332 select ARCH_REQUIRE_GPIOLIB
333 select ARCH_USES_GETTIMEOFFSET
335 Support for the Cortina Systems Gemini family SoCs
342 select ARCH_USES_GETTIMEOFFSET
344 This is an evaluation board for the StrongARM processor available
345 from Digital. It has limited hardware on-board, including an
346 Ethernet interface, two PCMCIA sockets, two serial ports and a
355 select ARCH_REQUIRE_GPIOLIB
356 select ARCH_HAS_HOLES_MEMORYMODEL
357 select ARCH_USES_GETTIMEOFFSET
359 This enables support for the Cirrus EP93xx series of CPUs.
361 config ARCH_FOOTBRIDGE
365 select GENERIC_CLOCKEVENTS
367 Support for systems based on the DC21285 companion chip
368 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
371 bool "Freescale MXC/iMX-based"
372 select GENERIC_CLOCKEVENTS
373 select ARCH_REQUIRE_GPIOLIB
375 select HAVE_SCHED_CLOCK
377 Support for Freescale MXC/iMX-based family of processors
380 bool "Freescale MXS-based"
381 select GENERIC_CLOCKEVENTS
382 select ARCH_REQUIRE_GPIOLIB
385 Support for Freescale MXS-based family of processors
388 bool "Freescale STMP3xxx"
391 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
393 select USB_ARCH_HAS_EHCI
395 Support for systems based on the Freescale 3xxx CPUs.
398 bool "Hilscher NetX based"
401 select GENERIC_CLOCKEVENTS
403 This enables support for systems based on the Hilscher NetX Soc
406 bool "Hynix HMS720x-based"
409 select ARCH_USES_GETTIMEOFFSET
411 This enables support for systems based on the Hynix HMS720x
419 select ARCH_SUPPORTS_MSI
422 Support for Intel's IOP13XX (XScale) family of processors.
430 select ARCH_REQUIRE_GPIOLIB
432 Support for Intel's 80219 and IOP32X (XScale) family of
441 select ARCH_REQUIRE_GPIOLIB
443 Support for Intel's IOP33X (XScale) family of processors.
450 select ARCH_USES_GETTIMEOFFSET
452 Support for Intel's IXP23xx (XScale) family of processors.
455 bool "IXP2400/2800-based"
459 select ARCH_USES_GETTIMEOFFSET
461 Support for Intel's IXP2400/2800 (XScale) family of processors.
468 select GENERIC_CLOCKEVENTS
469 select HAVE_SCHED_CLOCK
470 select MIGHT_HAVE_PCI
471 select DMABOUNCE if PCI
473 Support for Intel's IXP4XX (XScale) family of processors.
479 select ARCH_REQUIRE_GPIOLIB
480 select GENERIC_CLOCKEVENTS
483 Support for the Marvell Dove SoC 88AP510
486 bool "Marvell Kirkwood"
489 select ARCH_REQUIRE_GPIOLIB
490 select GENERIC_CLOCKEVENTS
493 Support for the following Marvell Kirkwood series SoCs:
494 88F6180, 88F6192 and 88F6281.
497 bool "Marvell Loki (88RC8480)"
499 select GENERIC_CLOCKEVENTS
502 Support for the Marvell Loki (88RC8480) SoC.
507 select ARCH_REQUIRE_GPIOLIB
510 select USB_ARCH_HAS_OHCI
513 select GENERIC_CLOCKEVENTS
515 Support for the NXP LPC32XX family of processors
518 bool "Marvell MV78xx0"
521 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
525 Support for the following Marvell MV78xx0 series SoCs:
533 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
537 Support for the following Marvell Orion 5x series SoCs:
538 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
539 Orion-2 (5281), Orion-1-90 (6183).
542 bool "Marvell PXA168/910/MMP2"
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
547 select HAVE_SCHED_CLOCK
552 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
555 bool "Micrel/Kendin KS8695"
557 select ARCH_REQUIRE_GPIOLIB
558 select ARCH_USES_GETTIMEOFFSET
560 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
561 System-on-Chip devices.
564 bool "NetSilicon NS9xxx"
567 select GENERIC_CLOCKEVENTS
570 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
573 <http://www.digi.com/products/microprocessors/index.jsp>
576 bool "Nuvoton W90X900 CPU"
578 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 bool "Nuvoton NUC93X CPU"
595 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
596 low-power and high performance MPEG-4/JPEG multimedia controller chip.
602 select GENERIC_CLOCKEVENTS
605 select HAVE_SCHED_CLOCK
606 select ARCH_HAS_BARRIERS if CACHE_L2X0
607 select ARCH_HAS_CPUFREQ
609 This enables support for NVIDIA Tegra based systems (Tegra APX,
610 Tegra 6xx and Tegra 2 series).
613 bool "Philips Nexperia PNX4008 Mobile"
616 select ARCH_USES_GETTIMEOFFSET
618 This enables support for Philips PNX4008 mobile platform.
621 bool "PXA2xx/PXA3xx-based"
624 select ARCH_HAS_CPUFREQ
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select HAVE_SCHED_CLOCK
633 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
638 select GENERIC_CLOCKEVENTS
639 select ARCH_REQUIRE_GPIOLIB
642 Support for Qualcomm MSM/QSD based systems. This runs on the
643 apps processor of the MSM/QSD and depends on a shared memory
644 interface to the modem processor which runs the baseband
645 stack and controls some vital subsystems
646 (clock and power control, etc).
649 bool "Renesas SH-Mobile / R-Mobile"
652 select GENERIC_CLOCKEVENTS
655 select MULTI_IRQ_HANDLER
657 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
664 select ARCH_MAY_HAVE_PC_FDC
665 select HAVE_PATA_PLATFORM
668 select ARCH_SPARSEMEM_ENABLE
669 select ARCH_USES_GETTIMEOFFSET
671 On the Acorn Risc-PC, Linux can support the internal IDE disk and
672 CD-ROM interface, serial and parallel port, and the floppy drive.
678 select ARCH_SPARSEMEM_ENABLE
680 select ARCH_HAS_CPUFREQ
682 select GENERIC_CLOCKEVENTS
684 select HAVE_SCHED_CLOCK
686 select ARCH_REQUIRE_GPIOLIB
688 Support for StrongARM 11x0 based boards.
691 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
693 select ARCH_HAS_CPUFREQ
695 select ARCH_USES_GETTIMEOFFSET
696 select HAVE_S3C2410_I2C if I2C
698 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
699 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
700 the Samsung SMDK2410 development board (and derivatives).
702 Note, the S3C2416 and the S3C2450 are so close that they even share
703 the same SoC ID code. This means that there is no separate machine
704 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
707 bool "Samsung S3C64XX"
713 select ARCH_USES_GETTIMEOFFSET
714 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
716 select SAMSUNG_CLKSRC
717 select SAMSUNG_IRQ_VIC_TIMER
718 select SAMSUNG_IRQ_UART
719 select S3C_GPIO_TRACK
720 select S3C_GPIO_PULL_UPDOWN
721 select S3C_GPIO_CFG_S3C24XX
722 select S3C_GPIO_CFG_S3C64XX
724 select USB_ARCH_HAS_OHCI
725 select SAMSUNG_GPIOLIB_4BIT
726 select HAVE_S3C2410_I2C if I2C
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
729 Samsung S3C64XX series based systems
732 bool "Samsung S5P6440 S5P6450"
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select GENERIC_CLOCKEVENTS
738 select HAVE_SCHED_CLOCK
739 select HAVE_S3C2410_I2C if I2C
740 select HAVE_S3C_RTC if RTC_CLASS
742 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
746 bool "Samsung S5P6442"
750 select ARCH_USES_GETTIMEOFFSET
751 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 Samsung S5P6442 CPU based systems
756 bool "Samsung S5PC100"
760 select ARM_L1_CACHE_SHIFT_6
761 select ARCH_USES_GETTIMEOFFSET
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C_RTC if RTC_CLASS
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 Samsung S5PC100 series based systems
769 bool "Samsung S5PV210/S5PC110"
771 select ARCH_SPARSEMEM_ENABLE
774 select ARM_L1_CACHE_SHIFT_6
775 select ARCH_HAS_CPUFREQ
776 select GENERIC_CLOCKEVENTS
777 select HAVE_SCHED_CLOCK
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C_RTC if RTC_CLASS
780 select HAVE_S3C2410_WATCHDOG if WATCHDOG
782 Samsung S5PV210/S5PC110 series based systems
785 bool "Samsung EXYNOS4"
787 select ARCH_SPARSEMEM_ENABLE
790 select ARCH_HAS_CPUFREQ
791 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C_RTC if RTC_CLASS
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 Samsung EXYNOS4 series based systems
805 select ARCH_USES_GETTIMEOFFSET
807 Support for the StrongARM based Digital DNARD machine, also known
808 as "Shark" (<http://www.shark-linux.de/shark.html>).
811 bool "Telechips TCC ARM926-based systems"
815 select GENERIC_CLOCKEVENTS
817 Support for Telechips TCC ARM926-based systems.
820 bool "ST-Ericsson U300 Series"
823 select HAVE_SCHED_CLOCK
827 select GENERIC_CLOCKEVENTS
831 Support for ST-Ericsson U300 series mobile platforms.
834 bool "ST-Ericsson U8500 Series"
837 select GENERIC_CLOCKEVENTS
839 select ARCH_REQUIRE_GPIOLIB
840 select ARCH_HAS_CPUFREQ
842 Support for ST-Ericsson's Ux500 architecture
845 bool "STMicroelectronics Nomadik"
850 select GENERIC_CLOCKEVENTS
851 select ARCH_REQUIRE_GPIOLIB
853 Support for the Nomadik platform by ST-Ericsson
857 select GENERIC_CLOCKEVENTS
858 select ARCH_REQUIRE_GPIOLIB
862 select GENERIC_ALLOCATOR
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 Support for TI's DaVinci platform.
870 select ARCH_REQUIRE_GPIOLIB
871 select ARCH_HAS_CPUFREQ
872 select GENERIC_CLOCKEVENTS
873 select HAVE_SCHED_CLOCK
874 select ARCH_HAS_HOLES_MEMORYMODEL
876 Support for TI's OMAP platform (OMAP1/2/3/4).
881 select ARCH_REQUIRE_GPIOLIB
883 select GENERIC_CLOCKEVENTS
886 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
889 bool "VIA/WonderMedia 85xx"
892 select ARCH_HAS_CPUFREQ
893 select GENERIC_CLOCKEVENTS
894 select ARCH_REQUIRE_GPIOLIB
897 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
901 # This is sorted alphabetically by mach-* pathname. However, plat-*
902 # Kconfigs may be included either alphabetically (according to the
903 # plat- suffix) or along side the corresponding mach-* source.
905 source "arch/arm/mach-at91/Kconfig"
907 source "arch/arm/mach-bcmring/Kconfig"
909 source "arch/arm/mach-clps711x/Kconfig"
911 source "arch/arm/mach-cns3xxx/Kconfig"
913 source "arch/arm/mach-davinci/Kconfig"
915 source "arch/arm/mach-dove/Kconfig"
917 source "arch/arm/mach-ep93xx/Kconfig"
919 source "arch/arm/mach-footbridge/Kconfig"
921 source "arch/arm/mach-gemini/Kconfig"
923 source "arch/arm/mach-h720x/Kconfig"
925 source "arch/arm/mach-integrator/Kconfig"
927 source "arch/arm/mach-iop32x/Kconfig"
929 source "arch/arm/mach-iop33x/Kconfig"
931 source "arch/arm/mach-iop13xx/Kconfig"
933 source "arch/arm/mach-ixp4xx/Kconfig"
935 source "arch/arm/mach-ixp2000/Kconfig"
937 source "arch/arm/mach-ixp23xx/Kconfig"
939 source "arch/arm/mach-kirkwood/Kconfig"
941 source "arch/arm/mach-ks8695/Kconfig"
943 source "arch/arm/mach-loki/Kconfig"
945 source "arch/arm/mach-lpc32xx/Kconfig"
947 source "arch/arm/mach-msm/Kconfig"
949 source "arch/arm/mach-mv78xx0/Kconfig"
951 source "arch/arm/plat-mxc/Kconfig"
953 source "arch/arm/mach-mxs/Kconfig"
955 source "arch/arm/mach-netx/Kconfig"
957 source "arch/arm/mach-nomadik/Kconfig"
958 source "arch/arm/plat-nomadik/Kconfig"
960 source "arch/arm/mach-ns9xxx/Kconfig"
962 source "arch/arm/mach-nuc93x/Kconfig"
964 source "arch/arm/plat-omap/Kconfig"
966 source "arch/arm/mach-omap1/Kconfig"
968 source "arch/arm/mach-omap2/Kconfig"
970 source "arch/arm/mach-orion5x/Kconfig"
972 source "arch/arm/mach-pxa/Kconfig"
973 source "arch/arm/plat-pxa/Kconfig"
975 source "arch/arm/mach-mmp/Kconfig"
977 source "arch/arm/mach-realview/Kconfig"
979 source "arch/arm/mach-sa1100/Kconfig"
981 source "arch/arm/plat-samsung/Kconfig"
982 source "arch/arm/plat-s3c24xx/Kconfig"
983 source "arch/arm/plat-s5p/Kconfig"
985 source "arch/arm/plat-spear/Kconfig"
987 source "arch/arm/plat-tcc/Kconfig"
990 source "arch/arm/mach-s3c2400/Kconfig"
991 source "arch/arm/mach-s3c2410/Kconfig"
992 source "arch/arm/mach-s3c2412/Kconfig"
993 source "arch/arm/mach-s3c2416/Kconfig"
994 source "arch/arm/mach-s3c2440/Kconfig"
995 source "arch/arm/mach-s3c2443/Kconfig"
999 source "arch/arm/mach-s3c64xx/Kconfig"
1002 source "arch/arm/mach-s5p64x0/Kconfig"
1004 source "arch/arm/mach-s5p6442/Kconfig"
1006 source "arch/arm/mach-s5pc100/Kconfig"
1008 source "arch/arm/mach-s5pv210/Kconfig"
1010 source "arch/arm/mach-exynos4/Kconfig"
1012 source "arch/arm/mach-shmobile/Kconfig"
1014 source "arch/arm/plat-stmp3xxx/Kconfig"
1016 source "arch/arm/mach-tegra/Kconfig"
1018 source "arch/arm/mach-u300/Kconfig"
1020 source "arch/arm/mach-ux500/Kconfig"
1022 source "arch/arm/mach-versatile/Kconfig"
1024 source "arch/arm/mach-vexpress/Kconfig"
1025 source "arch/arm/plat-versatile/Kconfig"
1027 source "arch/arm/mach-vt8500/Kconfig"
1029 source "arch/arm/mach-w90x900/Kconfig"
1031 # Definitions to make life easier
1037 select GENERIC_CLOCKEVENTS
1038 select HAVE_SCHED_CLOCK
1042 select HAVE_SCHED_CLOCK
1047 config PLAT_VERSATILE
1050 config ARM_TIMER_SP804
1053 source arch/arm/mm/Kconfig
1056 bool "Enable iWMMXt support"
1057 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1058 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1060 Enable support for iWMMXt context switching at run time if
1061 running on a CPU that supports it.
1063 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1066 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1070 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1071 (!ARCH_OMAP3 || OMAP3_EMU)
1075 config MULTI_IRQ_HANDLER
1078 Allow each machine to specify it's own IRQ handler at run time.
1081 source "arch/arm/Kconfig-nommu"
1084 config ARM_ERRATA_411920
1085 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1086 depends on CPU_V6 || CPU_V6K
1088 Invalidation of the Instruction Cache operation can
1089 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1090 It does not affect the MPCore. This option enables the ARM Ltd.
1091 recommended workaround.
1093 config ARM_ERRATA_430973
1094 bool "ARM errata: Stale prediction on replaced interworking branch"
1097 This option enables the workaround for the 430973 Cortex-A8
1098 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1099 interworking branch is replaced with another code sequence at the
1100 same virtual address, whether due to self-modifying code or virtual
1101 to physical address re-mapping, Cortex-A8 does not recover from the
1102 stale interworking branch prediction. This results in Cortex-A8
1103 executing the new code sequence in the incorrect ARM or Thumb state.
1104 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1105 and also flushes the branch target cache at every context switch.
1106 Note that setting specific bits in the ACTLR register may not be
1107 available in non-secure mode.
1109 config ARM_ERRATA_458693
1110 bool "ARM errata: Processor deadlock when a false hazard is created"
1113 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1114 erratum. For very specific sequences of memory operations, it is
1115 possible for a hazard condition intended for a cache line to instead
1116 be incorrectly associated with a different cache line. This false
1117 hazard might then cause a processor deadlock. The workaround enables
1118 the L1 caching of the NEON accesses and disables the PLD instruction
1119 in the ACTLR register. Note that setting specific bits in the ACTLR
1120 register may not be available in non-secure mode.
1122 config ARM_ERRATA_460075
1123 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1126 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1127 erratum. Any asynchronous access to the L2 cache may encounter a
1128 situation in which recent store transactions to the L2 cache are lost
1129 and overwritten with stale memory contents from external memory. The
1130 workaround disables the write-allocate mode for the L2 cache via the
1131 ACTLR register. Note that setting specific bits in the ACTLR register
1132 may not be available in non-secure mode.
1134 config ARM_ERRATA_742230
1135 bool "ARM errata: DMB operation may be faulty"
1136 depends on CPU_V7 && SMP
1138 This option enables the workaround for the 742230 Cortex-A9
1139 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1140 between two write operations may not ensure the correct visibility
1141 ordering of the two writes. This workaround sets a specific bit in
1142 the diagnostic register of the Cortex-A9 which causes the DMB
1143 instruction to behave as a DSB, ensuring the correct behaviour of
1146 config ARM_ERRATA_742231
1147 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1148 depends on CPU_V7 && SMP
1150 This option enables the workaround for the 742231 Cortex-A9
1151 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1152 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1153 accessing some data located in the same cache line, may get corrupted
1154 data due to bad handling of the address hazard when the line gets
1155 replaced from one of the CPUs at the same time as another CPU is
1156 accessing it. This workaround sets specific bits in the diagnostic
1157 register of the Cortex-A9 which reduces the linefill issuing
1158 capabilities of the processor.
1160 config PL310_ERRATA_588369
1161 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1162 depends on CACHE_L2X0
1164 The PL310 L2 cache controller implements three types of Clean &
1165 Invalidate maintenance operations: by Physical Address
1166 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1167 They are architecturally defined to behave as the execution of a
1168 clean operation followed immediately by an invalidate operation,
1169 both performing to the same memory location. This functionality
1170 is not correctly implemented in PL310 as clean lines are not
1171 invalidated as a result of these operations.
1173 config ARM_ERRATA_720789
1174 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1175 depends on CPU_V7 && SMP
1177 This option enables the workaround for the 720789 Cortex-A9 (prior to
1178 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1179 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1180 As a consequence of this erratum, some TLB entries which should be
1181 invalidated are not, resulting in an incoherency in the system page
1182 tables. The workaround changes the TLB flushing routines to invalidate
1183 entries regardless of the ASID.
1185 config PL310_ERRATA_727915
1186 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1187 depends on CACHE_L2X0
1189 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1190 operation (offset 0x7FC). This operation runs in background so that
1191 PL310 can handle normal accesses while it is in progress. Under very
1192 rare circumstances, due to this erratum, write data can be lost when
1193 PL310 treats a cacheable write transaction during a Clean &
1194 Invalidate by Way operation.
1196 config ARM_ERRATA_743622
1197 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1200 This option enables the workaround for the 743622 Cortex-A9
1201 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1202 optimisation in the Cortex-A9 Store Buffer may lead to data
1203 corruption. This workaround sets a specific bit in the diagnostic
1204 register of the Cortex-A9 which disables the Store Buffer
1205 optimisation, preventing the defect from occurring. This has no
1206 visible impact on the overall performance or power consumption of the
1209 config ARM_ERRATA_751472
1210 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1211 depends on CPU_V7 && SMP
1213 This option enables the workaround for the 751472 Cortex-A9 (prior
1214 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1215 completion of a following broadcasted operation if the second
1216 operation is received by a CPU before the ICIALLUIS has completed,
1217 potentially leading to corrupted entries in the cache or TLB.
1219 config ARM_ERRATA_753970
1220 bool "ARM errata: cache sync operation may be faulty"
1221 depends on CACHE_PL310
1223 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1225 Under some condition the effect of cache sync operation on
1226 the store buffer still remains when the operation completes.
1227 This means that the store buffer is always asked to drain and
1228 this prevents it from merging any further writes. The workaround
1229 is to replace the normal offset of cache sync operation (0x730)
1230 by another offset targeting an unmapped PL310 register 0x740.
1231 This has the same effect as the cache sync operation: store buffer
1232 drain and waiting for all buffers empty.
1234 config ARM_ERRATA_754322
1235 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1238 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1239 r3p*) erratum. A speculative memory access may cause a page table walk
1240 which starts prior to an ASID switch but completes afterwards. This
1241 can populate the micro-TLB with a stale entry which may be hit with
1242 the new ASID. This workaround places two dsb instructions in the mm
1243 switching code so that no page table walks can cross the ASID switch.
1245 config ARM_ERRATA_754327
1246 bool "ARM errata: no automatic Store Buffer drain"
1247 depends on CPU_V7 && SMP
1249 This option enables the workaround for the 754327 Cortex-A9 (prior to
1250 r2p0) erratum. The Store Buffer does not have any automatic draining
1251 mechanism and therefore a livelock may occur if an external agent
1252 continuously polls a memory location waiting to observe an update.
1253 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1254 written polling loops from denying visibility of updates to memory.
1258 source "arch/arm/common/Kconfig"
1268 Find out whether you have ISA slots on your motherboard. ISA is the
1269 name of a bus system, i.e. the way the CPU talks to the other stuff
1270 inside your box. Other bus systems are PCI, EISA, MicroChannel
1271 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1272 newer boards don't support it. If you have ISA, say Y, otherwise N.
1274 # Select ISA DMA controller support
1279 # Select ISA DMA interface
1284 bool "PCI support" if MIGHT_HAVE_PCI
1286 Find out whether you have a PCI motherboard. PCI is the name of a
1287 bus system, i.e. the way the CPU talks to the other stuff inside
1288 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1289 VESA. If you have PCI, say Y, otherwise N.
1295 config PCI_NANOENGINE
1296 bool "BSE nanoEngine PCI support"
1297 depends on SA1100_NANOENGINE
1299 Enable PCI on the BSE nanoEngine board.
1304 # Select the host bridge type
1305 config PCI_HOST_VIA82C505
1307 depends on PCI && ARCH_SHARK
1310 config PCI_HOST_ITE8152
1312 depends on PCI && MACH_ARMCORE
1316 source "drivers/pci/Kconfig"
1318 source "drivers/pcmcia/Kconfig"
1322 menu "Kernel Features"
1324 source "kernel/time/Kconfig"
1327 bool "Symmetric Multi-Processing"
1328 depends on CPU_V6K || CPU_V7
1329 depends on GENERIC_CLOCKEVENTS
1330 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1331 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1332 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1333 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1334 select USE_GENERIC_SMP_HELPERS
1335 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1337 This enables support for systems with more than one CPU. If you have
1338 a system with only one CPU, like most personal computers, say N. If
1339 you have a system with more than one CPU, say Y.
1341 If you say N here, the kernel will run on single and multiprocessor
1342 machines, but will use only one CPU of a multiprocessor machine. If
1343 you say Y here, the kernel will run on many, but not all, single
1344 processor machines. On a single processor machine, the kernel will
1345 run faster if you say N here.
1347 See also <file:Documentation/i386/IO-APIC.txt>,
1348 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1349 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1351 If you don't know what to do here, say N.
1354 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1355 depends on EXPERIMENTAL
1356 depends on SMP && !XIP_KERNEL
1359 SMP kernels contain instructions which fail on non-SMP processors.
1360 Enabling this option allows the kernel to modify itself to make
1361 these instructions safe. Disabling it allows about 1K of space
1364 If you don't know what to do here, say Y.
1370 This option enables support for the ARM system coherency unit
1377 This options enables support for the ARM timer and watchdog unit
1380 prompt "Memory split"
1383 Select the desired split between kernel and user memory.
1385 If you are not absolutely sure what you are doing, leave this
1389 bool "3G/1G user/kernel split"
1391 bool "2G/2G user/kernel split"
1393 bool "1G/3G user/kernel split"
1398 default 0x40000000 if VMSPLIT_1G
1399 default 0x80000000 if VMSPLIT_2G
1403 int "Maximum number of CPUs (2-32)"
1409 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1410 depends on SMP && HOTPLUG && EXPERIMENTAL
1411 depends on !ARCH_MSM
1413 Say Y here to experiment with turning CPUs off and on. CPUs
1414 can be controlled through /sys/devices/system/cpu.
1417 bool "Use local timer interrupts"
1420 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1422 Enable support for local timers on SMP platforms, rather then the
1423 legacy IPI broadcast method. Local timers allows the system
1424 accounting to be spread across the timer interval, preventing a
1425 "thundering herd" at every timer tick.
1427 source kernel/Kconfig.preempt
1431 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1432 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1433 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1434 default AT91_TIMER_HZ if ARCH_AT91
1435 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1438 config THUMB2_KERNEL
1439 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1440 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1442 select ARM_ASM_UNIFIED
1444 By enabling this option, the kernel will be compiled in
1445 Thumb-2 mode. A compiler/assembler that understand the unified
1446 ARM-Thumb syntax is needed.
1450 config THUMB2_AVOID_R_ARM_THM_JUMP11
1451 bool "Work around buggy Thumb-2 short branch relocations in gas"
1452 depends on THUMB2_KERNEL && MODULES
1455 Various binutils versions can resolve Thumb-2 branches to
1456 locally-defined, preemptible global symbols as short-range "b.n"
1457 branch instructions.
1459 This is a problem, because there's no guarantee the final
1460 destination of the symbol, or any candidate locations for a
1461 trampoline, are within range of the branch. For this reason, the
1462 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1463 relocation in modules at all, and it makes little sense to add
1466 The symptom is that the kernel fails with an "unsupported
1467 relocation" error when loading some modules.
1469 Until fixed tools are available, passing
1470 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1471 code which hits this problem, at the cost of a bit of extra runtime
1472 stack usage in some cases.
1474 The problem is described in more detail at:
1475 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1477 Only Thumb-2 kernels are affected.
1479 Unless you are sure your tools don't have this problem, say Y.
1481 config ARM_ASM_UNIFIED
1485 bool "Use the ARM EABI to compile the kernel"
1487 This option allows for the kernel to be compiled using the latest
1488 ARM ABI (aka EABI). This is only useful if you are using a user
1489 space environment that is also compiled with EABI.
1491 Since there are major incompatibilities between the legacy ABI and
1492 EABI, especially with regard to structure member alignment, this
1493 option also changes the kernel syscall calling convention to
1494 disambiguate both ABIs and allow for backward compatibility support
1495 (selected with CONFIG_OABI_COMPAT).
1497 To use this you need GCC version 4.0.0 or later.
1500 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1501 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1504 This option preserves the old syscall interface along with the
1505 new (ARM EABI) one. It also provides a compatibility layer to
1506 intercept syscalls that have structure arguments which layout
1507 in memory differs between the legacy ABI and the new ARM EABI
1508 (only for non "thumb" binaries). This option adds a tiny
1509 overhead to all syscalls and produces a slightly larger kernel.
1510 If you know you'll be using only pure EABI user space then you
1511 can say N here. If this option is not selected and you attempt
1512 to execute a legacy ABI binary then the result will be
1513 UNPREDICTABLE (in fact it can be predicted that it won't work
1514 at all). If in doubt say Y.
1516 config ARCH_HAS_HOLES_MEMORYMODEL
1519 config ARCH_SPARSEMEM_ENABLE
1522 config ARCH_SPARSEMEM_DEFAULT
1523 def_bool ARCH_SPARSEMEM_ENABLE
1525 config ARCH_SELECT_MEMORY_MODEL
1526 def_bool ARCH_SPARSEMEM_ENABLE
1529 bool "High Memory Support"
1532 The address space of ARM processors is only 4 Gigabytes large
1533 and it has to accommodate user address space, kernel address
1534 space as well as some memory mapped IO. That means that, if you
1535 have a large amount of physical memory and/or IO, not all of the
1536 memory can be "permanently mapped" by the kernel. The physical
1537 memory that is not permanently mapped is called "high memory".
1539 Depending on the selected kernel/user memory split, minimum
1540 vmalloc space and actual amount of RAM, you may not need this
1541 option which should result in a slightly faster kernel.
1546 bool "Allocate 2nd-level pagetables from highmem"
1549 config HW_PERF_EVENTS
1550 bool "Enable hardware performance counter support for perf events"
1551 depends on PERF_EVENTS && CPU_HAS_PMU
1554 Enable hardware performance counter support for perf events. If
1555 disabled, perf events will use software events only.
1559 config FORCE_MAX_ZONEORDER
1560 int "Maximum zone order" if ARCH_SHMOBILE
1561 range 11 64 if ARCH_SHMOBILE
1562 default "9" if SA1111
1565 The kernel memory allocator divides physically contiguous memory
1566 blocks into "zones", where each zone is a power of two number of
1567 pages. This option selects the largest power of two that the kernel
1568 keeps in the memory allocator. If you need to allocate very large
1569 blocks of physically contiguous memory, then you may need to
1570 increase this value.
1572 This config option is actually maximum order plus one. For example,
1573 a value of 11 means that the largest free memory block is 2^10 pages.
1576 bool "Timer and CPU usage LEDs"
1577 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1578 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1579 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1580 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1581 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1582 ARCH_AT91 || ARCH_DAVINCI || \
1583 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1585 If you say Y here, the LEDs on your machine will be used
1586 to provide useful information about your current system status.
1588 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1589 be able to select which LEDs are active using the options below. If
1590 you are compiling a kernel for the EBSA-110 or the LART however, the
1591 red LED will simply flash regularly to indicate that the system is
1592 still functional. It is safe to say Y here if you have a CATS
1593 system, but the driver will do nothing.
1596 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1597 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1598 || MACH_OMAP_PERSEUS2
1600 depends on !GENERIC_CLOCKEVENTS
1601 default y if ARCH_EBSA110
1603 If you say Y here, one of the system LEDs (the green one on the
1604 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1605 will flash regularly to indicate that the system is still
1606 operational. This is mainly useful to kernel hackers who are
1607 debugging unstable kernels.
1609 The LART uses the same LED for both Timer LED and CPU usage LED
1610 functions. You may choose to use both, but the Timer LED function
1611 will overrule the CPU usage LED.
1614 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1616 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1617 || MACH_OMAP_PERSEUS2
1620 If you say Y here, the red LED will be used to give a good real
1621 time indication of CPU usage, by lighting whenever the idle task
1622 is not currently executing.
1624 The LART uses the same LED for both Timer LED and CPU usage LED
1625 functions. You may choose to use both, but the Timer LED function
1626 will overrule the CPU usage LED.
1628 config ALIGNMENT_TRAP
1630 depends on CPU_CP15_MMU
1631 default y if !ARCH_EBSA110
1632 select HAVE_PROC_CPU if PROC_FS
1634 ARM processors cannot fetch/store information which is not
1635 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1636 address divisible by 4. On 32-bit ARM processors, these non-aligned
1637 fetch/store instructions will be emulated in software if you say
1638 here, which has a severe performance impact. This is necessary for
1639 correct operation of some network protocols. With an IP-only
1640 configuration it is safe to say N, otherwise say Y.
1642 config UACCESS_WITH_MEMCPY
1643 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1644 depends on MMU && EXPERIMENTAL
1645 default y if CPU_FEROCEON
1647 Implement faster copy_to_user and clear_user methods for CPU
1648 cores where a 8-word STM instruction give significantly higher
1649 memory write throughput than a sequence of individual 32bit stores.
1651 A possible side effect is a slight increase in scheduling latency
1652 between threads sharing the same address space if they invoke
1653 such copy operations with large buffers.
1655 However, if the CPU data cache is using a write-allocate mode,
1656 this option is unlikely to provide any performance gain.
1660 prompt "Enable seccomp to safely compute untrusted bytecode"
1662 This kernel feature is useful for number crunching applications
1663 that may need to compute untrusted bytecode during their
1664 execution. By using pipes or other transports made available to
1665 the process as file descriptors supporting the read/write
1666 syscalls, it's possible to isolate those applications in
1667 their own address space using seccomp. Once seccomp is
1668 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1669 and the task is only allowed to execute a few safe syscalls
1670 defined by each seccomp mode.
1672 config CC_STACKPROTECTOR
1673 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1674 depends on EXPERIMENTAL
1676 This option turns on the -fstack-protector GCC feature. This
1677 feature puts, at the beginning of functions, a canary value on
1678 the stack just before the return address, and validates
1679 the value just before actually returning. Stack based buffer
1680 overflows (that need to overwrite this return address) now also
1681 overwrite the canary, which gets detected and the attack is then
1682 neutralized via a kernel panic.
1683 This feature requires gcc version 4.2 or above.
1685 config DEPRECATED_PARAM_STRUCT
1686 bool "Provide old way to pass kernel parameters"
1688 This was deprecated in 2001 and announced to live on for 5 years.
1689 Some old boot loaders still use this way.
1695 # Compressed boot loader in ROM. Yes, we really want to ask about
1696 # TEXT and BSS so we preserve their values in the config files.
1697 config ZBOOT_ROM_TEXT
1698 hex "Compressed ROM boot loader base address"
1701 The physical address at which the ROM-able zImage is to be
1702 placed in the target. Platforms which normally make use of
1703 ROM-able zImage formats normally set this to a suitable
1704 value in their defconfig file.
1706 If ZBOOT_ROM is not enabled, this has no effect.
1708 config ZBOOT_ROM_BSS
1709 hex "Compressed ROM boot loader BSS address"
1712 The base address of an area of read/write memory in the target
1713 for the ROM-able zImage which must be available while the
1714 decompressor is running. It must be large enough to hold the
1715 entire decompressed kernel plus an additional 128 KiB.
1716 Platforms which normally make use of ROM-able zImage formats
1717 normally set this to a suitable value in their defconfig file.
1719 If ZBOOT_ROM is not enabled, this has no effect.
1722 bool "Compressed boot loader in ROM/flash"
1723 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1725 Say Y here if you intend to execute your compressed kernel image
1726 (zImage) directly from ROM or flash. If unsure, say N.
1728 config ZBOOT_ROM_MMCIF
1729 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1730 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1732 Say Y here to include experimental MMCIF loading code in the
1733 ROM-able zImage. With this enabled it is possible to write the
1734 the ROM-able zImage kernel image to an MMC card and boot the
1735 kernel straight from the reset vector. At reset the processor
1736 Mask ROM will load the first part of the the ROM-able zImage
1737 which in turn loads the rest the kernel image to RAM using the
1738 MMCIF hardware block.
1741 string "Default kernel command string"
1744 On some architectures (EBSA110 and CATS), there is currently no way
1745 for the boot loader to pass arguments to the kernel. For these
1746 architectures, you should supply some command-line options at build
1747 time by entering them here. As a minimum, you should specify the
1748 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1751 prompt "Kernel command line type" if CMDLINE != ""
1752 default CMDLINE_FROM_BOOTLOADER
1754 config CMDLINE_FROM_BOOTLOADER
1755 bool "Use bootloader kernel arguments if available"
1757 Uses the command-line options passed by the boot loader. If
1758 the boot loader doesn't provide any, the default kernel command
1759 string provided in CMDLINE will be used.
1761 config CMDLINE_EXTEND
1762 bool "Extend bootloader kernel arguments"
1764 The command-line arguments provided by the boot loader will be
1765 appended to the default kernel command string.
1767 config CMDLINE_FORCE
1768 bool "Always use the default kernel command string"
1770 Always use the default kernel command string, even if the boot
1771 loader passes other arguments to the kernel.
1772 This is useful if you cannot or don't want to change the
1773 command-line options your boot loader passes to the kernel.
1777 bool "Kernel Execute-In-Place from ROM"
1778 depends on !ZBOOT_ROM
1780 Execute-In-Place allows the kernel to run from non-volatile storage
1781 directly addressable by the CPU, such as NOR flash. This saves RAM
1782 space since the text section of the kernel is not loaded from flash
1783 to RAM. Read-write sections, such as the data section and stack,
1784 are still copied to RAM. The XIP kernel is not compressed since
1785 it has to run directly from flash, so it will take more space to
1786 store it. The flash address used to link the kernel object files,
1787 and for storing it, is configuration dependent. Therefore, if you
1788 say Y here, you must know the proper physical address where to
1789 store the kernel image depending on your own flash memory usage.
1791 Also note that the make target becomes "make xipImage" rather than
1792 "make zImage" or "make Image". The final kernel binary to put in
1793 ROM memory will be arch/arm/boot/xipImage.
1797 config XIP_PHYS_ADDR
1798 hex "XIP Kernel Physical Location"
1799 depends on XIP_KERNEL
1800 default "0x00080000"
1802 This is the physical address in your flash memory the kernel will
1803 be linked for and stored to. This address is dependent on your
1807 bool "Kexec system call (EXPERIMENTAL)"
1808 depends on EXPERIMENTAL
1810 kexec is a system call that implements the ability to shutdown your
1811 current kernel, and to start another kernel. It is like a reboot
1812 but it is independent of the system firmware. And like a reboot
1813 you can start any kernel with it, not just Linux.
1815 It is an ongoing process to be certain the hardware in a machine
1816 is properly shutdown, so do not be surprised if this code does not
1817 initially work for you. It may help to enable device hotplugging
1821 bool "Export atags in procfs"
1825 Should the atags used to boot the kernel be exported in an "atags"
1826 file in procfs. Useful with kexec.
1829 bool "Build kdump crash kernel (EXPERIMENTAL)"
1830 depends on EXPERIMENTAL
1832 Generate crash dump after being started by kexec. This should
1833 be normally only set in special crash dump kernels which are
1834 loaded in the main kernel with kexec-tools into a specially
1835 reserved region and then later executed after a crash by
1836 kdump/kexec. The crash dump kernel must be compiled to a
1837 memory address not used by the main kernel
1839 For more details see Documentation/kdump/kdump.txt
1841 config AUTO_ZRELADDR
1842 bool "Auto calculation of the decompressed kernel image address"
1843 depends on !ZBOOT_ROM && !ARCH_U300
1845 ZRELADDR is the physical address where the decompressed kernel
1846 image will be placed. If AUTO_ZRELADDR is selected, the address
1847 will be determined at run-time by masking the current IP with
1848 0xf8000000. This assumes the zImage being placed in the first 128MB
1849 from start of memory.
1853 menu "CPU Power Management"
1857 source "drivers/cpufreq/Kconfig"
1860 tristate "CPUfreq driver for i.MX CPUs"
1861 depends on ARCH_MXC && CPU_FREQ
1863 This enables the CPUfreq driver for i.MX CPUs.
1865 config CPU_FREQ_SA1100
1868 config CPU_FREQ_SA1110
1871 config CPU_FREQ_INTEGRATOR
1872 tristate "CPUfreq driver for ARM Integrator CPUs"
1873 depends on ARCH_INTEGRATOR && CPU_FREQ
1876 This enables the CPUfreq driver for ARM Integrator CPUs.
1878 For details, take a look at <file:Documentation/cpu-freq>.
1884 depends on CPU_FREQ && ARCH_PXA && PXA25x
1886 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1888 config CPU_FREQ_S3C64XX
1889 bool "CPUfreq support for Samsung S3C64XX CPUs"
1890 depends on CPU_FREQ && CPU_S3C6410
1895 Internal configuration node for common cpufreq on Samsung SoC
1897 config CPU_FREQ_S3C24XX
1898 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1899 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1902 This enables the CPUfreq driver for the Samsung S3C24XX family
1905 For details, take a look at <file:Documentation/cpu-freq>.
1909 config CPU_FREQ_S3C24XX_PLL
1910 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1911 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1913 Compile in support for changing the PLL frequency from the
1914 S3C24XX series CPUfreq driver. The PLL takes time to settle
1915 after a frequency change, so by default it is not enabled.
1917 This also means that the PLL tables for the selected CPU(s) will
1918 be built which may increase the size of the kernel image.
1920 config CPU_FREQ_S3C24XX_DEBUG
1921 bool "Debug CPUfreq Samsung driver core"
1922 depends on CPU_FREQ_S3C24XX
1924 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1926 config CPU_FREQ_S3C24XX_IODEBUG
1927 bool "Debug CPUfreq Samsung driver IO timing"
1928 depends on CPU_FREQ_S3C24XX
1930 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1932 config CPU_FREQ_S3C24XX_DEBUGFS
1933 bool "Export debugfs for CPUFreq"
1934 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1936 Export status information via debugfs.
1940 source "drivers/cpuidle/Kconfig"
1944 menu "Floating point emulation"
1946 comment "At least one emulation must be selected"
1949 bool "NWFPE math emulation"
1950 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1952 Say Y to include the NWFPE floating point emulator in the kernel.
1953 This is necessary to run most binaries. Linux does not currently
1954 support floating point hardware so you need to say Y here even if
1955 your machine has an FPA or floating point co-processor podule.
1957 You may say N here if you are going to load the Acorn FPEmulator
1958 early in the bootup.
1961 bool "Support extended precision"
1962 depends on FPE_NWFPE
1964 Say Y to include 80-bit support in the kernel floating-point
1965 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1966 Note that gcc does not generate 80-bit operations by default,
1967 so in most cases this option only enlarges the size of the
1968 floating point emulator without any good reason.
1970 You almost surely want to say N here.
1973 bool "FastFPE math emulation (EXPERIMENTAL)"
1974 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1976 Say Y here to include the FAST floating point emulator in the kernel.
1977 This is an experimental much faster emulator which now also has full
1978 precision for the mantissa. It does not support any exceptions.
1979 It is very simple, and approximately 3-6 times faster than NWFPE.
1981 It should be sufficient for most programs. It may be not suitable
1982 for scientific calculations, but you have to check this for yourself.
1983 If you do not feel you need a faster FP emulation you should better
1987 bool "VFP-format floating point maths"
1988 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1990 Say Y to include VFP support code in the kernel. This is needed
1991 if your hardware includes a VFP unit.
1993 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1994 release notes and additional status information.
1996 Say N if your target does not have VFP hardware.
2004 bool "Advanced SIMD (NEON) Extension support"
2005 depends on VFPv3 && CPU_V7
2007 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2012 menu "Userspace binary formats"
2014 source "fs/Kconfig.binfmt"
2017 tristate "RISC OS personality"
2020 Say Y here to include the kernel code necessary if you want to run
2021 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2022 experimental; if this sounds frightening, say N and sleep in peace.
2023 You can also say M here to compile this support as a module (which
2024 will be called arthur).
2028 menu "Power management options"
2030 source "kernel/power/Kconfig"
2032 config ARCH_SUSPEND_POSSIBLE
2033 depends on !ARCH_S5P64X0 && !ARCH_S5P6442
2034 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2035 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2040 source "net/Kconfig"
2042 source "drivers/Kconfig"
2046 source "arch/arm/Kconfig.debug"
2048 source "security/Kconfig"
2050 source "crypto/Kconfig"
2052 source "lib/Kconfig"