4 select HAVE_DMA_API_DEBUG
5 select HAVE_IDE if PCI || ISA || PCMCIA
7 select HAVE_DMA_CONTIGUOUS if MMU
10 select SYS_SUPPORTS_APM_EMULATION
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select HAVE_GENERIC_DMA_COHERENT
21 select HAVE_KERNEL_GZIP
22 select HAVE_KERNEL_LZO
23 select HAVE_KERNEL_LZMA
25 select HAVE_PERF_EVENTS
26 select PERF_USE_VMALLOC
27 select HAVE_REGS_AND_STACK_ACCESS_API
28 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_GENERIC_HARDIRQS
31 select HAVE_SPARSE_IRQ
32 select GENERIC_IRQ_SHOW
33 select CPU_PM if (SUSPEND || CPU_IDLE)
35 The ARM series is a line of low-power-consumption RISC chip designs
36 licensed by ARM Ltd and targeted at embedded applications and
37 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
38 manufactured, but legacy ARM-based PC hardware remains popular in
39 Europe. There is an ARM Linux project with a web page at
40 <http://www.arm.linux.org.uk/>.
42 config ARM_HAS_SG_CHAIN
45 config NEED_SG_DMA_LENGTH
48 config ARM_DMA_USE_IOMMU
49 select NEED_SG_DMA_LENGTH
50 select ARM_HAS_SG_CHAIN
59 config SYS_SUPPORTS_APM_EMULATION
62 config HAVE_SCHED_CLOCK
68 config ARCH_USES_GETTIMEOFFSET
72 config GENERIC_CLOCKEVENTS
75 config GENERIC_CLOCKEVENTS_BROADCAST
77 depends on GENERIC_CLOCKEVENTS
86 select GENERIC_ALLOCATOR
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
115 MicroChannel Architecture is found in some IBM PS/2 machines and
116 laptops. It is a bus system similar to PCI or ISA. See
117 <file:Documentation/mca.txt> (and especially the web page given
118 there) before attempting to build an MCA bus kernel.
120 config STACKTRACE_SUPPORT
124 config HAVE_LATENCYTOP_SUPPORT
129 config LOCKDEP_SUPPORT
133 config TRACE_IRQFLAGS_SUPPORT
137 config HARDIRQS_SW_RESEND
141 config GENERIC_IRQ_PROBE
145 config GENERIC_LOCKBREAK
148 depends on SMP && PREEMPT
150 config RWSEM_GENERIC_SPINLOCK
154 config RWSEM_XCHGADD_ALGORITHM
157 config ARCH_HAS_ILOG2_U32
160 config ARCH_HAS_ILOG2_U64
163 config ARCH_HAS_CPUFREQ
166 Internal node to signify that the ARCH has CPUFREQ support
167 and that the relevant menu configurations are displayed for
170 config ARCH_HAS_CPU_IDLE_WAIT
173 config GENERIC_HWEIGHT
177 config GENERIC_CALIBRATE_DELAY
181 config ARCH_MAY_HAVE_PC_FDC
187 config NEED_DMA_MAP_STATE
190 config ARCH_HAS_DMA_SET_COHERENT_MASK
193 config GENERIC_ISA_DMA
204 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
205 default DRAM_BASE if REMAP_VECTORS_TO_RAM
208 The base address of exception vectors.
210 config ARM_PATCH_PHYS_VIRT
211 bool "Patch physical to virtual translations at runtime" if EMBEDDED
213 depends on !XIP_KERNEL && MMU
214 depends on !ARCH_REALVIEW || !SPARSEMEM
216 Patch phys-to-virt and virt-to-phys translation functions at
217 boot and module load time according to the position of the
218 kernel in system memory.
220 This can only be used with non-XIP MMU kernels where the base
221 of physical memory is at a 16MB boundary.
223 Only disable this option if you know that you do not require
224 this feature (eg, building a kernel for a single machine) and
225 you need to shrink the kernel to the minimal size.
227 config NEED_MACH_MEMORY_H
230 Select this when mach/memory.h is required to provide special
231 definitions for this platform. The need for mach/memory.h should
232 be avoided when possible.
235 hex "Physical address of main memory" if MMU
236 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
237 default DRAM_BASE if !MMU
239 Please provide the physical address corresponding to the
240 location of main memory in your system.
246 source "init/Kconfig"
248 source "kernel/Kconfig.freezer"
253 bool "MMU-based Paged Memory Management Support"
256 Select if you want MMU-based virtualised addressing space
257 support by paged memory management. If unsure, say 'Y'.
260 # The "ARM system type" choice list is ordered alphabetically by option
261 # text. Please add new entries in the option alphabetic order.
264 prompt "ARM system type"
265 default ARCH_VERSATILE
267 config ARCH_INTEGRATOR
268 bool "ARM Ltd. Integrator family"
270 select ARCH_HAS_CPUFREQ
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select PLAT_VERSATILE
276 select PLAT_VERSATILE_FPGA_IRQ
277 select NEED_MACH_MEMORY_H
279 Support for ARM's Integrator platform.
282 bool "ARM Ltd. RealView family"
285 select HAVE_MACH_CLKDEV
287 select GENERIC_CLOCKEVENTS
288 select ARCH_WANT_OPTIONAL_GPIOLIB
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
291 select ARM_TIMER_SP804
292 select GPIO_PL061 if GPIOLIB
293 select NEED_MACH_MEMORY_H
295 This enables support for ARM Ltd RealView boards.
297 config ARCH_VERSATILE
298 bool "ARM Ltd. Versatile family"
302 select HAVE_MACH_CLKDEV
304 select GENERIC_CLOCKEVENTS
305 select ARCH_WANT_OPTIONAL_GPIOLIB
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
308 select PLAT_VERSATILE_FPGA_IRQ
309 select ARM_TIMER_SP804
311 This enables support for ARM Ltd Versatile board.
314 bool "ARM Ltd. Versatile Express family"
315 select ARCH_WANT_OPTIONAL_GPIOLIB
317 select ARM_TIMER_SP804
319 select HAVE_MACH_CLKDEV
320 select GENERIC_CLOCKEVENTS
322 select HAVE_PATA_PLATFORM
324 select PLAT_VERSATILE
325 select PLAT_VERSATILE_CLCD
327 This enables support for the ARM Ltd Versatile Express boards.
331 select ARCH_REQUIRE_GPIOLIB
335 This enables support for systems based on the Atmel AT91RM9200,
336 AT91SAM9 and AT91CAP9 processors.
339 bool "Broadcom BCMRING"
343 select ARM_TIMER_SP804
345 select GENERIC_CLOCKEVENTS
346 select ARCH_WANT_OPTIONAL_GPIOLIB
348 Support for Broadcom's BCMRing platform.
351 bool "Calxeda Highbank-based"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
355 select ARM_TIMER_SP804
358 select GENERIC_CLOCKEVENTS
362 Support for the Calxeda Highbank SoC based boards.
365 bool "Cirrus Logic CLPS711x/EP721x-based"
367 select ARCH_USES_GETTIMEOFFSET
368 select NEED_MACH_MEMORY_H
370 Support for Cirrus Logic 711x/721x based boards.
373 bool "Cavium Networks CNS3XXX family"
375 select GENERIC_CLOCKEVENTS
377 select MIGHT_HAVE_PCI
378 select PCI_DOMAINS if PCI
380 Support for Cavium Networks CNS3XXX platform.
383 bool "Cortina Systems Gemini"
385 select ARCH_REQUIRE_GPIOLIB
386 select ARCH_USES_GETTIMEOFFSET
388 Support for the Cortina Systems Gemini family SoCs
391 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
394 select GENERIC_CLOCKEVENTS
396 select GENERIC_IRQ_CHIP
400 Support for CSR SiRFSoC ARM Cortex A9 Platform
407 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 select ARCH_REQUIRE_GPIOLIB
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_MEMORY_H
436 Support for systems based on the DC21285 companion chip
437 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
440 bool "Freescale MXC/iMX-based"
441 select GENERIC_CLOCKEVENTS
442 select ARCH_REQUIRE_GPIOLIB
445 select GENERIC_IRQ_CHIP
446 select HAVE_SCHED_CLOCK
447 select MULTI_IRQ_HANDLER
449 Support for Freescale MXC/iMX-based family of processors
452 bool "Freescale MXS-based"
453 select GENERIC_CLOCKEVENTS
454 select ARCH_REQUIRE_GPIOLIB
458 Support for Freescale MXS-based family of processors
461 bool "Hilscher NetX based"
465 select GENERIC_CLOCKEVENTS
467 This enables support for systems based on the Hilscher NetX Soc
470 bool "Hynix HMS720x-based"
473 select ARCH_USES_GETTIMEOFFSET
475 This enables support for systems based on the Hynix HMS720x
483 select ARCH_SUPPORTS_MSI
485 select NEED_MACH_MEMORY_H
487 Support for Intel's IOP13XX (XScale) family of processors.
495 select ARCH_REQUIRE_GPIOLIB
497 Support for Intel's 80219 and IOP32X (XScale) family of
506 select ARCH_REQUIRE_GPIOLIB
508 Support for Intel's IOP33X (XScale) family of processors.
515 select ARCH_USES_GETTIMEOFFSET
516 select NEED_MACH_MEMORY_H
518 Support for Intel's IXP23xx (XScale) family of processors.
521 bool "IXP2400/2800-based"
525 select ARCH_USES_GETTIMEOFFSET
526 select NEED_MACH_MEMORY_H
528 Support for Intel's IXP2400/2800 (XScale) family of processors.
533 select ARCH_HAS_DMA_SET_COHERENT_MASK
536 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
538 select HAVE_SCHED_CLOCK
539 select MIGHT_HAVE_PCI
540 select DMABOUNCE if PCI
542 Support for Intel's IXP4XX (XScale) family of processors.
548 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 Support for the Marvell Dove SoC 88AP510
555 bool "Marvell Kirkwood"
559 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
563 Support for the following Marvell Kirkwood series SoCs:
564 88F6180, 88F6192 and 88F6281.
570 select ARCH_REQUIRE_GPIOLIB
573 select USB_ARCH_HAS_OHCI
575 select GENERIC_CLOCKEVENTS
577 Support for the NXP LPC32XX family of processors
580 bool "Marvell MV78xx0"
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
587 Support for the following Marvell MV78xx0 series SoCs:
595 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
599 Support for the following Marvell Orion 5x series SoCs:
600 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
601 Orion-2 (5281), Orion-1-90 (6183).
604 bool "Marvell PXA168/910/MMP2"
606 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
609 select HAVE_SCHED_CLOCK
613 select GENERIC_ALLOCATOR
615 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
618 bool "Micrel/Kendin KS8695"
620 select ARCH_REQUIRE_GPIOLIB
621 select ARCH_USES_GETTIMEOFFSET
622 select NEED_MACH_MEMORY_H
624 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
625 System-on-Chip devices.
628 bool "Nuvoton W90X900 CPU"
630 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
635 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
636 At present, the w90x900 has been renamed nuc900, regarding
637 the ARM series product line, you can login the following
638 link address to know more.
640 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
641 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
647 select GENERIC_CLOCKEVENTS
650 select HAVE_SCHED_CLOCK
651 select ARCH_HAS_CPUFREQ
653 This enables support for NVIDIA Tegra based systems (Tegra APX,
654 Tegra 6xx and Tegra 2 series).
656 config ARCH_PICOXCELL
657 bool "Picochip picoXcell"
658 select ARCH_REQUIRE_GPIOLIB
659 select ARM_PATCH_PHYS_VIRT
663 select GENERIC_CLOCKEVENTS
665 select HAVE_SCHED_CLOCK
670 This enables support for systems based on the Picochip picoXcell
671 family of Femtocell devices. The picoxcell support requires device tree
675 bool "Philips Nexperia PNX4008 Mobile"
678 select ARCH_USES_GETTIMEOFFSET
680 This enables support for Philips PNX4008 mobile platform.
683 bool "PXA2xx/PXA3xx-based"
686 select ARCH_HAS_CPUFREQ
689 select ARCH_REQUIRE_GPIOLIB
690 select GENERIC_CLOCKEVENTS
691 select HAVE_SCHED_CLOCK
696 select MULTI_IRQ_HANDLER
697 select ARM_CPU_SUSPEND if PM
700 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
705 select GENERIC_CLOCKEVENTS
706 select ARCH_REQUIRE_GPIOLIB
709 Support for Qualcomm MSM/QSD based systems. This runs on the
710 apps processor of the MSM/QSD and depends on a shared memory
711 interface to the modem processor which runs the baseband
712 stack and controls some vital subsystems
713 (clock and power control, etc).
716 bool "Renesas SH-Mobile / R-Mobile"
719 select HAVE_MACH_CLKDEV
720 select GENERIC_CLOCKEVENTS
723 select MULTI_IRQ_HANDLER
724 select PM_GENERIC_DOMAINS if PM
725 select NEED_MACH_MEMORY_H
727 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
734 select ARCH_MAY_HAVE_PC_FDC
735 select HAVE_PATA_PLATFORM
738 select ARCH_SPARSEMEM_ENABLE
739 select ARCH_USES_GETTIMEOFFSET
741 select NEED_MACH_MEMORY_H
743 On the Acorn Risc-PC, Linux can support the internal IDE disk and
744 CD-ROM interface, serial and parallel port, and the floppy drive.
751 select ARCH_SPARSEMEM_ENABLE
753 select ARCH_HAS_CPUFREQ
755 select GENERIC_CLOCKEVENTS
757 select HAVE_SCHED_CLOCK
759 select ARCH_REQUIRE_GPIOLIB
761 select NEED_MACH_MEMORY_H
763 Support for StrongARM 11x0 based boards.
766 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
768 select ARCH_HAS_CPUFREQ
771 select ARCH_USES_GETTIMEOFFSET
772 select HAVE_S3C2410_I2C if I2C
774 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
775 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
776 the Samsung SMDK2410 development board (and derivatives).
778 Note, the S3C2416 and the S3C2450 are so close that they even share
779 the same SoC ID code. This means that there is no separate machine
780 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
783 bool "Samsung S3C64XX"
791 select ARCH_USES_GETTIMEOFFSET
792 select ARCH_HAS_CPUFREQ
793 select ARCH_REQUIRE_GPIOLIB
794 select SAMSUNG_CLKSRC
795 select SAMSUNG_IRQ_VIC_TIMER
796 select S3C_GPIO_TRACK
798 select USB_ARCH_HAS_OHCI
799 select SAMSUNG_GPIOLIB_4BIT
800 select HAVE_S3C2410_I2C if I2C
801 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 Samsung S3C64XX series based systems
806 bool "Samsung S5P6440 S5P6450"
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select GENERIC_CLOCKEVENTS
814 select HAVE_SCHED_CLOCK
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
818 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
822 bool "Samsung S5PC100"
827 select ARM_L1_CACHE_SHIFT_6
828 select ARCH_USES_GETTIMEOFFSET
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C_RTC if RTC_CLASS
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 Samsung S5PC100 series based systems
836 bool "Samsung S5PV210/S5PC110"
838 select ARCH_SPARSEMEM_ENABLE
839 select ARCH_HAS_HOLES_MEMORYMODEL
844 select ARM_L1_CACHE_SHIFT_6
845 select ARCH_HAS_CPUFREQ
846 select GENERIC_CLOCKEVENTS
847 select HAVE_SCHED_CLOCK
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C_RTC if RTC_CLASS
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
851 select NEED_MACH_MEMORY_H
853 Samsung S5PV210/S5PC110 series based systems
856 bool "SAMSUNG EXYNOS"
858 select ARCH_SPARSEMEM_ENABLE
859 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_HAS_CPUFREQ
864 select GENERIC_CLOCKEVENTS
865 select HAVE_S3C_RTC if RTC_CLASS
866 select HAVE_S3C2410_I2C if I2C
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 select NEED_MACH_MEMORY_H
870 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
879 select ARCH_USES_GETTIMEOFFSET
880 select NEED_MACH_MEMORY_H
882 Support for the StrongARM based Digital DNARD machine, also known
883 as "Shark" (<http://www.shark-linux.de/shark.html>).
886 bool "Telechips TCC ARM926-based systems"
891 select GENERIC_CLOCKEVENTS
893 Support for Telechips TCC ARM926-based systems.
896 bool "ST-Ericsson U300 Series"
900 select HAVE_SCHED_CLOCK
903 select ARM_PATCH_PHYS_VIRT
905 select GENERIC_CLOCKEVENTS
907 select HAVE_MACH_CLKDEV
909 select ARCH_REQUIRE_GPIOLIB
910 select NEED_MACH_MEMORY_H
912 Support for ST-Ericsson U300 series mobile platforms.
915 bool "ST-Ericsson U8500 Series"
918 select GENERIC_CLOCKEVENTS
920 select ARCH_REQUIRE_GPIOLIB
921 select ARCH_HAS_CPUFREQ
923 Support for ST-Ericsson's Ux500 architecture
926 bool "STMicroelectronics Nomadik"
931 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
934 Support for the Nomadik platform by ST-Ericsson
938 select GENERIC_CLOCKEVENTS
939 select ARCH_REQUIRE_GPIOLIB
943 select GENERIC_ALLOCATOR
944 select GENERIC_IRQ_CHIP
945 select ARCH_HAS_HOLES_MEMORYMODEL
947 Support for TI's DaVinci platform.
952 select ARCH_REQUIRE_GPIOLIB
953 select ARCH_HAS_CPUFREQ
955 select GENERIC_CLOCKEVENTS
956 select HAVE_SCHED_CLOCK
957 select ARCH_HAS_HOLES_MEMORYMODEL
959 Support for TI's OMAP platform (OMAP1/2/3/4).
964 select ARCH_REQUIRE_GPIOLIB
967 select GENERIC_CLOCKEVENTS
970 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
973 bool "VIA/WonderMedia 85xx"
976 select ARCH_HAS_CPUFREQ
977 select GENERIC_CLOCKEVENTS
978 select ARCH_REQUIRE_GPIOLIB
981 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
984 bool "Xilinx Zynq ARM Cortex A9 Platform"
986 select GENERIC_CLOCKEVENTS
993 Support for Xilinx Zynq ARM Cortex A9 Platform
997 # This is sorted alphabetically by mach-* pathname. However, plat-*
998 # Kconfigs may be included either alphabetically (according to the
999 # plat- suffix) or along side the corresponding mach-* source.
1001 source "arch/arm/mach-at91/Kconfig"
1003 source "arch/arm/mach-bcmring/Kconfig"
1005 source "arch/arm/mach-clps711x/Kconfig"
1007 source "arch/arm/mach-cns3xxx/Kconfig"
1009 source "arch/arm/mach-davinci/Kconfig"
1011 source "arch/arm/mach-dove/Kconfig"
1013 source "arch/arm/mach-ep93xx/Kconfig"
1015 source "arch/arm/mach-footbridge/Kconfig"
1017 source "arch/arm/mach-gemini/Kconfig"
1019 source "arch/arm/mach-h720x/Kconfig"
1021 source "arch/arm/mach-integrator/Kconfig"
1023 source "arch/arm/mach-iop32x/Kconfig"
1025 source "arch/arm/mach-iop33x/Kconfig"
1027 source "arch/arm/mach-iop13xx/Kconfig"
1029 source "arch/arm/mach-ixp4xx/Kconfig"
1031 source "arch/arm/mach-ixp2000/Kconfig"
1033 source "arch/arm/mach-ixp23xx/Kconfig"
1035 source "arch/arm/mach-kirkwood/Kconfig"
1037 source "arch/arm/mach-ks8695/Kconfig"
1039 source "arch/arm/mach-lpc32xx/Kconfig"
1041 source "arch/arm/mach-msm/Kconfig"
1043 source "arch/arm/mach-mv78xx0/Kconfig"
1045 source "arch/arm/plat-mxc/Kconfig"
1047 source "arch/arm/mach-mxs/Kconfig"
1049 source "arch/arm/mach-netx/Kconfig"
1051 source "arch/arm/mach-nomadik/Kconfig"
1052 source "arch/arm/plat-nomadik/Kconfig"
1054 source "arch/arm/plat-omap/Kconfig"
1056 source "arch/arm/mach-omap1/Kconfig"
1058 source "arch/arm/mach-omap2/Kconfig"
1060 source "arch/arm/mach-orion5x/Kconfig"
1062 source "arch/arm/mach-pxa/Kconfig"
1063 source "arch/arm/plat-pxa/Kconfig"
1065 source "arch/arm/mach-mmp/Kconfig"
1067 source "arch/arm/mach-realview/Kconfig"
1069 source "arch/arm/mach-sa1100/Kconfig"
1071 source "arch/arm/plat-samsung/Kconfig"
1072 source "arch/arm/plat-s3c24xx/Kconfig"
1073 source "arch/arm/plat-s5p/Kconfig"
1075 source "arch/arm/plat-spear/Kconfig"
1077 source "arch/arm/plat-tcc/Kconfig"
1080 source "arch/arm/mach-s3c2410/Kconfig"
1081 source "arch/arm/mach-s3c2412/Kconfig"
1082 source "arch/arm/mach-s3c2416/Kconfig"
1083 source "arch/arm/mach-s3c2440/Kconfig"
1084 source "arch/arm/mach-s3c2443/Kconfig"
1088 source "arch/arm/mach-s3c64xx/Kconfig"
1091 source "arch/arm/mach-s5p64x0/Kconfig"
1093 source "arch/arm/mach-s5pc100/Kconfig"
1095 source "arch/arm/mach-s5pv210/Kconfig"
1097 source "arch/arm/mach-exynos/Kconfig"
1099 source "arch/arm/mach-shmobile/Kconfig"
1101 source "arch/arm/mach-tegra/Kconfig"
1103 source "arch/arm/mach-u300/Kconfig"
1105 source "arch/arm/mach-ux500/Kconfig"
1107 source "arch/arm/mach-versatile/Kconfig"
1109 source "arch/arm/mach-vexpress/Kconfig"
1110 source "arch/arm/plat-versatile/Kconfig"
1112 source "arch/arm/mach-vt8500/Kconfig"
1114 source "arch/arm/mach-w90x900/Kconfig"
1116 # Definitions to make life easier
1122 select GENERIC_CLOCKEVENTS
1123 select HAVE_SCHED_CLOCK
1128 select GENERIC_IRQ_CHIP
1129 select HAVE_SCHED_CLOCK
1134 config PLAT_VERSATILE
1137 config ARM_TIMER_SP804
1141 source arch/arm/mm/Kconfig
1144 bool "Enable iWMMXt support"
1145 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1146 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1148 Enable support for iWMMXt context switching at run time if
1149 running on a CPU that supports it.
1151 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1154 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1158 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1159 (!ARCH_OMAP3 || OMAP3_EMU)
1163 config MULTI_IRQ_HANDLER
1166 Allow each machine to specify it's own IRQ handler at run time.
1169 source "arch/arm/Kconfig-nommu"
1172 config ARM_ERRATA_326103
1173 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1176 Executing a SWP instruction to read-only memory does not set bit 11
1177 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1178 treat the access as a read, preventing a COW from occurring and
1179 causing the faulting task to livelock.
1181 config ARM_ERRATA_411920
1182 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1183 depends on CPU_V6 || CPU_V6K
1185 Invalidation of the Instruction Cache operation can
1186 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1187 It does not affect the MPCore. This option enables the ARM Ltd.
1188 recommended workaround.
1190 config ARM_ERRATA_430973
1191 bool "ARM errata: Stale prediction on replaced interworking branch"
1194 This option enables the workaround for the 430973 Cortex-A8
1195 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1196 interworking branch is replaced with another code sequence at the
1197 same virtual address, whether due to self-modifying code or virtual
1198 to physical address re-mapping, Cortex-A8 does not recover from the
1199 stale interworking branch prediction. This results in Cortex-A8
1200 executing the new code sequence in the incorrect ARM or Thumb state.
1201 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1202 and also flushes the branch target cache at every context switch.
1203 Note that setting specific bits in the ACTLR register may not be
1204 available in non-secure mode.
1206 config ARM_ERRATA_458693
1207 bool "ARM errata: Processor deadlock when a false hazard is created"
1210 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1211 erratum. For very specific sequences of memory operations, it is
1212 possible for a hazard condition intended for a cache line to instead
1213 be incorrectly associated with a different cache line. This false
1214 hazard might then cause a processor deadlock. The workaround enables
1215 the L1 caching of the NEON accesses and disables the PLD instruction
1216 in the ACTLR register. Note that setting specific bits in the ACTLR
1217 register may not be available in non-secure mode.
1219 config ARM_ERRATA_460075
1220 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1223 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1224 erratum. Any asynchronous access to the L2 cache may encounter a
1225 situation in which recent store transactions to the L2 cache are lost
1226 and overwritten with stale memory contents from external memory. The
1227 workaround disables the write-allocate mode for the L2 cache via the
1228 ACTLR register. Note that setting specific bits in the ACTLR register
1229 may not be available in non-secure mode.
1231 config ARM_ERRATA_742230
1232 bool "ARM errata: DMB operation may be faulty"
1233 depends on CPU_V7 && SMP
1235 This option enables the workaround for the 742230 Cortex-A9
1236 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1237 between two write operations may not ensure the correct visibility
1238 ordering of the two writes. This workaround sets a specific bit in
1239 the diagnostic register of the Cortex-A9 which causes the DMB
1240 instruction to behave as a DSB, ensuring the correct behaviour of
1243 config ARM_ERRATA_742231
1244 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1245 depends on CPU_V7 && SMP
1247 This option enables the workaround for the 742231 Cortex-A9
1248 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1249 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1250 accessing some data located in the same cache line, may get corrupted
1251 data due to bad handling of the address hazard when the line gets
1252 replaced from one of the CPUs at the same time as another CPU is
1253 accessing it. This workaround sets specific bits in the diagnostic
1254 register of the Cortex-A9 which reduces the linefill issuing
1255 capabilities of the processor.
1257 config PL310_ERRATA_588369
1258 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1259 depends on CACHE_L2X0
1261 The PL310 L2 cache controller implements three types of Clean &
1262 Invalidate maintenance operations: by Physical Address
1263 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1264 They are architecturally defined to behave as the execution of a
1265 clean operation followed immediately by an invalidate operation,
1266 both performing to the same memory location. This functionality
1267 is not correctly implemented in PL310 as clean lines are not
1268 invalidated as a result of these operations.
1270 config ARM_ERRATA_720789
1271 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1274 This option enables the workaround for the 720789 Cortex-A9 (prior to
1275 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1276 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1277 As a consequence of this erratum, some TLB entries which should be
1278 invalidated are not, resulting in an incoherency in the system page
1279 tables. The workaround changes the TLB flushing routines to invalidate
1280 entries regardless of the ASID.
1282 config PL310_ERRATA_727915
1283 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1284 depends on CACHE_L2X0
1286 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1287 operation (offset 0x7FC). This operation runs in background so that
1288 PL310 can handle normal accesses while it is in progress. Under very
1289 rare circumstances, due to this erratum, write data can be lost when
1290 PL310 treats a cacheable write transaction during a Clean &
1291 Invalidate by Way operation.
1293 config ARM_ERRATA_743622
1294 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1297 This option enables the workaround for the 743622 Cortex-A9
1298 (r2p*) erratum. Under very rare conditions, a faulty
1299 optimisation in the Cortex-A9 Store Buffer may lead to data
1300 corruption. This workaround sets a specific bit in the diagnostic
1301 register of the Cortex-A9 which disables the Store Buffer
1302 optimisation, preventing the defect from occurring. This has no
1303 visible impact on the overall performance or power consumption of the
1306 config ARM_ERRATA_751472
1307 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1310 This option enables the workaround for the 751472 Cortex-A9 (prior
1311 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1312 completion of a following broadcasted operation if the second
1313 operation is received by a CPU before the ICIALLUIS has completed,
1314 potentially leading to corrupted entries in the cache or TLB.
1316 config PL310_ERRATA_753970
1317 bool "PL310 errata: cache sync operation may be faulty"
1318 depends on CACHE_PL310
1320 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1322 Under some condition the effect of cache sync operation on
1323 the store buffer still remains when the operation completes.
1324 This means that the store buffer is always asked to drain and
1325 this prevents it from merging any further writes. The workaround
1326 is to replace the normal offset of cache sync operation (0x730)
1327 by another offset targeting an unmapped PL310 register 0x740.
1328 This has the same effect as the cache sync operation: store buffer
1329 drain and waiting for all buffers empty.
1331 config ARM_ERRATA_754322
1332 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1335 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1336 r3p*) erratum. A speculative memory access may cause a page table walk
1337 which starts prior to an ASID switch but completes afterwards. This
1338 can populate the micro-TLB with a stale entry which may be hit with
1339 the new ASID. This workaround places two dsb instructions in the mm
1340 switching code so that no page table walks can cross the ASID switch.
1342 config ARM_ERRATA_754327
1343 bool "ARM errata: no automatic Store Buffer drain"
1344 depends on CPU_V7 && SMP
1346 This option enables the workaround for the 754327 Cortex-A9 (prior to
1347 r2p0) erratum. The Store Buffer does not have any automatic draining
1348 mechanism and therefore a livelock may occur if an external agent
1349 continuously polls a memory location waiting to observe an update.
1350 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1351 written polling loops from denying visibility of updates to memory.
1353 config ARM_ERRATA_364296
1354 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1355 depends on CPU_V6 && !SMP
1357 This options enables the workaround for the 364296 ARM1136
1358 r0p2 erratum (possible cache data corruption with
1359 hit-under-miss enabled). It sets the undocumented bit 31 in
1360 the auxiliary control register and the FI bit in the control
1361 register, thus disabling hit-under-miss without putting the
1362 processor into full low interrupt latency mode. ARM11MPCore
1365 config ARM_ERRATA_764369
1366 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1367 depends on CPU_V7 && SMP
1369 This option enables the workaround for erratum 764369
1370 affecting Cortex-A9 MPCore with two or more processors (all
1371 current revisions). Under certain timing circumstances, a data
1372 cache line maintenance operation by MVA targeting an Inner
1373 Shareable memory region may fail to proceed up to either the
1374 Point of Coherency or to the Point of Unification of the
1375 system. This workaround adds a DSB instruction before the
1376 relevant cache maintenance functions and sets a specific bit
1377 in the diagnostic control register of the SCU.
1379 config PL310_ERRATA_769419
1380 bool "PL310 errata: no automatic Store Buffer drain"
1381 depends on CACHE_L2X0
1383 On revisions of the PL310 prior to r3p2, the Store Buffer does
1384 not automatically drain. This can cause normal, non-cacheable
1385 writes to be retained when the memory system is idle, leading
1386 to suboptimal I/O performance for drivers using coherent DMA.
1387 This option adds a write barrier to the cpu_idle loop so that,
1388 on systems with an outer cache, the store buffer is drained
1393 source "arch/arm/common/Kconfig"
1403 Find out whether you have ISA slots on your motherboard. ISA is the
1404 name of a bus system, i.e. the way the CPU talks to the other stuff
1405 inside your box. Other bus systems are PCI, EISA, MicroChannel
1406 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1407 newer boards don't support it. If you have ISA, say Y, otherwise N.
1409 # Select ISA DMA controller support
1414 # Select ISA DMA interface
1419 bool "PCI support" if MIGHT_HAVE_PCI
1421 Find out whether you have a PCI motherboard. PCI is the name of a
1422 bus system, i.e. the way the CPU talks to the other stuff inside
1423 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1424 VESA. If you have PCI, say Y, otherwise N.
1430 config PCI_NANOENGINE
1431 bool "BSE nanoEngine PCI support"
1432 depends on SA1100_NANOENGINE
1434 Enable PCI on the BSE nanoEngine board.
1439 # Select the host bridge type
1440 config PCI_HOST_VIA82C505
1442 depends on PCI && ARCH_SHARK
1445 config PCI_HOST_ITE8152
1447 depends on PCI && MACH_ARMCORE
1451 source "drivers/pci/Kconfig"
1453 source "drivers/pcmcia/Kconfig"
1457 menu "Kernel Features"
1459 source "kernel/time/Kconfig"
1462 bool "Symmetric Multi-Processing"
1463 depends on CPU_V6K || CPU_V7
1464 depends on GENERIC_CLOCKEVENTS
1465 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1466 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1467 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1468 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1470 select USE_GENERIC_SMP_HELPERS
1471 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1473 This enables support for systems with more than one CPU. If you have
1474 a system with only one CPU, like most personal computers, say N. If
1475 you have a system with more than one CPU, say Y.
1477 If you say N here, the kernel will run on single and multiprocessor
1478 machines, but will use only one CPU of a multiprocessor machine. If
1479 you say Y here, the kernel will run on many, but not all, single
1480 processor machines. On a single processor machine, the kernel will
1481 run faster if you say N here.
1483 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1484 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1485 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1487 If you don't know what to do here, say N.
1490 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1491 depends on EXPERIMENTAL
1492 depends on SMP && !XIP_KERNEL
1495 SMP kernels contain instructions which fail on non-SMP processors.
1496 Enabling this option allows the kernel to modify itself to make
1497 these instructions safe. Disabling it allows about 1K of space
1500 If you don't know what to do here, say Y.
1502 config ARM_CPU_TOPOLOGY
1503 bool "Support cpu topology definition"
1504 depends on SMP && CPU_V7
1507 Support ARM cpu topology definition. The MPIDR register defines
1508 affinity between processors which is then used to describe the cpu
1509 topology of an ARM System.
1512 bool "Multi-core scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1515 Multi-core scheduler support improves the CPU scheduler's decision
1516 making when dealing with multi-core CPU chips at a cost of slightly
1517 increased overhead in some places. If unsure say N here.
1520 bool "SMT scheduler support"
1521 depends on ARM_CPU_TOPOLOGY
1523 Improves the CPU scheduler's decision making when dealing with
1524 MultiThreading at a cost of slightly increased overhead in some
1525 places. If unsure say N here.
1530 This option enables support for the ARM system coherency unit
1537 This options enables support for the ARM timer and watchdog unit
1540 prompt "Memory split"
1543 Select the desired split between kernel and user memory.
1545 If you are not absolutely sure what you are doing, leave this
1549 bool "3G/1G user/kernel split"
1551 bool "2G/2G user/kernel split"
1553 bool "1G/3G user/kernel split"
1558 default 0x40000000 if VMSPLIT_1G
1559 default 0x80000000 if VMSPLIT_2G
1563 int "Maximum number of CPUs (2-32)"
1569 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1570 depends on SMP && HOTPLUG && EXPERIMENTAL
1572 Say Y here to experiment with turning CPUs off and on. CPUs
1573 can be controlled through /sys/devices/system/cpu.
1576 bool "Use local timer interrupts"
1579 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1581 Enable support for local timers on SMP platforms, rather then the
1582 legacy IPI broadcast method. Local timers allows the system
1583 accounting to be spread across the timer interval, preventing a
1584 "thundering herd" at every timer tick.
1586 source kernel/Kconfig.preempt
1590 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1591 ARCH_S5PV210 || ARCH_EXYNOS4
1592 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1593 default AT91_TIMER_HZ if ARCH_AT91
1594 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1597 config THUMB2_KERNEL
1598 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1599 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1601 select ARM_ASM_UNIFIED
1604 By enabling this option, the kernel will be compiled in
1605 Thumb-2 mode. A compiler/assembler that understand the unified
1606 ARM-Thumb syntax is needed.
1610 config THUMB2_AVOID_R_ARM_THM_JUMP11
1611 bool "Work around buggy Thumb-2 short branch relocations in gas"
1612 depends on THUMB2_KERNEL && MODULES
1615 Various binutils versions can resolve Thumb-2 branches to
1616 locally-defined, preemptible global symbols as short-range "b.n"
1617 branch instructions.
1619 This is a problem, because there's no guarantee the final
1620 destination of the symbol, or any candidate locations for a
1621 trampoline, are within range of the branch. For this reason, the
1622 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1623 relocation in modules at all, and it makes little sense to add
1626 The symptom is that the kernel fails with an "unsupported
1627 relocation" error when loading some modules.
1629 Until fixed tools are available, passing
1630 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1631 code which hits this problem, at the cost of a bit of extra runtime
1632 stack usage in some cases.
1634 The problem is described in more detail at:
1635 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1637 Only Thumb-2 kernels are affected.
1639 Unless you are sure your tools don't have this problem, say Y.
1641 config ARM_ASM_UNIFIED
1645 bool "Use the ARM EABI to compile the kernel"
1647 This option allows for the kernel to be compiled using the latest
1648 ARM ABI (aka EABI). This is only useful if you are using a user
1649 space environment that is also compiled with EABI.
1651 Since there are major incompatibilities between the legacy ABI and
1652 EABI, especially with regard to structure member alignment, this
1653 option also changes the kernel syscall calling convention to
1654 disambiguate both ABIs and allow for backward compatibility support
1655 (selected with CONFIG_OABI_COMPAT).
1657 To use this you need GCC version 4.0.0 or later.
1660 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1661 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1664 This option preserves the old syscall interface along with the
1665 new (ARM EABI) one. It also provides a compatibility layer to
1666 intercept syscalls that have structure arguments which layout
1667 in memory differs between the legacy ABI and the new ARM EABI
1668 (only for non "thumb" binaries). This option adds a tiny
1669 overhead to all syscalls and produces a slightly larger kernel.
1670 If you know you'll be using only pure EABI user space then you
1671 can say N here. If this option is not selected and you attempt
1672 to execute a legacy ABI binary then the result will be
1673 UNPREDICTABLE (in fact it can be predicted that it won't work
1674 at all). If in doubt say Y.
1676 config ARCH_HAS_HOLES_MEMORYMODEL
1679 config ARCH_SPARSEMEM_ENABLE
1682 config ARCH_SPARSEMEM_DEFAULT
1683 def_bool ARCH_SPARSEMEM_ENABLE
1685 config ARCH_SELECT_MEMORY_MODEL
1686 def_bool ARCH_SPARSEMEM_ENABLE
1688 config HAVE_ARCH_PFN_VALID
1689 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1692 bool "High Memory Support"
1695 The address space of ARM processors is only 4 Gigabytes large
1696 and it has to accommodate user address space, kernel address
1697 space as well as some memory mapped IO. That means that, if you
1698 have a large amount of physical memory and/or IO, not all of the
1699 memory can be "permanently mapped" by the kernel. The physical
1700 memory that is not permanently mapped is called "high memory".
1702 Depending on the selected kernel/user memory split, minimum
1703 vmalloc space and actual amount of RAM, you may not need this
1704 option which should result in a slightly faster kernel.
1709 bool "Allocate 2nd-level pagetables from highmem"
1712 config HW_PERF_EVENTS
1713 bool "Enable hardware performance counter support for perf events"
1714 depends on PERF_EVENTS && CPU_HAS_PMU
1717 Enable hardware performance counter support for perf events. If
1718 disabled, perf events will use software events only.
1720 config SYS_SUPPORTS_HUGETLBFS
1722 depends on ARM_LPAE || (!CPU_USE_DOMAINS && !MEMORY_FAILURE)
1724 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1726 depends on SYS_SUPPORTS_HUGETLBFS
1730 config FORCE_MAX_ZONEORDER
1731 int "Maximum zone order" if ARCH_SHMOBILE
1732 range 11 64 if ARCH_SHMOBILE
1733 default "9" if SA1111
1736 The kernel memory allocator divides physically contiguous memory
1737 blocks into "zones", where each zone is a power of two number of
1738 pages. This option selects the largest power of two that the kernel
1739 keeps in the memory allocator. If you need to allocate very large
1740 blocks of physically contiguous memory, then you may need to
1741 increase this value.
1743 This config option is actually maximum order plus one. For example,
1744 a value of 11 means that the largest free memory block is 2^10 pages.
1747 bool "Timer and CPU usage LEDs"
1748 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1749 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1750 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1751 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1752 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1753 ARCH_AT91 || ARCH_DAVINCI || \
1754 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1756 If you say Y here, the LEDs on your machine will be used
1757 to provide useful information about your current system status.
1759 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1760 be able to select which LEDs are active using the options below. If
1761 you are compiling a kernel for the EBSA-110 or the LART however, the
1762 red LED will simply flash regularly to indicate that the system is
1763 still functional. It is safe to say Y here if you have a CATS
1764 system, but the driver will do nothing.
1767 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1768 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1769 || MACH_OMAP_PERSEUS2
1771 depends on !GENERIC_CLOCKEVENTS
1772 default y if ARCH_EBSA110
1774 If you say Y here, one of the system LEDs (the green one on the
1775 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1776 will flash regularly to indicate that the system is still
1777 operational. This is mainly useful to kernel hackers who are
1778 debugging unstable kernels.
1780 The LART uses the same LED for both Timer LED and CPU usage LED
1781 functions. You may choose to use both, but the Timer LED function
1782 will overrule the CPU usage LED.
1785 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1787 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1788 || MACH_OMAP_PERSEUS2
1791 If you say Y here, the red LED will be used to give a good real
1792 time indication of CPU usage, by lighting whenever the idle task
1793 is not currently executing.
1795 The LART uses the same LED for both Timer LED and CPU usage LED
1796 functions. You may choose to use both, but the Timer LED function
1797 will overrule the CPU usage LED.
1799 config ALIGNMENT_TRAP
1800 bool "Enable alignment trap"
1801 depends on CPU_CP15_MMU
1802 default y if !ARCH_EBSA110
1803 select HAVE_PROC_CPU if PROC_FS
1805 ARM processors cannot fetch/store information which is not
1806 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1807 address divisible by 4. On 32-bit ARM processors, these non-aligned
1808 fetch/store instructions will be emulated in software if you say
1809 here, which has a severe performance impact. This is necessary for
1810 correct operation of some network protocols. With an IP-only
1811 configuration it is safe to say N, otherwise say Y.
1813 config UACCESS_WITH_MEMCPY
1814 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1815 depends on MMU && EXPERIMENTAL
1816 default y if CPU_FEROCEON
1818 Implement faster copy_to_user and clear_user methods for CPU
1819 cores where a 8-word STM instruction give significantly higher
1820 memory write throughput than a sequence of individual 32bit stores.
1822 A possible side effect is a slight increase in scheduling latency
1823 between threads sharing the same address space if they invoke
1824 such copy operations with large buffers.
1826 However, if the CPU data cache is using a write-allocate mode,
1827 this option is unlikely to provide any performance gain.
1831 prompt "Enable seccomp to safely compute untrusted bytecode"
1833 This kernel feature is useful for number crunching applications
1834 that may need to compute untrusted bytecode during their
1835 execution. By using pipes or other transports made available to
1836 the process as file descriptors supporting the read/write
1837 syscalls, it's possible to isolate those applications in
1838 their own address space using seccomp. Once seccomp is
1839 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1840 and the task is only allowed to execute a few safe syscalls
1841 defined by each seccomp mode.
1843 config CC_STACKPROTECTOR
1844 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1845 depends on EXPERIMENTAL
1847 This option turns on the -fstack-protector GCC feature. This
1848 feature puts, at the beginning of functions, a canary value on
1849 the stack just before the return address, and validates
1850 the value just before actually returning. Stack based buffer
1851 overflows (that need to overwrite this return address) now also
1852 overwrite the canary, which gets detected and the attack is then
1853 neutralized via a kernel panic.
1854 This feature requires gcc version 4.2 or above.
1856 config DEPRECATED_PARAM_STRUCT
1857 bool "Provide old way to pass kernel parameters"
1859 This was deprecated in 2001 and announced to live on for 5 years.
1860 Some old boot loaders still use this way.
1864 depends on CPU_V7 && SYSFS
1872 bool "Flattened Device Tree support"
1874 select OF_EARLY_FLATTREE
1877 Include support for flattened device tree machine descriptions.
1879 # Compressed boot loader in ROM. Yes, we really want to ask about
1880 # TEXT and BSS so we preserve their values in the config files.
1881 config ZBOOT_ROM_TEXT
1882 hex "Compressed ROM boot loader base address"
1885 The physical address at which the ROM-able zImage is to be
1886 placed in the target. Platforms which normally make use of
1887 ROM-able zImage formats normally set this to a suitable
1888 value in their defconfig file.
1890 If ZBOOT_ROM is not enabled, this has no effect.
1892 config ZBOOT_ROM_BSS
1893 hex "Compressed ROM boot loader BSS address"
1896 The base address of an area of read/write memory in the target
1897 for the ROM-able zImage which must be available while the
1898 decompressor is running. It must be large enough to hold the
1899 entire decompressed kernel plus an additional 128 KiB.
1900 Platforms which normally make use of ROM-able zImage formats
1901 normally set this to a suitable value in their defconfig file.
1903 If ZBOOT_ROM is not enabled, this has no effect.
1906 bool "Compressed boot loader in ROM/flash"
1907 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1909 Say Y here if you intend to execute your compressed kernel image
1910 (zImage) directly from ROM or flash. If unsure, say N.
1913 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1914 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1915 default ZBOOT_ROM_NONE
1917 Include experimental SD/MMC loading code in the ROM-able zImage.
1918 With this enabled it is possible to write the the ROM-able zImage
1919 kernel image to an MMC or SD card and boot the kernel straight
1920 from the reset vector. At reset the processor Mask ROM will load
1921 the first part of the the ROM-able zImage which in turn loads the
1922 rest the kernel image to RAM.
1924 config ZBOOT_ROM_NONE
1925 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1927 Do not load image from SD or MMC
1929 config ZBOOT_ROM_MMCIF
1930 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1932 Load image from MMCIF hardware block.
1934 config ZBOOT_ROM_SH_MOBILE_SDHI
1935 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1937 Load image from SDHI hardware block
1941 config ARM_APPENDED_DTB
1942 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1943 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1945 With this option, the boot code will look for a device tree binary
1946 (DTB) appended to zImage
1947 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1949 This is meant as a backward compatibility convenience for those
1950 systems with a bootloader that can't be upgraded to accommodate
1951 the documented boot protocol using a device tree.
1953 Beware that there is very little in terms of protection against
1954 this option being confused by leftover garbage in memory that might
1955 look like a DTB header after a reboot if no actual DTB is appended
1956 to zImage. Do not leave this option active in a production kernel
1957 if you don't intend to always append a DTB. Proper passing of the
1958 location into r2 of a bootloader provided DTB is always preferable
1961 config ARM_ATAG_DTB_COMPAT
1962 bool "Supplement the appended DTB with traditional ATAG information"
1963 depends on ARM_APPENDED_DTB
1965 Some old bootloaders can't be updated to a DTB capable one, yet
1966 they provide ATAGs with memory configuration, the ramdisk address,
1967 the kernel cmdline string, etc. Such information is dynamically
1968 provided by the bootloader and can't always be stored in a static
1969 DTB. To allow a device tree enabled kernel to be used with such
1970 bootloaders, this option allows zImage to extract the information
1971 from the ATAG list and store it at run time into the appended DTB.
1974 string "Default kernel command string"
1977 On some architectures (EBSA110 and CATS), there is currently no way
1978 for the boot loader to pass arguments to the kernel. For these
1979 architectures, you should supply some command-line options at build
1980 time by entering them here. As a minimum, you should specify the
1981 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1984 prompt "Kernel command line type" if CMDLINE != ""
1985 default CMDLINE_FROM_BOOTLOADER
1987 config CMDLINE_FROM_BOOTLOADER
1988 bool "Use bootloader kernel arguments if available"
1990 Uses the command-line options passed by the boot loader. If
1991 the boot loader doesn't provide any, the default kernel command
1992 string provided in CMDLINE will be used.
1994 config CMDLINE_EXTEND
1995 bool "Extend bootloader kernel arguments"
1997 The command-line arguments provided by the boot loader will be
1998 appended to the default kernel command string.
2000 config CMDLINE_FORCE
2001 bool "Always use the default kernel command string"
2003 Always use the default kernel command string, even if the boot
2004 loader passes other arguments to the kernel.
2005 This is useful if you cannot or don't want to change the
2006 command-line options your boot loader passes to the kernel.
2010 bool "Kernel Execute-In-Place from ROM"
2011 depends on !ZBOOT_ROM && !ARM_LPAE
2013 Execute-In-Place allows the kernel to run from non-volatile storage
2014 directly addressable by the CPU, such as NOR flash. This saves RAM
2015 space since the text section of the kernel is not loaded from flash
2016 to RAM. Read-write sections, such as the data section and stack,
2017 are still copied to RAM. The XIP kernel is not compressed since
2018 it has to run directly from flash, so it will take more space to
2019 store it. The flash address used to link the kernel object files,
2020 and for storing it, is configuration dependent. Therefore, if you
2021 say Y here, you must know the proper physical address where to
2022 store the kernel image depending on your own flash memory usage.
2024 Also note that the make target becomes "make xipImage" rather than
2025 "make zImage" or "make Image". The final kernel binary to put in
2026 ROM memory will be arch/arm/boot/xipImage.
2030 config XIP_PHYS_ADDR
2031 hex "XIP Kernel Physical Location"
2032 depends on XIP_KERNEL
2033 default "0x00080000"
2035 This is the physical address in your flash memory the kernel will
2036 be linked for and stored to. This address is dependent on your
2040 bool "Kexec system call (EXPERIMENTAL)"
2041 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2043 kexec is a system call that implements the ability to shutdown your
2044 current kernel, and to start another kernel. It is like a reboot
2045 but it is independent of the system firmware. And like a reboot
2046 you can start any kernel with it, not just Linux.
2048 It is an ongoing process to be certain the hardware in a machine
2049 is properly shutdown, so do not be surprised if this code does not
2050 initially work for you. It may help to enable device hotplugging
2054 bool "Export atags in procfs"
2058 Should the atags used to boot the kernel be exported in an "atags"
2059 file in procfs. Useful with kexec.
2062 bool "Build kdump crash kernel (EXPERIMENTAL)"
2063 depends on EXPERIMENTAL
2065 Generate crash dump after being started by kexec. This should
2066 be normally only set in special crash dump kernels which are
2067 loaded in the main kernel with kexec-tools into a specially
2068 reserved region and then later executed after a crash by
2069 kdump/kexec. The crash dump kernel must be compiled to a
2070 memory address not used by the main kernel
2072 For more details see Documentation/kdump/kdump.txt
2074 config AUTO_ZRELADDR
2075 bool "Auto calculation of the decompressed kernel image address"
2076 depends on !ZBOOT_ROM && !ARCH_U300
2078 ZRELADDR is the physical address where the decompressed kernel
2079 image will be placed. If AUTO_ZRELADDR is selected, the address
2080 will be determined at run-time by masking the current IP with
2081 0xf8000000. This assumes the zImage being placed in the first 128MB
2082 from start of memory.
2086 menu "CPU Power Management"
2090 source "drivers/cpufreq/Kconfig"
2093 tristate "CPUfreq driver for i.MX CPUs"
2094 depends on ARCH_MXC && CPU_FREQ
2095 select CPU_FREQ_TABLE
2097 This enables the CPUfreq driver for i.MX CPUs.
2099 config CPU_FREQ_SA1100
2102 config CPU_FREQ_SA1110
2105 config CPU_FREQ_INTEGRATOR
2106 tristate "CPUfreq driver for ARM Integrator CPUs"
2107 depends on ARCH_INTEGRATOR && CPU_FREQ
2110 This enables the CPUfreq driver for ARM Integrator CPUs.
2112 For details, take a look at <file:Documentation/cpu-freq>.
2118 depends on CPU_FREQ && ARCH_PXA && PXA25x
2120 select CPU_FREQ_TABLE
2121 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2126 Internal configuration node for common cpufreq on Samsung SoC
2128 config CPU_FREQ_S3C24XX
2129 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2130 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2133 This enables the CPUfreq driver for the Samsung S3C24XX family
2136 For details, take a look at <file:Documentation/cpu-freq>.
2140 config CPU_FREQ_S3C24XX_PLL
2141 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2142 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2144 Compile in support for changing the PLL frequency from the
2145 S3C24XX series CPUfreq driver. The PLL takes time to settle
2146 after a frequency change, so by default it is not enabled.
2148 This also means that the PLL tables for the selected CPU(s) will
2149 be built which may increase the size of the kernel image.
2151 config CPU_FREQ_S3C24XX_DEBUG
2152 bool "Debug CPUfreq Samsung driver core"
2153 depends on CPU_FREQ_S3C24XX
2155 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2157 config CPU_FREQ_S3C24XX_IODEBUG
2158 bool "Debug CPUfreq Samsung driver IO timing"
2159 depends on CPU_FREQ_S3C24XX
2161 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2163 config CPU_FREQ_S3C24XX_DEBUGFS
2164 bool "Export debugfs for CPUFreq"
2165 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2167 Export status information via debugfs.
2171 source "drivers/cpuidle/Kconfig"
2175 menu "Floating point emulation"
2177 comment "At least one emulation must be selected"
2180 bool "NWFPE math emulation"
2181 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2183 Say Y to include the NWFPE floating point emulator in the kernel.
2184 This is necessary to run most binaries. Linux does not currently
2185 support floating point hardware so you need to say Y here even if
2186 your machine has an FPA or floating point co-processor podule.
2188 You may say N here if you are going to load the Acorn FPEmulator
2189 early in the bootup.
2192 bool "Support extended precision"
2193 depends on FPE_NWFPE
2195 Say Y to include 80-bit support in the kernel floating-point
2196 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2197 Note that gcc does not generate 80-bit operations by default,
2198 so in most cases this option only enlarges the size of the
2199 floating point emulator without any good reason.
2201 You almost surely want to say N here.
2204 bool "FastFPE math emulation (EXPERIMENTAL)"
2205 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2207 Say Y here to include the FAST floating point emulator in the kernel.
2208 This is an experimental much faster emulator which now also has full
2209 precision for the mantissa. It does not support any exceptions.
2210 It is very simple, and approximately 3-6 times faster than NWFPE.
2212 It should be sufficient for most programs. It may be not suitable
2213 for scientific calculations, but you have to check this for yourself.
2214 If you do not feel you need a faster FP emulation you should better
2218 bool "VFP-format floating point maths"
2219 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2221 Say Y to include VFP support code in the kernel. This is needed
2222 if your hardware includes a VFP unit.
2224 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2225 release notes and additional status information.
2227 Say N if your target does not have VFP hardware.
2235 bool "Advanced SIMD (NEON) Extension support"
2236 depends on VFPv3 && CPU_V7
2238 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2243 menu "Userspace binary formats"
2245 source "fs/Kconfig.binfmt"
2248 tristate "RISC OS personality"
2251 Say Y here to include the kernel code necessary if you want to run
2252 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2253 experimental; if this sounds frightening, say N and sleep in peace.
2254 You can also say M here to compile this support as a module (which
2255 will be called arthur).
2259 menu "Power management options"
2261 source "kernel/power/Kconfig"
2263 config ARCH_SUSPEND_POSSIBLE
2264 depends on !ARCH_S5PC100
2265 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2266 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2269 config ARM_CPU_SUSPEND
2274 source "net/Kconfig"
2276 source "drivers/Kconfig"
2280 source "arch/arm/Kconfig.debug"
2282 source "security/Kconfig"
2284 source "crypto/Kconfig"
2286 source "lib/Kconfig"