4 select HAVE_DMA_API_DEBUG
5 select HAVE_IDE if PCI || ISA || PCMCIA
8 select SYS_SUPPORTS_APM_EMULATION
9 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
10 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_KPROBES if !XIP_KERNEL
13 select HAVE_KRETPROBES if (HAVE_KPROBES)
14 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
15 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
16 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
17 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
18 select HAVE_GENERIC_DMA_COHERENT
19 select HAVE_KERNEL_GZIP
20 select HAVE_KERNEL_LZO
21 select HAVE_KERNEL_LZMA
23 select HAVE_PERF_EVENTS
24 select PERF_USE_VMALLOC
25 select HAVE_REGS_AND_STACK_ACCESS_API
26 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_GENERIC_HARDIRQS
29 select HAVE_SPARSE_IRQ
30 select GENERIC_IRQ_SHOW
31 select CPU_PM if (SUSPEND || CPU_IDLE)
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_MEMORY_H
217 Select this when mach/memory.h is required to provide special
218 definitions for this platform. The need for mach/memory.h should
219 be avoided when possible.
222 hex "Physical address of main memory" if MMU
223 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
224 default DRAM_BASE if !MMU
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
257 select ARCH_HAS_CPUFREQ
259 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 Support for ARM's Integrator platform.
269 bool "ARM Ltd. RealView family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select ARM_TIMER_SP804
279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
282 This enables support for ARM Ltd RealView boards.
284 config ARCH_VERSATILE
285 bool "ARM Ltd. Versatile family"
289 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
293 select PLAT_VERSATILE
294 select PLAT_VERSATILE_CLCD
295 select PLAT_VERSATILE_FPGA_IRQ
296 select ARM_TIMER_SP804
298 This enables support for ARM Ltd Versatile board.
301 bool "ARM Ltd. Versatile Express family"
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_TIMER_SP804
306 select HAVE_MACH_CLKDEV
307 select GENERIC_CLOCKEVENTS
309 select HAVE_PATA_PLATFORM
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
314 This enables support for the ARM Ltd Versatile Express boards.
318 select ARCH_REQUIRE_GPIOLIB
322 This enables support for systems based on the Atmel AT91RM9200,
323 AT91SAM9 and AT91CAP9 processors.
326 bool "Broadcom BCMRING"
330 select ARM_TIMER_SP804
332 select GENERIC_CLOCKEVENTS
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 Support for Broadcom's BCMRing platform.
338 bool "Calxeda Highbank-based"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
345 select GENERIC_CLOCKEVENTS
349 Support for the Calxeda Highbank SoC based boards.
352 bool "Cirrus Logic CLPS711x/EP721x-based"
354 select ARCH_USES_GETTIMEOFFSET
355 select NEED_MACH_MEMORY_H
357 Support for Cirrus Logic 711x/721x based boards.
360 bool "Cavium Networks CNS3XXX family"
362 select GENERIC_CLOCKEVENTS
364 select MIGHT_HAVE_PCI
365 select PCI_DOMAINS if PCI
367 Support for Cavium Networks CNS3XXX platform.
370 bool "Cortina Systems Gemini"
372 select ARCH_REQUIRE_GPIOLIB
373 select ARCH_USES_GETTIMEOFFSET
375 Support for the Cortina Systems Gemini family SoCs
378 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
381 select GENERIC_CLOCKEVENTS
383 select GENERIC_IRQ_CHIP
387 Support for CSR SiRFSoC ARM Cortex A9 Platform
394 select ARCH_USES_GETTIMEOFFSET
395 select NEED_MACH_MEMORY_H
397 This is an evaluation board for the StrongARM processor available
398 from Digital. It has limited hardware on-board, including an
399 Ethernet interface, two PCMCIA sockets, two serial ports and a
408 select ARCH_REQUIRE_GPIOLIB
409 select ARCH_HAS_HOLES_MEMORYMODEL
410 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_MEMORY_H
413 This enables support for the Cirrus EP93xx series of CPUs.
415 config ARCH_FOOTBRIDGE
419 select GENERIC_CLOCKEVENTS
421 select NEED_MACH_MEMORY_H
423 Support for systems based on the DC21285 companion chip
424 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
427 bool "Freescale MXC/iMX-based"
428 select GENERIC_CLOCKEVENTS
429 select ARCH_REQUIRE_GPIOLIB
432 select GENERIC_IRQ_CHIP
433 select HAVE_SCHED_CLOCK
434 select MULTI_IRQ_HANDLER
436 Support for Freescale MXC/iMX-based family of processors
439 bool "Freescale MXS-based"
440 select GENERIC_CLOCKEVENTS
441 select ARCH_REQUIRE_GPIOLIB
445 Support for Freescale MXS-based family of processors
448 bool "Hilscher NetX based"
452 select GENERIC_CLOCKEVENTS
454 This enables support for systems based on the Hilscher NetX Soc
457 bool "Hynix HMS720x-based"
460 select ARCH_USES_GETTIMEOFFSET
462 This enables support for systems based on the Hynix HMS720x
470 select ARCH_SUPPORTS_MSI
472 select NEED_MACH_MEMORY_H
474 Support for Intel's IOP13XX (XScale) family of processors.
482 select ARCH_REQUIRE_GPIOLIB
484 Support for Intel's 80219 and IOP32X (XScale) family of
493 select ARCH_REQUIRE_GPIOLIB
495 Support for Intel's IOP33X (XScale) family of processors.
502 select ARCH_USES_GETTIMEOFFSET
503 select NEED_MACH_MEMORY_H
505 Support for Intel's IXP23xx (XScale) family of processors.
508 bool "IXP2400/2800-based"
512 select ARCH_USES_GETTIMEOFFSET
513 select NEED_MACH_MEMORY_H
515 Support for Intel's IXP2400/2800 (XScale) family of processors.
522 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
524 select HAVE_SCHED_CLOCK
525 select MIGHT_HAVE_PCI
526 select DMABOUNCE if PCI
528 Support for Intel's IXP4XX (XScale) family of processors.
534 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
538 Support for the Marvell Dove SoC 88AP510
541 bool "Marvell Kirkwood"
545 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
549 Support for the following Marvell Kirkwood series SoCs:
550 88F6180, 88F6192 and 88F6281.
556 select ARCH_REQUIRE_GPIOLIB
559 select USB_ARCH_HAS_OHCI
561 select GENERIC_CLOCKEVENTS
563 Support for the NXP LPC32XX family of processors
566 bool "Marvell MV78xx0"
569 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
573 Support for the following Marvell MV78xx0 series SoCs:
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
585 Support for the following Marvell Orion 5x series SoCs:
586 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
587 Orion-2 (5281), Orion-1-90 (6183).
590 bool "Marvell PXA168/910/MMP2"
592 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
595 select HAVE_SCHED_CLOCK
599 select GENERIC_ALLOCATOR
601 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
604 bool "Micrel/Kendin KS8695"
606 select ARCH_REQUIRE_GPIOLIB
607 select ARCH_USES_GETTIMEOFFSET
608 select NEED_MACH_MEMORY_H
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
614 bool "Nuvoton W90X900 CPU"
616 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
633 select GENERIC_CLOCKEVENTS
636 select HAVE_SCHED_CLOCK
637 select ARCH_HAS_CPUFREQ
639 This enables support for NVIDIA Tegra based systems (Tegra APX,
640 Tegra 6xx and Tegra 2 series).
642 config ARCH_PICOXCELL
643 bool "Picochip picoXcell"
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_PATCH_PHYS_VIRT
649 select GENERIC_CLOCKEVENTS
651 select HAVE_SCHED_CLOCK
656 This enables support for systems based on the Picochip picoXcell
657 family of Femtocell devices. The picoxcell support requires device tree
661 bool "Philips Nexperia PNX4008 Mobile"
664 select ARCH_USES_GETTIMEOFFSET
666 This enables support for Philips PNX4008 mobile platform.
669 bool "PXA2xx/PXA3xx-based"
672 select ARCH_HAS_CPUFREQ
675 select ARCH_REQUIRE_GPIOLIB
676 select GENERIC_CLOCKEVENTS
677 select HAVE_SCHED_CLOCK
682 select MULTI_IRQ_HANDLER
683 select ARM_CPU_SUSPEND if PM
686 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
691 select GENERIC_CLOCKEVENTS
692 select ARCH_REQUIRE_GPIOLIB
695 Support for Qualcomm MSM/QSD based systems. This runs on the
696 apps processor of the MSM/QSD and depends on a shared memory
697 interface to the modem processor which runs the baseband
698 stack and controls some vital subsystems
699 (clock and power control, etc).
702 bool "Renesas SH-Mobile / R-Mobile"
705 select HAVE_MACH_CLKDEV
706 select GENERIC_CLOCKEVENTS
709 select MULTI_IRQ_HANDLER
710 select PM_GENERIC_DOMAINS if PM
711 select NEED_MACH_MEMORY_H
713 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
720 select ARCH_MAY_HAVE_PC_FDC
721 select HAVE_PATA_PLATFORM
724 select ARCH_SPARSEMEM_ENABLE
725 select ARCH_USES_GETTIMEOFFSET
727 select NEED_MACH_MEMORY_H
729 On the Acorn Risc-PC, Linux can support the internal IDE disk and
730 CD-ROM interface, serial and parallel port, and the floppy drive.
737 select ARCH_SPARSEMEM_ENABLE
739 select ARCH_HAS_CPUFREQ
741 select GENERIC_CLOCKEVENTS
743 select HAVE_SCHED_CLOCK
745 select ARCH_REQUIRE_GPIOLIB
747 select NEED_MACH_MEMORY_H
749 Support for StrongARM 11x0 based boards.
752 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
754 select ARCH_HAS_CPUFREQ
757 select ARCH_USES_GETTIMEOFFSET
758 select HAVE_S3C2410_I2C if I2C
760 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
761 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
762 the Samsung SMDK2410 development board (and derivatives).
764 Note, the S3C2416 and the S3C2450 are so close that they even share
765 the same SoC ID code. This means that there is no separate machine
766 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
769 bool "Samsung S3C64XX"
777 select ARCH_USES_GETTIMEOFFSET
778 select ARCH_HAS_CPUFREQ
779 select ARCH_REQUIRE_GPIOLIB
780 select SAMSUNG_CLKSRC
781 select SAMSUNG_IRQ_VIC_TIMER
782 select S3C_GPIO_TRACK
784 select USB_ARCH_HAS_OHCI
785 select SAMSUNG_GPIOLIB_4BIT
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 Samsung S3C64XX series based systems
792 bool "Samsung S5P6440 S5P6450"
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select GENERIC_CLOCKEVENTS
800 select HAVE_SCHED_CLOCK
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C_RTC if RTC_CLASS
804 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
808 bool "Samsung S5PC100"
813 select ARM_L1_CACHE_SHIFT_6
814 select ARCH_USES_GETTIMEOFFSET
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 Samsung S5PC100 series based systems
822 bool "Samsung S5PV210/S5PC110"
824 select ARCH_SPARSEMEM_ENABLE
825 select ARCH_HAS_HOLES_MEMORYMODEL
830 select ARM_L1_CACHE_SHIFT_6
831 select ARCH_HAS_CPUFREQ
832 select GENERIC_CLOCKEVENTS
833 select HAVE_SCHED_CLOCK
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C_RTC if RTC_CLASS
836 select HAVE_S3C2410_WATCHDOG if WATCHDOG
837 select NEED_MACH_MEMORY_H
839 Samsung S5PV210/S5PC110 series based systems
842 bool "SAMSUNG EXYNOS"
844 select ARCH_SPARSEMEM_ENABLE
845 select ARCH_HAS_HOLES_MEMORYMODEL
849 select ARCH_HAS_CPUFREQ
850 select GENERIC_CLOCKEVENTS
851 select HAVE_S3C_RTC if RTC_CLASS
852 select HAVE_S3C2410_I2C if I2C
853 select HAVE_S3C2410_WATCHDOG if WATCHDOG
854 select NEED_MACH_MEMORY_H
856 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
865 select ARCH_USES_GETTIMEOFFSET
866 select NEED_MACH_MEMORY_H
868 Support for the StrongARM based Digital DNARD machine, also known
869 as "Shark" (<http://www.shark-linux.de/shark.html>).
872 bool "Telechips TCC ARM926-based systems"
877 select GENERIC_CLOCKEVENTS
879 Support for Telechips TCC ARM926-based systems.
882 bool "ST-Ericsson U300 Series"
886 select HAVE_SCHED_CLOCK
889 select ARM_PATCH_PHYS_VIRT
891 select GENERIC_CLOCKEVENTS
893 select HAVE_MACH_CLKDEV
895 select ARCH_REQUIRE_GPIOLIB
896 select NEED_MACH_MEMORY_H
898 Support for ST-Ericsson U300 series mobile platforms.
901 bool "ST-Ericsson U8500 Series"
904 select GENERIC_CLOCKEVENTS
906 select ARCH_REQUIRE_GPIOLIB
907 select ARCH_HAS_CPUFREQ
909 Support for ST-Ericsson's Ux500 architecture
912 bool "STMicroelectronics Nomadik"
917 select GENERIC_CLOCKEVENTS
918 select ARCH_REQUIRE_GPIOLIB
920 Support for the Nomadik platform by ST-Ericsson
924 select GENERIC_CLOCKEVENTS
925 select ARCH_REQUIRE_GPIOLIB
929 select GENERIC_ALLOCATOR
930 select GENERIC_IRQ_CHIP
931 select ARCH_HAS_HOLES_MEMORYMODEL
933 Support for TI's DaVinci platform.
938 select ARCH_REQUIRE_GPIOLIB
939 select ARCH_HAS_CPUFREQ
941 select GENERIC_CLOCKEVENTS
942 select HAVE_SCHED_CLOCK
943 select ARCH_HAS_HOLES_MEMORYMODEL
945 Support for TI's OMAP platform (OMAP1/2/3/4).
950 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_CLOCKEVENTS
956 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
959 bool "VIA/WonderMedia 85xx"
962 select ARCH_HAS_CPUFREQ
963 select GENERIC_CLOCKEVENTS
964 select ARCH_REQUIRE_GPIOLIB
967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
970 bool "Xilinx Zynq ARM Cortex A9 Platform"
972 select GENERIC_CLOCKEVENTS
979 Support for Xilinx Zynq ARM Cortex A9 Platform
983 # This is sorted alphabetically by mach-* pathname. However, plat-*
984 # Kconfigs may be included either alphabetically (according to the
985 # plat- suffix) or along side the corresponding mach-* source.
987 source "arch/arm/mach-at91/Kconfig"
989 source "arch/arm/mach-bcmring/Kconfig"
991 source "arch/arm/mach-clps711x/Kconfig"
993 source "arch/arm/mach-cns3xxx/Kconfig"
995 source "arch/arm/mach-davinci/Kconfig"
997 source "arch/arm/mach-dove/Kconfig"
999 source "arch/arm/mach-ep93xx/Kconfig"
1001 source "arch/arm/mach-footbridge/Kconfig"
1003 source "arch/arm/mach-gemini/Kconfig"
1005 source "arch/arm/mach-h720x/Kconfig"
1007 source "arch/arm/mach-integrator/Kconfig"
1009 source "arch/arm/mach-iop32x/Kconfig"
1011 source "arch/arm/mach-iop33x/Kconfig"
1013 source "arch/arm/mach-iop13xx/Kconfig"
1015 source "arch/arm/mach-ixp4xx/Kconfig"
1017 source "arch/arm/mach-ixp2000/Kconfig"
1019 source "arch/arm/mach-ixp23xx/Kconfig"
1021 source "arch/arm/mach-kirkwood/Kconfig"
1023 source "arch/arm/mach-ks8695/Kconfig"
1025 source "arch/arm/mach-lpc32xx/Kconfig"
1027 source "arch/arm/mach-msm/Kconfig"
1029 source "arch/arm/mach-mv78xx0/Kconfig"
1031 source "arch/arm/plat-mxc/Kconfig"
1033 source "arch/arm/mach-mxs/Kconfig"
1035 source "arch/arm/mach-netx/Kconfig"
1037 source "arch/arm/mach-nomadik/Kconfig"
1038 source "arch/arm/plat-nomadik/Kconfig"
1040 source "arch/arm/plat-omap/Kconfig"
1042 source "arch/arm/mach-omap1/Kconfig"
1044 source "arch/arm/mach-omap2/Kconfig"
1046 source "arch/arm/mach-orion5x/Kconfig"
1048 source "arch/arm/mach-pxa/Kconfig"
1049 source "arch/arm/plat-pxa/Kconfig"
1051 source "arch/arm/mach-mmp/Kconfig"
1053 source "arch/arm/mach-realview/Kconfig"
1055 source "arch/arm/mach-sa1100/Kconfig"
1057 source "arch/arm/plat-samsung/Kconfig"
1058 source "arch/arm/plat-s3c24xx/Kconfig"
1059 source "arch/arm/plat-s5p/Kconfig"
1061 source "arch/arm/plat-spear/Kconfig"
1063 source "arch/arm/plat-tcc/Kconfig"
1066 source "arch/arm/mach-s3c2410/Kconfig"
1067 source "arch/arm/mach-s3c2412/Kconfig"
1068 source "arch/arm/mach-s3c2416/Kconfig"
1069 source "arch/arm/mach-s3c2440/Kconfig"
1070 source "arch/arm/mach-s3c2443/Kconfig"
1074 source "arch/arm/mach-s3c64xx/Kconfig"
1077 source "arch/arm/mach-s5p64x0/Kconfig"
1079 source "arch/arm/mach-s5pc100/Kconfig"
1081 source "arch/arm/mach-s5pv210/Kconfig"
1083 source "arch/arm/mach-exynos/Kconfig"
1085 source "arch/arm/mach-shmobile/Kconfig"
1087 source "arch/arm/mach-tegra/Kconfig"
1089 source "arch/arm/mach-u300/Kconfig"
1091 source "arch/arm/mach-ux500/Kconfig"
1093 source "arch/arm/mach-versatile/Kconfig"
1095 source "arch/arm/mach-vexpress/Kconfig"
1096 source "arch/arm/plat-versatile/Kconfig"
1098 source "arch/arm/mach-vt8500/Kconfig"
1100 source "arch/arm/mach-w90x900/Kconfig"
1102 # Definitions to make life easier
1108 select GENERIC_CLOCKEVENTS
1109 select HAVE_SCHED_CLOCK
1114 select GENERIC_IRQ_CHIP
1115 select HAVE_SCHED_CLOCK
1120 config PLAT_VERSATILE
1123 config ARM_TIMER_SP804
1127 source arch/arm/mm/Kconfig
1130 bool "Enable iWMMXt support"
1131 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1132 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1134 Enable support for iWMMXt context switching at run time if
1135 running on a CPU that supports it.
1137 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1140 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1144 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1145 (!ARCH_OMAP3 || OMAP3_EMU)
1149 config MULTI_IRQ_HANDLER
1152 Allow each machine to specify it's own IRQ handler at run time.
1155 source "arch/arm/Kconfig-nommu"
1158 config ARM_ERRATA_326103
1159 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1162 Executing a SWP instruction to read-only memory does not set bit 11
1163 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1164 treat the access as a read, preventing a COW from occurring and
1165 causing the faulting task to livelock.
1167 config ARM_ERRATA_411920
1168 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1169 depends on CPU_V6 || CPU_V6K
1171 Invalidation of the Instruction Cache operation can
1172 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1173 It does not affect the MPCore. This option enables the ARM Ltd.
1174 recommended workaround.
1176 config ARM_ERRATA_430973
1177 bool "ARM errata: Stale prediction on replaced interworking branch"
1180 This option enables the workaround for the 430973 Cortex-A8
1181 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1182 interworking branch is replaced with another code sequence at the
1183 same virtual address, whether due to self-modifying code or virtual
1184 to physical address re-mapping, Cortex-A8 does not recover from the
1185 stale interworking branch prediction. This results in Cortex-A8
1186 executing the new code sequence in the incorrect ARM or Thumb state.
1187 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1188 and also flushes the branch target cache at every context switch.
1189 Note that setting specific bits in the ACTLR register may not be
1190 available in non-secure mode.
1192 config ARM_ERRATA_458693
1193 bool "ARM errata: Processor deadlock when a false hazard is created"
1196 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1197 erratum. For very specific sequences of memory operations, it is
1198 possible for a hazard condition intended for a cache line to instead
1199 be incorrectly associated with a different cache line. This false
1200 hazard might then cause a processor deadlock. The workaround enables
1201 the L1 caching of the NEON accesses and disables the PLD instruction
1202 in the ACTLR register. Note that setting specific bits in the ACTLR
1203 register may not be available in non-secure mode.
1205 config ARM_ERRATA_460075
1206 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1209 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1210 erratum. Any asynchronous access to the L2 cache may encounter a
1211 situation in which recent store transactions to the L2 cache are lost
1212 and overwritten with stale memory contents from external memory. The
1213 workaround disables the write-allocate mode for the L2 cache via the
1214 ACTLR register. Note that setting specific bits in the ACTLR register
1215 may not be available in non-secure mode.
1217 config ARM_ERRATA_742230
1218 bool "ARM errata: DMB operation may be faulty"
1219 depends on CPU_V7 && SMP
1221 This option enables the workaround for the 742230 Cortex-A9
1222 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1223 between two write operations may not ensure the correct visibility
1224 ordering of the two writes. This workaround sets a specific bit in
1225 the diagnostic register of the Cortex-A9 which causes the DMB
1226 instruction to behave as a DSB, ensuring the correct behaviour of
1229 config ARM_ERRATA_742231
1230 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1231 depends on CPU_V7 && SMP
1233 This option enables the workaround for the 742231 Cortex-A9
1234 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1235 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1236 accessing some data located in the same cache line, may get corrupted
1237 data due to bad handling of the address hazard when the line gets
1238 replaced from one of the CPUs at the same time as another CPU is
1239 accessing it. This workaround sets specific bits in the diagnostic
1240 register of the Cortex-A9 which reduces the linefill issuing
1241 capabilities of the processor.
1243 config PL310_ERRATA_588369
1244 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1245 depends on CACHE_L2X0
1247 The PL310 L2 cache controller implements three types of Clean &
1248 Invalidate maintenance operations: by Physical Address
1249 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1250 They are architecturally defined to behave as the execution of a
1251 clean operation followed immediately by an invalidate operation,
1252 both performing to the same memory location. This functionality
1253 is not correctly implemented in PL310 as clean lines are not
1254 invalidated as a result of these operations.
1256 config ARM_ERRATA_720789
1257 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1260 This option enables the workaround for the 720789 Cortex-A9 (prior to
1261 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1262 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1263 As a consequence of this erratum, some TLB entries which should be
1264 invalidated are not, resulting in an incoherency in the system page
1265 tables. The workaround changes the TLB flushing routines to invalidate
1266 entries regardless of the ASID.
1268 config PL310_ERRATA_727915
1269 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1270 depends on CACHE_L2X0
1272 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1273 operation (offset 0x7FC). This operation runs in background so that
1274 PL310 can handle normal accesses while it is in progress. Under very
1275 rare circumstances, due to this erratum, write data can be lost when
1276 PL310 treats a cacheable write transaction during a Clean &
1277 Invalidate by Way operation.
1279 config ARM_ERRATA_743622
1280 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1283 This option enables the workaround for the 743622 Cortex-A9
1284 (r2p*) erratum. Under very rare conditions, a faulty
1285 optimisation in the Cortex-A9 Store Buffer may lead to data
1286 corruption. This workaround sets a specific bit in the diagnostic
1287 register of the Cortex-A9 which disables the Store Buffer
1288 optimisation, preventing the defect from occurring. This has no
1289 visible impact on the overall performance or power consumption of the
1292 config ARM_ERRATA_751472
1293 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1296 This option enables the workaround for the 751472 Cortex-A9 (prior
1297 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1298 completion of a following broadcasted operation if the second
1299 operation is received by a CPU before the ICIALLUIS has completed,
1300 potentially leading to corrupted entries in the cache or TLB.
1302 config PL310_ERRATA_753970
1303 bool "PL310 errata: cache sync operation may be faulty"
1304 depends on CACHE_PL310
1306 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1308 Under some condition the effect of cache sync operation on
1309 the store buffer still remains when the operation completes.
1310 This means that the store buffer is always asked to drain and
1311 this prevents it from merging any further writes. The workaround
1312 is to replace the normal offset of cache sync operation (0x730)
1313 by another offset targeting an unmapped PL310 register 0x740.
1314 This has the same effect as the cache sync operation: store buffer
1315 drain and waiting for all buffers empty.
1317 config ARM_ERRATA_754322
1318 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1321 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1322 r3p*) erratum. A speculative memory access may cause a page table walk
1323 which starts prior to an ASID switch but completes afterwards. This
1324 can populate the micro-TLB with a stale entry which may be hit with
1325 the new ASID. This workaround places two dsb instructions in the mm
1326 switching code so that no page table walks can cross the ASID switch.
1328 config ARM_ERRATA_754327
1329 bool "ARM errata: no automatic Store Buffer drain"
1330 depends on CPU_V7 && SMP
1332 This option enables the workaround for the 754327 Cortex-A9 (prior to
1333 r2p0) erratum. The Store Buffer does not have any automatic draining
1334 mechanism and therefore a livelock may occur if an external agent
1335 continuously polls a memory location waiting to observe an update.
1336 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1337 written polling loops from denying visibility of updates to memory.
1339 config ARM_ERRATA_364296
1340 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1341 depends on CPU_V6 && !SMP
1343 This options enables the workaround for the 364296 ARM1136
1344 r0p2 erratum (possible cache data corruption with
1345 hit-under-miss enabled). It sets the undocumented bit 31 in
1346 the auxiliary control register and the FI bit in the control
1347 register, thus disabling hit-under-miss without putting the
1348 processor into full low interrupt latency mode. ARM11MPCore
1351 config ARM_ERRATA_764369
1352 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1353 depends on CPU_V7 && SMP
1355 This option enables the workaround for erratum 764369
1356 affecting Cortex-A9 MPCore with two or more processors (all
1357 current revisions). Under certain timing circumstances, a data
1358 cache line maintenance operation by MVA targeting an Inner
1359 Shareable memory region may fail to proceed up to either the
1360 Point of Coherency or to the Point of Unification of the
1361 system. This workaround adds a DSB instruction before the
1362 relevant cache maintenance functions and sets a specific bit
1363 in the diagnostic control register of the SCU.
1365 config PL310_ERRATA_769419
1366 bool "PL310 errata: no automatic Store Buffer drain"
1367 depends on CACHE_L2X0
1369 On revisions of the PL310 prior to r3p2, the Store Buffer does
1370 not automatically drain. This can cause normal, non-cacheable
1371 writes to be retained when the memory system is idle, leading
1372 to suboptimal I/O performance for drivers using coherent DMA.
1373 This option adds a write barrier to the cpu_idle loop so that,
1374 on systems with an outer cache, the store buffer is drained
1379 source "arch/arm/common/Kconfig"
1389 Find out whether you have ISA slots on your motherboard. ISA is the
1390 name of a bus system, i.e. the way the CPU talks to the other stuff
1391 inside your box. Other bus systems are PCI, EISA, MicroChannel
1392 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1393 newer boards don't support it. If you have ISA, say Y, otherwise N.
1395 # Select ISA DMA controller support
1400 # Select ISA DMA interface
1405 bool "PCI support" if MIGHT_HAVE_PCI
1407 Find out whether you have a PCI motherboard. PCI is the name of a
1408 bus system, i.e. the way the CPU talks to the other stuff inside
1409 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1410 VESA. If you have PCI, say Y, otherwise N.
1416 config PCI_NANOENGINE
1417 bool "BSE nanoEngine PCI support"
1418 depends on SA1100_NANOENGINE
1420 Enable PCI on the BSE nanoEngine board.
1425 # Select the host bridge type
1426 config PCI_HOST_VIA82C505
1428 depends on PCI && ARCH_SHARK
1431 config PCI_HOST_ITE8152
1433 depends on PCI && MACH_ARMCORE
1437 source "drivers/pci/Kconfig"
1439 source "drivers/pcmcia/Kconfig"
1443 menu "Kernel Features"
1445 source "kernel/time/Kconfig"
1448 bool "Symmetric Multi-Processing"
1449 depends on CPU_V6K || CPU_V7
1450 depends on GENERIC_CLOCKEVENTS
1451 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1452 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1453 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1454 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1456 select USE_GENERIC_SMP_HELPERS
1457 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1459 This enables support for systems with more than one CPU. If you have
1460 a system with only one CPU, like most personal computers, say N. If
1461 you have a system with more than one CPU, say Y.
1463 If you say N here, the kernel will run on single and multiprocessor
1464 machines, but will use only one CPU of a multiprocessor machine. If
1465 you say Y here, the kernel will run on many, but not all, single
1466 processor machines. On a single processor machine, the kernel will
1467 run faster if you say N here.
1469 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1470 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1471 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1473 If you don't know what to do here, say N.
1476 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1477 depends on EXPERIMENTAL
1478 depends on SMP && !XIP_KERNEL
1481 SMP kernels contain instructions which fail on non-SMP processors.
1482 Enabling this option allows the kernel to modify itself to make
1483 these instructions safe. Disabling it allows about 1K of space
1486 If you don't know what to do here, say Y.
1488 config ARM_CPU_TOPOLOGY
1489 bool "Support cpu topology definition"
1490 depends on SMP && CPU_V7
1493 Support ARM cpu topology definition. The MPIDR register defines
1494 affinity between processors which is then used to describe the cpu
1495 topology of an ARM System.
1498 bool "Multi-core scheduler support"
1499 depends on ARM_CPU_TOPOLOGY
1501 Multi-core scheduler support improves the CPU scheduler's decision
1502 making when dealing with multi-core CPU chips at a cost of slightly
1503 increased overhead in some places. If unsure say N here.
1506 bool "SMT scheduler support"
1507 depends on ARM_CPU_TOPOLOGY
1509 Improves the CPU scheduler's decision making when dealing with
1510 MultiThreading at a cost of slightly increased overhead in some
1511 places. If unsure say N here.
1516 This option enables support for the ARM system coherency unit
1523 This options enables support for the ARM timer and watchdog unit
1526 prompt "Memory split"
1529 Select the desired split between kernel and user memory.
1531 If you are not absolutely sure what you are doing, leave this
1535 bool "3G/1G user/kernel split"
1537 bool "2G/2G user/kernel split"
1539 bool "1G/3G user/kernel split"
1544 default 0x40000000 if VMSPLIT_1G
1545 default 0x80000000 if VMSPLIT_2G
1549 int "Maximum number of CPUs (2-32)"
1555 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1556 depends on SMP && HOTPLUG && EXPERIMENTAL
1558 Say Y here to experiment with turning CPUs off and on. CPUs
1559 can be controlled through /sys/devices/system/cpu.
1562 bool "Use local timer interrupts"
1565 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1567 Enable support for local timers on SMP platforms, rather then the
1568 legacy IPI broadcast method. Local timers allows the system
1569 accounting to be spread across the timer interval, preventing a
1570 "thundering herd" at every timer tick.
1572 source kernel/Kconfig.preempt
1576 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1577 ARCH_S5PV210 || ARCH_EXYNOS4
1578 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1579 default AT91_TIMER_HZ if ARCH_AT91
1580 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1583 config THUMB2_KERNEL
1584 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1585 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1587 select ARM_ASM_UNIFIED
1590 By enabling this option, the kernel will be compiled in
1591 Thumb-2 mode. A compiler/assembler that understand the unified
1592 ARM-Thumb syntax is needed.
1596 config THUMB2_AVOID_R_ARM_THM_JUMP11
1597 bool "Work around buggy Thumb-2 short branch relocations in gas"
1598 depends on THUMB2_KERNEL && MODULES
1601 Various binutils versions can resolve Thumb-2 branches to
1602 locally-defined, preemptible global symbols as short-range "b.n"
1603 branch instructions.
1605 This is a problem, because there's no guarantee the final
1606 destination of the symbol, or any candidate locations for a
1607 trampoline, are within range of the branch. For this reason, the
1608 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1609 relocation in modules at all, and it makes little sense to add
1612 The symptom is that the kernel fails with an "unsupported
1613 relocation" error when loading some modules.
1615 Until fixed tools are available, passing
1616 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1617 code which hits this problem, at the cost of a bit of extra runtime
1618 stack usage in some cases.
1620 The problem is described in more detail at:
1621 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1623 Only Thumb-2 kernels are affected.
1625 Unless you are sure your tools don't have this problem, say Y.
1627 config ARM_ASM_UNIFIED
1631 bool "Use the ARM EABI to compile the kernel"
1633 This option allows for the kernel to be compiled using the latest
1634 ARM ABI (aka EABI). This is only useful if you are using a user
1635 space environment that is also compiled with EABI.
1637 Since there are major incompatibilities between the legacy ABI and
1638 EABI, especially with regard to structure member alignment, this
1639 option also changes the kernel syscall calling convention to
1640 disambiguate both ABIs and allow for backward compatibility support
1641 (selected with CONFIG_OABI_COMPAT).
1643 To use this you need GCC version 4.0.0 or later.
1646 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1647 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1650 This option preserves the old syscall interface along with the
1651 new (ARM EABI) one. It also provides a compatibility layer to
1652 intercept syscalls that have structure arguments which layout
1653 in memory differs between the legacy ABI and the new ARM EABI
1654 (only for non "thumb" binaries). This option adds a tiny
1655 overhead to all syscalls and produces a slightly larger kernel.
1656 If you know you'll be using only pure EABI user space then you
1657 can say N here. If this option is not selected and you attempt
1658 to execute a legacy ABI binary then the result will be
1659 UNPREDICTABLE (in fact it can be predicted that it won't work
1660 at all). If in doubt say Y.
1662 config ARCH_HAS_HOLES_MEMORYMODEL
1665 config ARCH_SPARSEMEM_ENABLE
1668 config ARCH_SPARSEMEM_DEFAULT
1669 def_bool ARCH_SPARSEMEM_ENABLE
1671 config ARCH_SELECT_MEMORY_MODEL
1672 def_bool ARCH_SPARSEMEM_ENABLE
1674 config HAVE_ARCH_PFN_VALID
1675 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1678 bool "High Memory Support"
1681 The address space of ARM processors is only 4 Gigabytes large
1682 and it has to accommodate user address space, kernel address
1683 space as well as some memory mapped IO. That means that, if you
1684 have a large amount of physical memory and/or IO, not all of the
1685 memory can be "permanently mapped" by the kernel. The physical
1686 memory that is not permanently mapped is called "high memory".
1688 Depending on the selected kernel/user memory split, minimum
1689 vmalloc space and actual amount of RAM, you may not need this
1690 option which should result in a slightly faster kernel.
1695 bool "Allocate 2nd-level pagetables from highmem"
1698 config HW_PERF_EVENTS
1699 bool "Enable hardware performance counter support for perf events"
1700 depends on PERF_EVENTS && CPU_HAS_PMU
1703 Enable hardware performance counter support for perf events. If
1704 disabled, perf events will use software events only.
1708 config FORCE_MAX_ZONEORDER
1709 int "Maximum zone order" if ARCH_SHMOBILE
1710 range 11 64 if ARCH_SHMOBILE
1711 default "9" if SA1111
1714 The kernel memory allocator divides physically contiguous memory
1715 blocks into "zones", where each zone is a power of two number of
1716 pages. This option selects the largest power of two that the kernel
1717 keeps in the memory allocator. If you need to allocate very large
1718 blocks of physically contiguous memory, then you may need to
1719 increase this value.
1721 This config option is actually maximum order plus one. For example,
1722 a value of 11 means that the largest free memory block is 2^10 pages.
1725 bool "Timer and CPU usage LEDs"
1726 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1727 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1728 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1729 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1730 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1731 ARCH_AT91 || ARCH_DAVINCI || \
1732 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1734 If you say Y here, the LEDs on your machine will be used
1735 to provide useful information about your current system status.
1737 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1738 be able to select which LEDs are active using the options below. If
1739 you are compiling a kernel for the EBSA-110 or the LART however, the
1740 red LED will simply flash regularly to indicate that the system is
1741 still functional. It is safe to say Y here if you have a CATS
1742 system, but the driver will do nothing.
1745 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1746 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1747 || MACH_OMAP_PERSEUS2
1749 depends on !GENERIC_CLOCKEVENTS
1750 default y if ARCH_EBSA110
1752 If you say Y here, one of the system LEDs (the green one on the
1753 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1754 will flash regularly to indicate that the system is still
1755 operational. This is mainly useful to kernel hackers who are
1756 debugging unstable kernels.
1758 The LART uses the same LED for both Timer LED and CPU usage LED
1759 functions. You may choose to use both, but the Timer LED function
1760 will overrule the CPU usage LED.
1763 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1765 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1766 || MACH_OMAP_PERSEUS2
1769 If you say Y here, the red LED will be used to give a good real
1770 time indication of CPU usage, by lighting whenever the idle task
1771 is not currently executing.
1773 The LART uses the same LED for both Timer LED and CPU usage LED
1774 functions. You may choose to use both, but the Timer LED function
1775 will overrule the CPU usage LED.
1777 config ALIGNMENT_TRAP
1779 depends on CPU_CP15_MMU
1780 default y if !ARCH_EBSA110
1781 select HAVE_PROC_CPU if PROC_FS
1783 ARM processors cannot fetch/store information which is not
1784 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1785 address divisible by 4. On 32-bit ARM processors, these non-aligned
1786 fetch/store instructions will be emulated in software if you say
1787 here, which has a severe performance impact. This is necessary for
1788 correct operation of some network protocols. With an IP-only
1789 configuration it is safe to say N, otherwise say Y.
1791 config UACCESS_WITH_MEMCPY
1792 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1793 depends on MMU && EXPERIMENTAL
1794 default y if CPU_FEROCEON
1796 Implement faster copy_to_user and clear_user methods for CPU
1797 cores where a 8-word STM instruction give significantly higher
1798 memory write throughput than a sequence of individual 32bit stores.
1800 A possible side effect is a slight increase in scheduling latency
1801 between threads sharing the same address space if they invoke
1802 such copy operations with large buffers.
1804 However, if the CPU data cache is using a write-allocate mode,
1805 this option is unlikely to provide any performance gain.
1809 prompt "Enable seccomp to safely compute untrusted bytecode"
1811 This kernel feature is useful for number crunching applications
1812 that may need to compute untrusted bytecode during their
1813 execution. By using pipes or other transports made available to
1814 the process as file descriptors supporting the read/write
1815 syscalls, it's possible to isolate those applications in
1816 their own address space using seccomp. Once seccomp is
1817 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1818 and the task is only allowed to execute a few safe syscalls
1819 defined by each seccomp mode.
1821 config CC_STACKPROTECTOR
1822 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1823 depends on EXPERIMENTAL
1825 This option turns on the -fstack-protector GCC feature. This
1826 feature puts, at the beginning of functions, a canary value on
1827 the stack just before the return address, and validates
1828 the value just before actually returning. Stack based buffer
1829 overflows (that need to overwrite this return address) now also
1830 overwrite the canary, which gets detected and the attack is then
1831 neutralized via a kernel panic.
1832 This feature requires gcc version 4.2 or above.
1834 config DEPRECATED_PARAM_STRUCT
1835 bool "Provide old way to pass kernel parameters"
1837 This was deprecated in 2001 and announced to live on for 5 years.
1838 Some old boot loaders still use this way.
1845 bool "Flattened Device Tree support"
1847 select OF_EARLY_FLATTREE
1850 Include support for flattened device tree machine descriptions.
1852 # Compressed boot loader in ROM. Yes, we really want to ask about
1853 # TEXT and BSS so we preserve their values in the config files.
1854 config ZBOOT_ROM_TEXT
1855 hex "Compressed ROM boot loader base address"
1858 The physical address at which the ROM-able zImage is to be
1859 placed in the target. Platforms which normally make use of
1860 ROM-able zImage formats normally set this to a suitable
1861 value in their defconfig file.
1863 If ZBOOT_ROM is not enabled, this has no effect.
1865 config ZBOOT_ROM_BSS
1866 hex "Compressed ROM boot loader BSS address"
1869 The base address of an area of read/write memory in the target
1870 for the ROM-able zImage which must be available while the
1871 decompressor is running. It must be large enough to hold the
1872 entire decompressed kernel plus an additional 128 KiB.
1873 Platforms which normally make use of ROM-able zImage formats
1874 normally set this to a suitable value in their defconfig file.
1876 If ZBOOT_ROM is not enabled, this has no effect.
1879 bool "Compressed boot loader in ROM/flash"
1880 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1882 Say Y here if you intend to execute your compressed kernel image
1883 (zImage) directly from ROM or flash. If unsure, say N.
1886 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1887 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1888 default ZBOOT_ROM_NONE
1890 Include experimental SD/MMC loading code in the ROM-able zImage.
1891 With this enabled it is possible to write the the ROM-able zImage
1892 kernel image to an MMC or SD card and boot the kernel straight
1893 from the reset vector. At reset the processor Mask ROM will load
1894 the first part of the the ROM-able zImage which in turn loads the
1895 rest the kernel image to RAM.
1897 config ZBOOT_ROM_NONE
1898 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1900 Do not load image from SD or MMC
1902 config ZBOOT_ROM_MMCIF
1903 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1905 Load image from MMCIF hardware block.
1907 config ZBOOT_ROM_SH_MOBILE_SDHI
1908 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1910 Load image from SDHI hardware block
1914 config ARM_APPENDED_DTB
1915 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1916 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1918 With this option, the boot code will look for a device tree binary
1919 (DTB) appended to zImage
1920 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1922 This is meant as a backward compatibility convenience for those
1923 systems with a bootloader that can't be upgraded to accommodate
1924 the documented boot protocol using a device tree.
1926 Beware that there is very little in terms of protection against
1927 this option being confused by leftover garbage in memory that might
1928 look like a DTB header after a reboot if no actual DTB is appended
1929 to zImage. Do not leave this option active in a production kernel
1930 if you don't intend to always append a DTB. Proper passing of the
1931 location into r2 of a bootloader provided DTB is always preferable
1934 config ARM_ATAG_DTB_COMPAT
1935 bool "Supplement the appended DTB with traditional ATAG information"
1936 depends on ARM_APPENDED_DTB
1938 Some old bootloaders can't be updated to a DTB capable one, yet
1939 they provide ATAGs with memory configuration, the ramdisk address,
1940 the kernel cmdline string, etc. Such information is dynamically
1941 provided by the bootloader and can't always be stored in a static
1942 DTB. To allow a device tree enabled kernel to be used with such
1943 bootloaders, this option allows zImage to extract the information
1944 from the ATAG list and store it at run time into the appended DTB.
1947 string "Default kernel command string"
1950 On some architectures (EBSA110 and CATS), there is currently no way
1951 for the boot loader to pass arguments to the kernel. For these
1952 architectures, you should supply some command-line options at build
1953 time by entering them here. As a minimum, you should specify the
1954 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1957 prompt "Kernel command line type" if CMDLINE != ""
1958 default CMDLINE_FROM_BOOTLOADER
1960 config CMDLINE_FROM_BOOTLOADER
1961 bool "Use bootloader kernel arguments if available"
1963 Uses the command-line options passed by the boot loader. If
1964 the boot loader doesn't provide any, the default kernel command
1965 string provided in CMDLINE will be used.
1967 config CMDLINE_EXTEND
1968 bool "Extend bootloader kernel arguments"
1970 The command-line arguments provided by the boot loader will be
1971 appended to the default kernel command string.
1973 config CMDLINE_FORCE
1974 bool "Always use the default kernel command string"
1976 Always use the default kernel command string, even if the boot
1977 loader passes other arguments to the kernel.
1978 This is useful if you cannot or don't want to change the
1979 command-line options your boot loader passes to the kernel.
1983 bool "Kernel Execute-In-Place from ROM"
1984 depends on !ZBOOT_ROM
1986 Execute-In-Place allows the kernel to run from non-volatile storage
1987 directly addressable by the CPU, such as NOR flash. This saves RAM
1988 space since the text section of the kernel is not loaded from flash
1989 to RAM. Read-write sections, such as the data section and stack,
1990 are still copied to RAM. The XIP kernel is not compressed since
1991 it has to run directly from flash, so it will take more space to
1992 store it. The flash address used to link the kernel object files,
1993 and for storing it, is configuration dependent. Therefore, if you
1994 say Y here, you must know the proper physical address where to
1995 store the kernel image depending on your own flash memory usage.
1997 Also note that the make target becomes "make xipImage" rather than
1998 "make zImage" or "make Image". The final kernel binary to put in
1999 ROM memory will be arch/arm/boot/xipImage.
2003 config XIP_PHYS_ADDR
2004 hex "XIP Kernel Physical Location"
2005 depends on XIP_KERNEL
2006 default "0x00080000"
2008 This is the physical address in your flash memory the kernel will
2009 be linked for and stored to. This address is dependent on your
2013 bool "Kexec system call (EXPERIMENTAL)"
2014 depends on EXPERIMENTAL
2016 kexec is a system call that implements the ability to shutdown your
2017 current kernel, and to start another kernel. It is like a reboot
2018 but it is independent of the system firmware. And like a reboot
2019 you can start any kernel with it, not just Linux.
2021 It is an ongoing process to be certain the hardware in a machine
2022 is properly shutdown, so do not be surprised if this code does not
2023 initially work for you. It may help to enable device hotplugging
2027 bool "Export atags in procfs"
2031 Should the atags used to boot the kernel be exported in an "atags"
2032 file in procfs. Useful with kexec.
2035 bool "Build kdump crash kernel (EXPERIMENTAL)"
2036 depends on EXPERIMENTAL
2038 Generate crash dump after being started by kexec. This should
2039 be normally only set in special crash dump kernels which are
2040 loaded in the main kernel with kexec-tools into a specially
2041 reserved region and then later executed after a crash by
2042 kdump/kexec. The crash dump kernel must be compiled to a
2043 memory address not used by the main kernel
2045 For more details see Documentation/kdump/kdump.txt
2047 config AUTO_ZRELADDR
2048 bool "Auto calculation of the decompressed kernel image address"
2049 depends on !ZBOOT_ROM && !ARCH_U300
2051 ZRELADDR is the physical address where the decompressed kernel
2052 image will be placed. If AUTO_ZRELADDR is selected, the address
2053 will be determined at run-time by masking the current IP with
2054 0xf8000000. This assumes the zImage being placed in the first 128MB
2055 from start of memory.
2059 menu "CPU Power Management"
2063 source "drivers/cpufreq/Kconfig"
2066 tristate "CPUfreq driver for i.MX CPUs"
2067 depends on ARCH_MXC && CPU_FREQ
2068 select CPU_FREQ_TABLE
2070 This enables the CPUfreq driver for i.MX CPUs.
2072 config CPU_FREQ_SA1100
2075 config CPU_FREQ_SA1110
2078 config CPU_FREQ_INTEGRATOR
2079 tristate "CPUfreq driver for ARM Integrator CPUs"
2080 depends on ARCH_INTEGRATOR && CPU_FREQ
2083 This enables the CPUfreq driver for ARM Integrator CPUs.
2085 For details, take a look at <file:Documentation/cpu-freq>.
2091 depends on CPU_FREQ && ARCH_PXA && PXA25x
2093 select CPU_FREQ_TABLE
2094 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2099 Internal configuration node for common cpufreq on Samsung SoC
2101 config CPU_FREQ_S3C24XX
2102 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2103 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2106 This enables the CPUfreq driver for the Samsung S3C24XX family
2109 For details, take a look at <file:Documentation/cpu-freq>.
2113 config CPU_FREQ_S3C24XX_PLL
2114 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2115 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2117 Compile in support for changing the PLL frequency from the
2118 S3C24XX series CPUfreq driver. The PLL takes time to settle
2119 after a frequency change, so by default it is not enabled.
2121 This also means that the PLL tables for the selected CPU(s) will
2122 be built which may increase the size of the kernel image.
2124 config CPU_FREQ_S3C24XX_DEBUG
2125 bool "Debug CPUfreq Samsung driver core"
2126 depends on CPU_FREQ_S3C24XX
2128 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2130 config CPU_FREQ_S3C24XX_IODEBUG
2131 bool "Debug CPUfreq Samsung driver IO timing"
2132 depends on CPU_FREQ_S3C24XX
2134 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2136 config CPU_FREQ_S3C24XX_DEBUGFS
2137 bool "Export debugfs for CPUFreq"
2138 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2140 Export status information via debugfs.
2144 source "drivers/cpuidle/Kconfig"
2148 menu "Floating point emulation"
2150 comment "At least one emulation must be selected"
2153 bool "NWFPE math emulation"
2154 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2156 Say Y to include the NWFPE floating point emulator in the kernel.
2157 This is necessary to run most binaries. Linux does not currently
2158 support floating point hardware so you need to say Y here even if
2159 your machine has an FPA or floating point co-processor podule.
2161 You may say N here if you are going to load the Acorn FPEmulator
2162 early in the bootup.
2165 bool "Support extended precision"
2166 depends on FPE_NWFPE
2168 Say Y to include 80-bit support in the kernel floating-point
2169 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2170 Note that gcc does not generate 80-bit operations by default,
2171 so in most cases this option only enlarges the size of the
2172 floating point emulator without any good reason.
2174 You almost surely want to say N here.
2177 bool "FastFPE math emulation (EXPERIMENTAL)"
2178 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2180 Say Y here to include the FAST floating point emulator in the kernel.
2181 This is an experimental much faster emulator which now also has full
2182 precision for the mantissa. It does not support any exceptions.
2183 It is very simple, and approximately 3-6 times faster than NWFPE.
2185 It should be sufficient for most programs. It may be not suitable
2186 for scientific calculations, but you have to check this for yourself.
2187 If you do not feel you need a faster FP emulation you should better
2191 bool "VFP-format floating point maths"
2192 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2194 Say Y to include VFP support code in the kernel. This is needed
2195 if your hardware includes a VFP unit.
2197 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2198 release notes and additional status information.
2200 Say N if your target does not have VFP hardware.
2208 bool "Advanced SIMD (NEON) Extension support"
2209 depends on VFPv3 && CPU_V7
2211 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2216 menu "Userspace binary formats"
2218 source "fs/Kconfig.binfmt"
2221 tristate "RISC OS personality"
2224 Say Y here to include the kernel code necessary if you want to run
2225 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2226 experimental; if this sounds frightening, say N and sleep in peace.
2227 You can also say M here to compile this support as a module (which
2228 will be called arthur).
2232 menu "Power management options"
2234 source "kernel/power/Kconfig"
2236 config ARCH_SUSPEND_POSSIBLE
2237 depends on !ARCH_S5PC100
2238 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2239 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2242 config ARM_CPU_SUSPEND
2247 source "net/Kconfig"
2249 source "drivers/Kconfig"
2253 source "arch/arm/Kconfig.debug"
2255 source "security/Kconfig"
2257 source "crypto/Kconfig"
2259 source "lib/Kconfig"