5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_CONTIGUOUS if MMU
11 select SYS_SUPPORTS_APM_EMULATION
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_KPROBES if !XIP_KERNEL
16 select HAVE_KRETPROBES if (HAVE_KPROBES)
17 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
18 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
19 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
20 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
26 select HAVE_PERF_EVENTS
27 select PERF_USE_VMALLOC
28 select HAVE_REGS_AND_STACK_ACCESS_API
29 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_GENERIC_HARDIRQS
32 select HAVE_SPARSE_IRQ
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
36 The ARM series is a line of low-power-consumption RISC chip designs
37 licensed by ARM Ltd and targeted at embedded applications and
38 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
39 manufactured, but legacy ARM-based PC hardware remains popular in
40 Europe. There is an ARM Linux project with a web page at
41 <http://www.arm.linux.org.uk/>.
43 config ARM_HAS_SG_CHAIN
46 config NEED_SG_DMA_LENGTH
49 config ARM_DMA_USE_IOMMU
50 select NEED_SG_DMA_LENGTH
51 select ARM_HAS_SG_CHAIN
60 config SYS_SUPPORTS_APM_EMULATION
63 config HAVE_SCHED_CLOCK
69 config ARCH_USES_GETTIMEOFFSET
73 config GENERIC_CLOCKEVENTS
76 config GENERIC_CLOCKEVENTS_BROADCAST
78 depends on GENERIC_CLOCKEVENTS
87 select GENERIC_ALLOCATOR
98 The Extended Industry Standard Architecture (EISA) bus was
99 developed as an open alternative to the IBM MicroChannel bus.
101 The EISA bus provided some of the features of the IBM MicroChannel
102 bus while maintaining backward compatibility with cards made for
103 the older ISA bus. The EISA bus saw limited use between 1988 and
104 1995 when it was made obsolete by the PCI bus.
106 Say Y here if you are building a kernel for an EISA-based machine.
116 MicroChannel Architecture is found in some IBM PS/2 machines and
117 laptops. It is a bus system similar to PCI or ISA. See
118 <file:Documentation/mca.txt> (and especially the web page given
119 there) before attempting to build an MCA bus kernel.
121 config STACKTRACE_SUPPORT
125 config HAVE_LATENCYTOP_SUPPORT
130 config LOCKDEP_SUPPORT
134 config TRACE_IRQFLAGS_SUPPORT
138 config HARDIRQS_SW_RESEND
142 config GENERIC_IRQ_PROBE
146 config GENERIC_LOCKBREAK
149 depends on SMP && PREEMPT
151 config RWSEM_GENERIC_SPINLOCK
155 config RWSEM_XCHGADD_ALGORITHM
158 config ARCH_HAS_ILOG2_U32
161 config ARCH_HAS_ILOG2_U64
164 config ARCH_HAS_CPUFREQ
167 Internal node to signify that the ARCH has CPUFREQ support
168 and that the relevant menu configurations are displayed for
171 config ARCH_HAS_CPU_IDLE_WAIT
174 config GENERIC_HWEIGHT
178 config GENERIC_CALIBRATE_DELAY
182 config ARCH_MAY_HAVE_PC_FDC
188 config NEED_DMA_MAP_STATE
191 config ARCH_HAS_DMA_SET_COHERENT_MASK
194 config GENERIC_ISA_DMA
205 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
206 default DRAM_BASE if REMAP_VECTORS_TO_RAM
209 The base address of exception vectors.
211 config ARM_PATCH_PHYS_VIRT
212 bool "Patch physical to virtual translations at runtime" if EMBEDDED
214 depends on !XIP_KERNEL && MMU
215 depends on !ARCH_REALVIEW || !SPARSEMEM
217 Patch phys-to-virt and virt-to-phys translation functions at
218 boot and module load time according to the position of the
219 kernel in system memory.
221 This can only be used with non-XIP MMU kernels where the base
222 of physical memory is at a 16MB boundary.
224 Only disable this option if you know that you do not require
225 this feature (eg, building a kernel for a single machine) and
226 you need to shrink the kernel to the minimal size.
228 config NEED_MACH_MEMORY_H
231 Select this when mach/memory.h is required to provide special
232 definitions for this platform. The need for mach/memory.h should
233 be avoided when possible.
236 hex "Physical address of main memory" if MMU
237 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
238 default DRAM_BASE if !MMU
240 Please provide the physical address corresponding to the
241 location of main memory in your system.
247 source "init/Kconfig"
249 source "kernel/Kconfig.freezer"
254 bool "MMU-based Paged Memory Management Support"
257 Select if you want MMU-based virtualised addressing space
258 support by paged memory management. If unsure, say 'Y'.
261 # The "ARM system type" choice list is ordered alphabetically by option
262 # text. Please add new entries in the option alphabetic order.
265 prompt "ARM system type"
266 default ARCH_VERSATILE
268 config ARCH_INTEGRATOR
269 bool "ARM Ltd. Integrator family"
271 select ARCH_HAS_CPUFREQ
273 select HAVE_MACH_CLKDEV
275 select GENERIC_CLOCKEVENTS
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_FPGA_IRQ
278 select NEED_MACH_MEMORY_H
280 Support for ARM's Integrator platform.
283 bool "ARM Ltd. RealView family"
286 select HAVE_MACH_CLKDEV
288 select GENERIC_CLOCKEVENTS
289 select ARCH_WANT_OPTIONAL_GPIOLIB
290 select PLAT_VERSATILE
291 select PLAT_VERSATILE_CLCD
292 select ARM_TIMER_SP804
293 select GPIO_PL061 if GPIOLIB
294 select NEED_MACH_MEMORY_H
296 This enables support for ARM Ltd RealView boards.
298 config ARCH_VERSATILE
299 bool "ARM Ltd. Versatile family"
303 select HAVE_MACH_CLKDEV
305 select GENERIC_CLOCKEVENTS
306 select ARCH_WANT_OPTIONAL_GPIOLIB
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
309 select PLAT_VERSATILE_FPGA_IRQ
310 select ARM_TIMER_SP804
312 This enables support for ARM Ltd Versatile board.
315 bool "ARM Ltd. Versatile Express family"
316 select ARCH_WANT_OPTIONAL_GPIOLIB
318 select ARM_TIMER_SP804
320 select HAVE_MACH_CLKDEV
321 select GENERIC_CLOCKEVENTS
323 select HAVE_PATA_PLATFORM
325 select PLAT_VERSATILE
326 select PLAT_VERSATILE_CLCD
328 This enables support for the ARM Ltd Versatile Express boards.
332 select ARCH_REQUIRE_GPIOLIB
336 This enables support for systems based on the Atmel AT91RM9200,
337 AT91SAM9 and AT91CAP9 processors.
340 bool "Broadcom BCMRING"
344 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 Support for Broadcom's BCMRing platform.
352 bool "Calxeda Highbank-based"
353 select ARCH_WANT_OPTIONAL_GPIOLIB
356 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
363 Support for the Calxeda Highbank SoC based boards.
366 bool "Cirrus Logic CLPS711x/EP721x-based"
368 select ARCH_USES_GETTIMEOFFSET
369 select NEED_MACH_MEMORY_H
371 Support for Cirrus Logic 711x/721x based boards.
374 bool "Cavium Networks CNS3XXX family"
376 select GENERIC_CLOCKEVENTS
378 select MIGHT_HAVE_PCI
379 select PCI_DOMAINS if PCI
381 Support for Cavium Networks CNS3XXX platform.
384 bool "Cortina Systems Gemini"
386 select ARCH_REQUIRE_GPIOLIB
387 select ARCH_USES_GETTIMEOFFSET
389 Support for the Cortina Systems Gemini family SoCs
392 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
395 select GENERIC_CLOCKEVENTS
397 select GENERIC_IRQ_CHIP
401 Support for CSR SiRFSoC ARM Cortex A9 Platform
408 select ARCH_USES_GETTIMEOFFSET
409 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_REQUIRE_GPIOLIB
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_USES_GETTIMEOFFSET
425 select NEED_MACH_MEMORY_H
427 This enables support for the Cirrus EP93xx series of CPUs.
429 config ARCH_FOOTBRIDGE
433 select GENERIC_CLOCKEVENTS
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_IRQ_CHIP
447 select HAVE_SCHED_CLOCK
448 select MULTI_IRQ_HANDLER
450 Support for Freescale MXC/iMX-based family of processors
453 bool "Freescale MXS-based"
454 select GENERIC_CLOCKEVENTS
455 select ARCH_REQUIRE_GPIOLIB
459 Support for Freescale MXS-based family of processors
462 bool "Hilscher NetX based"
466 select GENERIC_CLOCKEVENTS
468 This enables support for systems based on the Hilscher NetX Soc
471 bool "Hynix HMS720x-based"
474 select ARCH_USES_GETTIMEOFFSET
476 This enables support for systems based on the Hynix HMS720x
484 select ARCH_SUPPORTS_MSI
486 select NEED_MACH_MEMORY_H
488 Support for Intel's IOP13XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
498 Support for Intel's 80219 and IOP32X (XScale) family of
507 select ARCH_REQUIRE_GPIOLIB
509 Support for Intel's IOP33X (XScale) family of processors.
516 select ARCH_USES_GETTIMEOFFSET
517 select NEED_MACH_MEMORY_H
519 Support for Intel's IXP23xx (XScale) family of processors.
522 bool "IXP2400/2800-based"
526 select ARCH_USES_GETTIMEOFFSET
527 select NEED_MACH_MEMORY_H
529 Support for Intel's IXP2400/2800 (XScale) family of processors.
534 select ARCH_HAS_DMA_SET_COHERENT_MASK
537 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
539 select HAVE_SCHED_CLOCK
540 select MIGHT_HAVE_PCI
541 select DMABOUNCE if PCI
543 Support for Intel's IXP4XX (XScale) family of processors.
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 Support for the Marvell Dove SoC 88AP510
556 bool "Marvell Kirkwood"
560 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
564 Support for the following Marvell Kirkwood series SoCs:
565 88F6180, 88F6192 and 88F6281.
571 select ARCH_REQUIRE_GPIOLIB
574 select USB_ARCH_HAS_OHCI
576 select GENERIC_CLOCKEVENTS
578 Support for the NXP LPC32XX family of processors
581 bool "Marvell MV78xx0"
584 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_CLOCKEVENTS
588 Support for the following Marvell MV78xx0 series SoCs:
596 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
600 Support for the following Marvell Orion 5x series SoCs:
601 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
602 Orion-2 (5281), Orion-1-90 (6183).
605 bool "Marvell PXA168/910/MMP2"
607 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select HAVE_SCHED_CLOCK
614 select GENERIC_ALLOCATOR
616 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
619 bool "Micrel/Kendin KS8695"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARCH_USES_GETTIMEOFFSET
623 select NEED_MACH_MEMORY_H
625 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
626 System-on-Chip devices.
629 bool "Nuvoton W90X900 CPU"
631 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
636 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
637 At present, the w90x900 has been renamed nuc900, regarding
638 the ARM series product line, you can login the following
639 link address to know more.
641 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
642 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
648 select GENERIC_CLOCKEVENTS
651 select HAVE_SCHED_CLOCK
652 select ARCH_HAS_CPUFREQ
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
657 config ARCH_PICOXCELL
658 bool "Picochip picoXcell"
659 select ARCH_REQUIRE_GPIOLIB
660 select ARM_PATCH_PHYS_VIRT
664 select GENERIC_CLOCKEVENTS
666 select HAVE_SCHED_CLOCK
671 This enables support for systems based on the Picochip picoXcell
672 family of Femtocell devices. The picoxcell support requires device tree
676 bool "Philips Nexperia PNX4008 Mobile"
679 select ARCH_USES_GETTIMEOFFSET
681 This enables support for Philips PNX4008 mobile platform.
684 bool "PXA2xx/PXA3xx-based"
687 select ARCH_HAS_CPUFREQ
690 select ARCH_REQUIRE_GPIOLIB
691 select GENERIC_CLOCKEVENTS
692 select HAVE_SCHED_CLOCK
697 select MULTI_IRQ_HANDLER
698 select ARM_CPU_SUSPEND if PM
701 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
706 select GENERIC_CLOCKEVENTS
707 select ARCH_REQUIRE_GPIOLIB
710 Support for Qualcomm MSM/QSD based systems. This runs on the
711 apps processor of the MSM/QSD and depends on a shared memory
712 interface to the modem processor which runs the baseband
713 stack and controls some vital subsystems
714 (clock and power control, etc).
717 bool "Renesas SH-Mobile / R-Mobile"
720 select HAVE_MACH_CLKDEV
721 select GENERIC_CLOCKEVENTS
724 select MULTI_IRQ_HANDLER
725 select PM_GENERIC_DOMAINS if PM
726 select NEED_MACH_MEMORY_H
728 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
735 select ARCH_MAY_HAVE_PC_FDC
736 select HAVE_PATA_PLATFORM
739 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_USES_GETTIMEOFFSET
742 select NEED_MACH_MEMORY_H
744 On the Acorn Risc-PC, Linux can support the internal IDE disk and
745 CD-ROM interface, serial and parallel port, and the floppy drive.
752 select ARCH_SPARSEMEM_ENABLE
754 select ARCH_HAS_CPUFREQ
756 select GENERIC_CLOCKEVENTS
758 select HAVE_SCHED_CLOCK
760 select ARCH_REQUIRE_GPIOLIB
762 select NEED_MACH_MEMORY_H
764 Support for StrongARM 11x0 based boards.
767 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
769 select ARCH_HAS_CPUFREQ
772 select ARCH_USES_GETTIMEOFFSET
773 select HAVE_S3C2410_I2C if I2C
775 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
776 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
777 the Samsung SMDK2410 development board (and derivatives).
779 Note, the S3C2416 and the S3C2450 are so close that they even share
780 the same SoC ID code. This means that there is no separate machine
781 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
784 bool "Samsung S3C64XX"
792 select ARCH_USES_GETTIMEOFFSET
793 select ARCH_HAS_CPUFREQ
794 select ARCH_REQUIRE_GPIOLIB
795 select SAMSUNG_CLKSRC
796 select SAMSUNG_IRQ_VIC_TIMER
797 select S3C_GPIO_TRACK
799 select USB_ARCH_HAS_OHCI
800 select SAMSUNG_GPIOLIB_4BIT
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 Samsung S3C64XX series based systems
807 bool "Samsung S5P6440 S5P6450"
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select GENERIC_CLOCKEVENTS
815 select HAVE_SCHED_CLOCK
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
819 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
823 bool "Samsung S5PC100"
828 select ARM_L1_CACHE_SHIFT_6
829 select ARCH_USES_GETTIMEOFFSET
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C_RTC if RTC_CLASS
832 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 Samsung S5PC100 series based systems
837 bool "Samsung S5PV210/S5PC110"
839 select ARCH_SPARSEMEM_ENABLE
840 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARM_L1_CACHE_SHIFT_6
846 select ARCH_HAS_CPUFREQ
847 select GENERIC_CLOCKEVENTS
848 select HAVE_SCHED_CLOCK
849 select HAVE_S3C2410_I2C if I2C
850 select HAVE_S3C_RTC if RTC_CLASS
851 select HAVE_S3C2410_WATCHDOG if WATCHDOG
852 select NEED_MACH_MEMORY_H
854 Samsung S5PV210/S5PC110 series based systems
857 bool "SAMSUNG EXYNOS"
859 select ARCH_SPARSEMEM_ENABLE
860 select ARCH_HAS_HOLES_MEMORYMODEL
864 select ARCH_HAS_CPUFREQ
865 select GENERIC_CLOCKEVENTS
866 select HAVE_S3C_RTC if RTC_CLASS
867 select HAVE_S3C2410_I2C if I2C
868 select HAVE_S3C2410_WATCHDOG if WATCHDOG
869 select NEED_MACH_MEMORY_H
871 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
880 select ARCH_USES_GETTIMEOFFSET
881 select NEED_MACH_MEMORY_H
883 Support for the StrongARM based Digital DNARD machine, also known
884 as "Shark" (<http://www.shark-linux.de/shark.html>).
887 bool "Telechips TCC ARM926-based systems"
892 select GENERIC_CLOCKEVENTS
894 Support for Telechips TCC ARM926-based systems.
897 bool "ST-Ericsson U300 Series"
901 select HAVE_SCHED_CLOCK
904 select ARM_PATCH_PHYS_VIRT
906 select GENERIC_CLOCKEVENTS
908 select HAVE_MACH_CLKDEV
910 select ARCH_REQUIRE_GPIOLIB
911 select NEED_MACH_MEMORY_H
913 Support for ST-Ericsson U300 series mobile platforms.
916 bool "ST-Ericsson U8500 Series"
919 select GENERIC_CLOCKEVENTS
921 select ARCH_REQUIRE_GPIOLIB
922 select ARCH_HAS_CPUFREQ
924 Support for ST-Ericsson's Ux500 architecture
927 bool "STMicroelectronics Nomadik"
932 select GENERIC_CLOCKEVENTS
933 select ARCH_REQUIRE_GPIOLIB
935 Support for the Nomadik platform by ST-Ericsson
939 select GENERIC_CLOCKEVENTS
940 select ARCH_REQUIRE_GPIOLIB
944 select GENERIC_ALLOCATOR
945 select GENERIC_IRQ_CHIP
946 select ARCH_HAS_HOLES_MEMORYMODEL
948 Support for TI's DaVinci platform.
953 select ARCH_REQUIRE_GPIOLIB
954 select ARCH_HAS_CPUFREQ
956 select GENERIC_CLOCKEVENTS
957 select HAVE_SCHED_CLOCK
958 select ARCH_HAS_HOLES_MEMORYMODEL
960 Support for TI's OMAP platform (OMAP1/2/3/4).
965 select ARCH_REQUIRE_GPIOLIB
968 select GENERIC_CLOCKEVENTS
971 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
974 bool "VIA/WonderMedia 85xx"
977 select ARCH_HAS_CPUFREQ
978 select GENERIC_CLOCKEVENTS
979 select ARCH_REQUIRE_GPIOLIB
982 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
985 bool "Xilinx Zynq ARM Cortex A9 Platform"
987 select GENERIC_CLOCKEVENTS
994 Support for Xilinx Zynq ARM Cortex A9 Platform
998 # This is sorted alphabetically by mach-* pathname. However, plat-*
999 # Kconfigs may be included either alphabetically (according to the
1000 # plat- suffix) or along side the corresponding mach-* source.
1002 source "arch/arm/mach-at91/Kconfig"
1004 source "arch/arm/mach-bcmring/Kconfig"
1006 source "arch/arm/mach-clps711x/Kconfig"
1008 source "arch/arm/mach-cns3xxx/Kconfig"
1010 source "arch/arm/mach-davinci/Kconfig"
1012 source "arch/arm/mach-dove/Kconfig"
1014 source "arch/arm/mach-ep93xx/Kconfig"
1016 source "arch/arm/mach-footbridge/Kconfig"
1018 source "arch/arm/mach-gemini/Kconfig"
1020 source "arch/arm/mach-h720x/Kconfig"
1022 source "arch/arm/mach-integrator/Kconfig"
1024 source "arch/arm/mach-iop32x/Kconfig"
1026 source "arch/arm/mach-iop33x/Kconfig"
1028 source "arch/arm/mach-iop13xx/Kconfig"
1030 source "arch/arm/mach-ixp4xx/Kconfig"
1032 source "arch/arm/mach-ixp2000/Kconfig"
1034 source "arch/arm/mach-ixp23xx/Kconfig"
1036 source "arch/arm/mach-kirkwood/Kconfig"
1038 source "arch/arm/mach-ks8695/Kconfig"
1040 source "arch/arm/mach-lpc32xx/Kconfig"
1042 source "arch/arm/mach-msm/Kconfig"
1044 source "arch/arm/mach-mv78xx0/Kconfig"
1046 source "arch/arm/plat-mxc/Kconfig"
1048 source "arch/arm/mach-mxs/Kconfig"
1050 source "arch/arm/mach-netx/Kconfig"
1052 source "arch/arm/mach-nomadik/Kconfig"
1053 source "arch/arm/plat-nomadik/Kconfig"
1055 source "arch/arm/plat-omap/Kconfig"
1057 source "arch/arm/mach-omap1/Kconfig"
1059 source "arch/arm/mach-omap2/Kconfig"
1061 source "arch/arm/mach-orion5x/Kconfig"
1063 source "arch/arm/mach-pxa/Kconfig"
1064 source "arch/arm/plat-pxa/Kconfig"
1066 source "arch/arm/mach-mmp/Kconfig"
1068 source "arch/arm/mach-realview/Kconfig"
1070 source "arch/arm/mach-sa1100/Kconfig"
1072 source "arch/arm/plat-samsung/Kconfig"
1073 source "arch/arm/plat-s3c24xx/Kconfig"
1074 source "arch/arm/plat-s5p/Kconfig"
1076 source "arch/arm/plat-spear/Kconfig"
1078 source "arch/arm/plat-tcc/Kconfig"
1081 source "arch/arm/mach-s3c2410/Kconfig"
1082 source "arch/arm/mach-s3c2412/Kconfig"
1083 source "arch/arm/mach-s3c2416/Kconfig"
1084 source "arch/arm/mach-s3c2440/Kconfig"
1085 source "arch/arm/mach-s3c2443/Kconfig"
1089 source "arch/arm/mach-s3c64xx/Kconfig"
1092 source "arch/arm/mach-s5p64x0/Kconfig"
1094 source "arch/arm/mach-s5pc100/Kconfig"
1096 source "arch/arm/mach-s5pv210/Kconfig"
1098 source "arch/arm/mach-exynos/Kconfig"
1100 source "arch/arm/mach-shmobile/Kconfig"
1102 source "arch/arm/mach-tegra/Kconfig"
1104 source "arch/arm/mach-u300/Kconfig"
1106 source "arch/arm/mach-ux500/Kconfig"
1108 source "arch/arm/mach-versatile/Kconfig"
1110 source "arch/arm/mach-vexpress/Kconfig"
1111 source "arch/arm/plat-versatile/Kconfig"
1113 source "arch/arm/mach-vt8500/Kconfig"
1115 source "arch/arm/mach-w90x900/Kconfig"
1117 # Definitions to make life easier
1123 select GENERIC_CLOCKEVENTS
1124 select HAVE_SCHED_CLOCK
1129 select GENERIC_IRQ_CHIP
1130 select HAVE_SCHED_CLOCK
1135 config PLAT_VERSATILE
1138 config ARM_TIMER_SP804
1142 source arch/arm/mm/Kconfig
1145 bool "Enable iWMMXt support"
1146 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1147 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1149 Enable support for iWMMXt context switching at run time if
1150 running on a CPU that supports it.
1152 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1155 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1159 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1160 (!ARCH_OMAP3 || OMAP3_EMU)
1164 config MULTI_IRQ_HANDLER
1167 Allow each machine to specify it's own IRQ handler at run time.
1170 source "arch/arm/Kconfig-nommu"
1173 config ARM_ERRATA_326103
1174 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1177 Executing a SWP instruction to read-only memory does not set bit 11
1178 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1179 treat the access as a read, preventing a COW from occurring and
1180 causing the faulting task to livelock.
1182 config ARM_ERRATA_411920
1183 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1184 depends on CPU_V6 || CPU_V6K
1186 Invalidation of the Instruction Cache operation can
1187 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1188 It does not affect the MPCore. This option enables the ARM Ltd.
1189 recommended workaround.
1191 config ARM_ERRATA_430973
1192 bool "ARM errata: Stale prediction on replaced interworking branch"
1195 This option enables the workaround for the 430973 Cortex-A8
1196 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1197 interworking branch is replaced with another code sequence at the
1198 same virtual address, whether due to self-modifying code or virtual
1199 to physical address re-mapping, Cortex-A8 does not recover from the
1200 stale interworking branch prediction. This results in Cortex-A8
1201 executing the new code sequence in the incorrect ARM or Thumb state.
1202 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1203 and also flushes the branch target cache at every context switch.
1204 Note that setting specific bits in the ACTLR register may not be
1205 available in non-secure mode.
1207 config ARM_ERRATA_458693
1208 bool "ARM errata: Processor deadlock when a false hazard is created"
1211 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1212 erratum. For very specific sequences of memory operations, it is
1213 possible for a hazard condition intended for a cache line to instead
1214 be incorrectly associated with a different cache line. This false
1215 hazard might then cause a processor deadlock. The workaround enables
1216 the L1 caching of the NEON accesses and disables the PLD instruction
1217 in the ACTLR register. Note that setting specific bits in the ACTLR
1218 register may not be available in non-secure mode.
1220 config ARM_ERRATA_460075
1221 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1224 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1225 erratum. Any asynchronous access to the L2 cache may encounter a
1226 situation in which recent store transactions to the L2 cache are lost
1227 and overwritten with stale memory contents from external memory. The
1228 workaround disables the write-allocate mode for the L2 cache via the
1229 ACTLR register. Note that setting specific bits in the ACTLR register
1230 may not be available in non-secure mode.
1232 config ARM_ERRATA_742230
1233 bool "ARM errata: DMB operation may be faulty"
1234 depends on CPU_V7 && SMP
1236 This option enables the workaround for the 742230 Cortex-A9
1237 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1238 between two write operations may not ensure the correct visibility
1239 ordering of the two writes. This workaround sets a specific bit in
1240 the diagnostic register of the Cortex-A9 which causes the DMB
1241 instruction to behave as a DSB, ensuring the correct behaviour of
1244 config ARM_ERRATA_742231
1245 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1246 depends on CPU_V7 && SMP
1248 This option enables the workaround for the 742231 Cortex-A9
1249 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1250 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1251 accessing some data located in the same cache line, may get corrupted
1252 data due to bad handling of the address hazard when the line gets
1253 replaced from one of the CPUs at the same time as another CPU is
1254 accessing it. This workaround sets specific bits in the diagnostic
1255 register of the Cortex-A9 which reduces the linefill issuing
1256 capabilities of the processor.
1258 config PL310_ERRATA_588369
1259 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1260 depends on CACHE_L2X0
1262 The PL310 L2 cache controller implements three types of Clean &
1263 Invalidate maintenance operations: by Physical Address
1264 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1265 They are architecturally defined to behave as the execution of a
1266 clean operation followed immediately by an invalidate operation,
1267 both performing to the same memory location. This functionality
1268 is not correctly implemented in PL310 as clean lines are not
1269 invalidated as a result of these operations.
1271 config ARM_ERRATA_720789
1272 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1275 This option enables the workaround for the 720789 Cortex-A9 (prior to
1276 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1277 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1278 As a consequence of this erratum, some TLB entries which should be
1279 invalidated are not, resulting in an incoherency in the system page
1280 tables. The workaround changes the TLB flushing routines to invalidate
1281 entries regardless of the ASID.
1283 config PL310_ERRATA_727915
1284 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1285 depends on CACHE_L2X0
1287 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1288 operation (offset 0x7FC). This operation runs in background so that
1289 PL310 can handle normal accesses while it is in progress. Under very
1290 rare circumstances, due to this erratum, write data can be lost when
1291 PL310 treats a cacheable write transaction during a Clean &
1292 Invalidate by Way operation.
1294 config ARM_ERRATA_743622
1295 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1298 This option enables the workaround for the 743622 Cortex-A9
1299 (r2p*) erratum. Under very rare conditions, a faulty
1300 optimisation in the Cortex-A9 Store Buffer may lead to data
1301 corruption. This workaround sets a specific bit in the diagnostic
1302 register of the Cortex-A9 which disables the Store Buffer
1303 optimisation, preventing the defect from occurring. This has no
1304 visible impact on the overall performance or power consumption of the
1307 config ARM_ERRATA_751472
1308 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1311 This option enables the workaround for the 751472 Cortex-A9 (prior
1312 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1313 completion of a following broadcasted operation if the second
1314 operation is received by a CPU before the ICIALLUIS has completed,
1315 potentially leading to corrupted entries in the cache or TLB.
1317 config PL310_ERRATA_753970
1318 bool "PL310 errata: cache sync operation may be faulty"
1319 depends on CACHE_PL310
1321 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1323 Under some condition the effect of cache sync operation on
1324 the store buffer still remains when the operation completes.
1325 This means that the store buffer is always asked to drain and
1326 this prevents it from merging any further writes. The workaround
1327 is to replace the normal offset of cache sync operation (0x730)
1328 by another offset targeting an unmapped PL310 register 0x740.
1329 This has the same effect as the cache sync operation: store buffer
1330 drain and waiting for all buffers empty.
1332 config ARM_ERRATA_754322
1333 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1336 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1337 r3p*) erratum. A speculative memory access may cause a page table walk
1338 which starts prior to an ASID switch but completes afterwards. This
1339 can populate the micro-TLB with a stale entry which may be hit with
1340 the new ASID. This workaround places two dsb instructions in the mm
1341 switching code so that no page table walks can cross the ASID switch.
1343 config ARM_ERRATA_754327
1344 bool "ARM errata: no automatic Store Buffer drain"
1345 depends on CPU_V7 && SMP
1347 This option enables the workaround for the 754327 Cortex-A9 (prior to
1348 r2p0) erratum. The Store Buffer does not have any automatic draining
1349 mechanism and therefore a livelock may occur if an external agent
1350 continuously polls a memory location waiting to observe an update.
1351 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1352 written polling loops from denying visibility of updates to memory.
1354 config ARM_ERRATA_364296
1355 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1356 depends on CPU_V6 && !SMP
1358 This options enables the workaround for the 364296 ARM1136
1359 r0p2 erratum (possible cache data corruption with
1360 hit-under-miss enabled). It sets the undocumented bit 31 in
1361 the auxiliary control register and the FI bit in the control
1362 register, thus disabling hit-under-miss without putting the
1363 processor into full low interrupt latency mode. ARM11MPCore
1366 config ARM_ERRATA_764369
1367 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1368 depends on CPU_V7 && SMP
1370 This option enables the workaround for erratum 764369
1371 affecting Cortex-A9 MPCore with two or more processors (all
1372 current revisions). Under certain timing circumstances, a data
1373 cache line maintenance operation by MVA targeting an Inner
1374 Shareable memory region may fail to proceed up to either the
1375 Point of Coherency or to the Point of Unification of the
1376 system. This workaround adds a DSB instruction before the
1377 relevant cache maintenance functions and sets a specific bit
1378 in the diagnostic control register of the SCU.
1380 config PL310_ERRATA_769419
1381 bool "PL310 errata: no automatic Store Buffer drain"
1382 depends on CACHE_L2X0
1384 On revisions of the PL310 prior to r3p2, the Store Buffer does
1385 not automatically drain. This can cause normal, non-cacheable
1386 writes to be retained when the memory system is idle, leading
1387 to suboptimal I/O performance for drivers using coherent DMA.
1388 This option adds a write barrier to the cpu_idle loop so that,
1389 on systems with an outer cache, the store buffer is drained
1394 source "arch/arm/common/Kconfig"
1404 Find out whether you have ISA slots on your motherboard. ISA is the
1405 name of a bus system, i.e. the way the CPU talks to the other stuff
1406 inside your box. Other bus systems are PCI, EISA, MicroChannel
1407 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1408 newer boards don't support it. If you have ISA, say Y, otherwise N.
1410 # Select ISA DMA controller support
1415 # Select ISA DMA interface
1420 bool "PCI support" if MIGHT_HAVE_PCI
1422 Find out whether you have a PCI motherboard. PCI is the name of a
1423 bus system, i.e. the way the CPU talks to the other stuff inside
1424 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1425 VESA. If you have PCI, say Y, otherwise N.
1431 config PCI_NANOENGINE
1432 bool "BSE nanoEngine PCI support"
1433 depends on SA1100_NANOENGINE
1435 Enable PCI on the BSE nanoEngine board.
1440 # Select the host bridge type
1441 config PCI_HOST_VIA82C505
1443 depends on PCI && ARCH_SHARK
1446 config PCI_HOST_ITE8152
1448 depends on PCI && MACH_ARMCORE
1452 source "drivers/pci/Kconfig"
1454 source "drivers/pcmcia/Kconfig"
1458 menu "Kernel Features"
1460 source "kernel/time/Kconfig"
1463 bool "Symmetric Multi-Processing"
1464 depends on CPU_V6K || CPU_V7
1465 depends on GENERIC_CLOCKEVENTS
1466 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1467 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1468 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1469 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1471 select USE_GENERIC_SMP_HELPERS
1472 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1474 This enables support for systems with more than one CPU. If you have
1475 a system with only one CPU, like most personal computers, say N. If
1476 you have a system with more than one CPU, say Y.
1478 If you say N here, the kernel will run on single and multiprocessor
1479 machines, but will use only one CPU of a multiprocessor machine. If
1480 you say Y here, the kernel will run on many, but not all, single
1481 processor machines. On a single processor machine, the kernel will
1482 run faster if you say N here.
1484 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1485 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1486 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1488 If you don't know what to do here, say N.
1491 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1492 depends on EXPERIMENTAL
1493 depends on SMP && !XIP_KERNEL
1496 SMP kernels contain instructions which fail on non-SMP processors.
1497 Enabling this option allows the kernel to modify itself to make
1498 these instructions safe. Disabling it allows about 1K of space
1501 If you don't know what to do here, say Y.
1503 config ARM_CPU_TOPOLOGY
1504 bool "Support cpu topology definition"
1505 depends on SMP && CPU_V7
1508 Support ARM cpu topology definition. The MPIDR register defines
1509 affinity between processors which is then used to describe the cpu
1510 topology of an ARM System.
1513 bool "Multi-core scheduler support"
1514 depends on ARM_CPU_TOPOLOGY
1516 Multi-core scheduler support improves the CPU scheduler's decision
1517 making when dealing with multi-core CPU chips at a cost of slightly
1518 increased overhead in some places. If unsure say N here.
1521 bool "SMT scheduler support"
1522 depends on ARM_CPU_TOPOLOGY
1524 Improves the CPU scheduler's decision making when dealing with
1525 MultiThreading at a cost of slightly increased overhead in some
1526 places. If unsure say N here.
1531 This option enables support for the ARM system coherency unit
1538 This options enables support for the ARM timer and watchdog unit
1541 prompt "Memory split"
1544 Select the desired split between kernel and user memory.
1546 If you are not absolutely sure what you are doing, leave this
1550 bool "3G/1G user/kernel split"
1552 bool "2G/2G user/kernel split"
1554 bool "1G/3G user/kernel split"
1559 default 0x40000000 if VMSPLIT_1G
1560 default 0x80000000 if VMSPLIT_2G
1564 int "Maximum number of CPUs (2-32)"
1570 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1571 depends on SMP && HOTPLUG && EXPERIMENTAL
1573 Say Y here to experiment with turning CPUs off and on. CPUs
1574 can be controlled through /sys/devices/system/cpu.
1577 bool "Use local timer interrupts"
1580 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1582 Enable support for local timers on SMP platforms, rather then the
1583 legacy IPI broadcast method. Local timers allows the system
1584 accounting to be spread across the timer interval, preventing a
1585 "thundering herd" at every timer tick.
1587 source kernel/Kconfig.preempt
1591 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1592 ARCH_S5PV210 || ARCH_EXYNOS4
1593 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1594 default AT91_TIMER_HZ if ARCH_AT91
1595 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1598 config THUMB2_KERNEL
1599 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1600 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1602 select ARM_ASM_UNIFIED
1605 By enabling this option, the kernel will be compiled in
1606 Thumb-2 mode. A compiler/assembler that understand the unified
1607 ARM-Thumb syntax is needed.
1611 config THUMB2_AVOID_R_ARM_THM_JUMP11
1612 bool "Work around buggy Thumb-2 short branch relocations in gas"
1613 depends on THUMB2_KERNEL && MODULES
1616 Various binutils versions can resolve Thumb-2 branches to
1617 locally-defined, preemptible global symbols as short-range "b.n"
1618 branch instructions.
1620 This is a problem, because there's no guarantee the final
1621 destination of the symbol, or any candidate locations for a
1622 trampoline, are within range of the branch. For this reason, the
1623 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1624 relocation in modules at all, and it makes little sense to add
1627 The symptom is that the kernel fails with an "unsupported
1628 relocation" error when loading some modules.
1630 Until fixed tools are available, passing
1631 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1632 code which hits this problem, at the cost of a bit of extra runtime
1633 stack usage in some cases.
1635 The problem is described in more detail at:
1636 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1638 Only Thumb-2 kernels are affected.
1640 Unless you are sure your tools don't have this problem, say Y.
1642 config ARM_ASM_UNIFIED
1646 bool "Use the ARM EABI to compile the kernel"
1648 This option allows for the kernel to be compiled using the latest
1649 ARM ABI (aka EABI). This is only useful if you are using a user
1650 space environment that is also compiled with EABI.
1652 Since there are major incompatibilities between the legacy ABI and
1653 EABI, especially with regard to structure member alignment, this
1654 option also changes the kernel syscall calling convention to
1655 disambiguate both ABIs and allow for backward compatibility support
1656 (selected with CONFIG_OABI_COMPAT).
1658 To use this you need GCC version 4.0.0 or later.
1661 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1662 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1665 This option preserves the old syscall interface along with the
1666 new (ARM EABI) one. It also provides a compatibility layer to
1667 intercept syscalls that have structure arguments which layout
1668 in memory differs between the legacy ABI and the new ARM EABI
1669 (only for non "thumb" binaries). This option adds a tiny
1670 overhead to all syscalls and produces a slightly larger kernel.
1671 If you know you'll be using only pure EABI user space then you
1672 can say N here. If this option is not selected and you attempt
1673 to execute a legacy ABI binary then the result will be
1674 UNPREDICTABLE (in fact it can be predicted that it won't work
1675 at all). If in doubt say Y.
1677 config ARCH_HAS_HOLES_MEMORYMODEL
1680 config ARCH_SPARSEMEM_ENABLE
1683 config ARCH_SPARSEMEM_DEFAULT
1684 def_bool ARCH_SPARSEMEM_ENABLE
1686 config ARCH_SELECT_MEMORY_MODEL
1687 def_bool ARCH_SPARSEMEM_ENABLE
1689 config HAVE_ARCH_PFN_VALID
1690 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1693 bool "High Memory Support"
1696 The address space of ARM processors is only 4 Gigabytes large
1697 and it has to accommodate user address space, kernel address
1698 space as well as some memory mapped IO. That means that, if you
1699 have a large amount of physical memory and/or IO, not all of the
1700 memory can be "permanently mapped" by the kernel. The physical
1701 memory that is not permanently mapped is called "high memory".
1703 Depending on the selected kernel/user memory split, minimum
1704 vmalloc space and actual amount of RAM, you may not need this
1705 option which should result in a slightly faster kernel.
1710 bool "Allocate 2nd-level pagetables from highmem"
1713 config HW_PERF_EVENTS
1714 bool "Enable hardware performance counter support for perf events"
1715 depends on PERF_EVENTS && CPU_HAS_PMU
1718 Enable hardware performance counter support for perf events. If
1719 disabled, perf events will use software events only.
1721 config SYS_SUPPORTS_HUGETLBFS
1723 depends on ARM_LPAE || (!CPU_USE_DOMAINS && !MEMORY_FAILURE)
1725 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1727 depends on SYS_SUPPORTS_HUGETLBFS
1731 config FORCE_MAX_ZONEORDER
1732 int "Maximum zone order" if ARCH_SHMOBILE
1733 range 11 64 if ARCH_SHMOBILE
1734 default "9" if SA1111
1737 The kernel memory allocator divides physically contiguous memory
1738 blocks into "zones", where each zone is a power of two number of
1739 pages. This option selects the largest power of two that the kernel
1740 keeps in the memory allocator. If you need to allocate very large
1741 blocks of physically contiguous memory, then you may need to
1742 increase this value.
1744 This config option is actually maximum order plus one. For example,
1745 a value of 11 means that the largest free memory block is 2^10 pages.
1748 bool "Timer and CPU usage LEDs"
1749 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1750 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1751 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1752 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1753 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1754 ARCH_AT91 || ARCH_DAVINCI || \
1755 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1757 If you say Y here, the LEDs on your machine will be used
1758 to provide useful information about your current system status.
1760 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1761 be able to select which LEDs are active using the options below. If
1762 you are compiling a kernel for the EBSA-110 or the LART however, the
1763 red LED will simply flash regularly to indicate that the system is
1764 still functional. It is safe to say Y here if you have a CATS
1765 system, but the driver will do nothing.
1768 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1769 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1770 || MACH_OMAP_PERSEUS2
1772 depends on !GENERIC_CLOCKEVENTS
1773 default y if ARCH_EBSA110
1775 If you say Y here, one of the system LEDs (the green one on the
1776 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1777 will flash regularly to indicate that the system is still
1778 operational. This is mainly useful to kernel hackers who are
1779 debugging unstable kernels.
1781 The LART uses the same LED for both Timer LED and CPU usage LED
1782 functions. You may choose to use both, but the Timer LED function
1783 will overrule the CPU usage LED.
1786 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1788 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1789 || MACH_OMAP_PERSEUS2
1792 If you say Y here, the red LED will be used to give a good real
1793 time indication of CPU usage, by lighting whenever the idle task
1794 is not currently executing.
1796 The LART uses the same LED for both Timer LED and CPU usage LED
1797 functions. You may choose to use both, but the Timer LED function
1798 will overrule the CPU usage LED.
1800 config ALIGNMENT_TRAP
1801 bool "Enable alignment trap"
1802 depends on CPU_CP15_MMU
1803 default y if !ARCH_EBSA110
1804 select HAVE_PROC_CPU if PROC_FS
1806 ARM processors cannot fetch/store information which is not
1807 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1808 address divisible by 4. On 32-bit ARM processors, these non-aligned
1809 fetch/store instructions will be emulated in software if you say
1810 here, which has a severe performance impact. This is necessary for
1811 correct operation of some network protocols. With an IP-only
1812 configuration it is safe to say N, otherwise say Y.
1814 config UACCESS_WITH_MEMCPY
1815 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1816 depends on MMU && EXPERIMENTAL
1817 default y if CPU_FEROCEON
1819 Implement faster copy_to_user and clear_user methods for CPU
1820 cores where a 8-word STM instruction give significantly higher
1821 memory write throughput than a sequence of individual 32bit stores.
1823 A possible side effect is a slight increase in scheduling latency
1824 between threads sharing the same address space if they invoke
1825 such copy operations with large buffers.
1827 However, if the CPU data cache is using a write-allocate mode,
1828 this option is unlikely to provide any performance gain.
1832 prompt "Enable seccomp to safely compute untrusted bytecode"
1834 This kernel feature is useful for number crunching applications
1835 that may need to compute untrusted bytecode during their
1836 execution. By using pipes or other transports made available to
1837 the process as file descriptors supporting the read/write
1838 syscalls, it's possible to isolate those applications in
1839 their own address space using seccomp. Once seccomp is
1840 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1841 and the task is only allowed to execute a few safe syscalls
1842 defined by each seccomp mode.
1844 config CC_STACKPROTECTOR
1845 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1846 depends on EXPERIMENTAL
1848 This option turns on the -fstack-protector GCC feature. This
1849 feature puts, at the beginning of functions, a canary value on
1850 the stack just before the return address, and validates
1851 the value just before actually returning. Stack based buffer
1852 overflows (that need to overwrite this return address) now also
1853 overwrite the canary, which gets detected and the attack is then
1854 neutralized via a kernel panic.
1855 This feature requires gcc version 4.2 or above.
1857 config DEPRECATED_PARAM_STRUCT
1858 bool "Provide old way to pass kernel parameters"
1860 This was deprecated in 2001 and announced to live on for 5 years.
1861 Some old boot loaders still use this way.
1865 depends on CPU_V7 && SYSFS
1873 bool "Flattened Device Tree support"
1875 select OF_EARLY_FLATTREE
1878 Include support for flattened device tree machine descriptions.
1880 # Compressed boot loader in ROM. Yes, we really want to ask about
1881 # TEXT and BSS so we preserve their values in the config files.
1882 config ZBOOT_ROM_TEXT
1883 hex "Compressed ROM boot loader base address"
1886 The physical address at which the ROM-able zImage is to be
1887 placed in the target. Platforms which normally make use of
1888 ROM-able zImage formats normally set this to a suitable
1889 value in their defconfig file.
1891 If ZBOOT_ROM is not enabled, this has no effect.
1893 config ZBOOT_ROM_BSS
1894 hex "Compressed ROM boot loader BSS address"
1897 The base address of an area of read/write memory in the target
1898 for the ROM-able zImage which must be available while the
1899 decompressor is running. It must be large enough to hold the
1900 entire decompressed kernel plus an additional 128 KiB.
1901 Platforms which normally make use of ROM-able zImage formats
1902 normally set this to a suitable value in their defconfig file.
1904 If ZBOOT_ROM is not enabled, this has no effect.
1907 bool "Compressed boot loader in ROM/flash"
1908 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1910 Say Y here if you intend to execute your compressed kernel image
1911 (zImage) directly from ROM or flash. If unsure, say N.
1914 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1915 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1916 default ZBOOT_ROM_NONE
1918 Include experimental SD/MMC loading code in the ROM-able zImage.
1919 With this enabled it is possible to write the the ROM-able zImage
1920 kernel image to an MMC or SD card and boot the kernel straight
1921 from the reset vector. At reset the processor Mask ROM will load
1922 the first part of the the ROM-able zImage which in turn loads the
1923 rest the kernel image to RAM.
1925 config ZBOOT_ROM_NONE
1926 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1928 Do not load image from SD or MMC
1930 config ZBOOT_ROM_MMCIF
1931 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1933 Load image from MMCIF hardware block.
1935 config ZBOOT_ROM_SH_MOBILE_SDHI
1936 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1938 Load image from SDHI hardware block
1942 config ARM_APPENDED_DTB
1943 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1944 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1946 With this option, the boot code will look for a device tree binary
1947 (DTB) appended to zImage
1948 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1950 This is meant as a backward compatibility convenience for those
1951 systems with a bootloader that can't be upgraded to accommodate
1952 the documented boot protocol using a device tree.
1954 Beware that there is very little in terms of protection against
1955 this option being confused by leftover garbage in memory that might
1956 look like a DTB header after a reboot if no actual DTB is appended
1957 to zImage. Do not leave this option active in a production kernel
1958 if you don't intend to always append a DTB. Proper passing of the
1959 location into r2 of a bootloader provided DTB is always preferable
1962 config ARM_ATAG_DTB_COMPAT
1963 bool "Supplement the appended DTB with traditional ATAG information"
1964 depends on ARM_APPENDED_DTB
1966 Some old bootloaders can't be updated to a DTB capable one, yet
1967 they provide ATAGs with memory configuration, the ramdisk address,
1968 the kernel cmdline string, etc. Such information is dynamically
1969 provided by the bootloader and can't always be stored in a static
1970 DTB. To allow a device tree enabled kernel to be used with such
1971 bootloaders, this option allows zImage to extract the information
1972 from the ATAG list and store it at run time into the appended DTB.
1975 string "Default kernel command string"
1978 On some architectures (EBSA110 and CATS), there is currently no way
1979 for the boot loader to pass arguments to the kernel. For these
1980 architectures, you should supply some command-line options at build
1981 time by entering them here. As a minimum, you should specify the
1982 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1985 prompt "Kernel command line type" if CMDLINE != ""
1986 default CMDLINE_FROM_BOOTLOADER
1988 config CMDLINE_FROM_BOOTLOADER
1989 bool "Use bootloader kernel arguments if available"
1991 Uses the command-line options passed by the boot loader. If
1992 the boot loader doesn't provide any, the default kernel command
1993 string provided in CMDLINE will be used.
1995 config CMDLINE_EXTEND
1996 bool "Extend bootloader kernel arguments"
1998 The command-line arguments provided by the boot loader will be
1999 appended to the default kernel command string.
2001 config CMDLINE_FORCE
2002 bool "Always use the default kernel command string"
2004 Always use the default kernel command string, even if the boot
2005 loader passes other arguments to the kernel.
2006 This is useful if you cannot or don't want to change the
2007 command-line options your boot loader passes to the kernel.
2011 bool "Kernel Execute-In-Place from ROM"
2012 depends on !ZBOOT_ROM && !ARM_LPAE
2014 Execute-In-Place allows the kernel to run from non-volatile storage
2015 directly addressable by the CPU, such as NOR flash. This saves RAM
2016 space since the text section of the kernel is not loaded from flash
2017 to RAM. Read-write sections, such as the data section and stack,
2018 are still copied to RAM. The XIP kernel is not compressed since
2019 it has to run directly from flash, so it will take more space to
2020 store it. The flash address used to link the kernel object files,
2021 and for storing it, is configuration dependent. Therefore, if you
2022 say Y here, you must know the proper physical address where to
2023 store the kernel image depending on your own flash memory usage.
2025 Also note that the make target becomes "make xipImage" rather than
2026 "make zImage" or "make Image". The final kernel binary to put in
2027 ROM memory will be arch/arm/boot/xipImage.
2031 config XIP_PHYS_ADDR
2032 hex "XIP Kernel Physical Location"
2033 depends on XIP_KERNEL
2034 default "0x00080000"
2036 This is the physical address in your flash memory the kernel will
2037 be linked for and stored to. This address is dependent on your
2041 bool "Kexec system call (EXPERIMENTAL)"
2042 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2044 kexec is a system call that implements the ability to shutdown your
2045 current kernel, and to start another kernel. It is like a reboot
2046 but it is independent of the system firmware. And like a reboot
2047 you can start any kernel with it, not just Linux.
2049 It is an ongoing process to be certain the hardware in a machine
2050 is properly shutdown, so do not be surprised if this code does not
2051 initially work for you. It may help to enable device hotplugging
2055 bool "Export atags in procfs"
2059 Should the atags used to boot the kernel be exported in an "atags"
2060 file in procfs. Useful with kexec.
2063 bool "Build kdump crash kernel (EXPERIMENTAL)"
2064 depends on EXPERIMENTAL
2066 Generate crash dump after being started by kexec. This should
2067 be normally only set in special crash dump kernels which are
2068 loaded in the main kernel with kexec-tools into a specially
2069 reserved region and then later executed after a crash by
2070 kdump/kexec. The crash dump kernel must be compiled to a
2071 memory address not used by the main kernel
2073 For more details see Documentation/kdump/kdump.txt
2075 config AUTO_ZRELADDR
2076 bool "Auto calculation of the decompressed kernel image address"
2077 depends on !ZBOOT_ROM && !ARCH_U300
2079 ZRELADDR is the physical address where the decompressed kernel
2080 image will be placed. If AUTO_ZRELADDR is selected, the address
2081 will be determined at run-time by masking the current IP with
2082 0xf8000000. This assumes the zImage being placed in the first 128MB
2083 from start of memory.
2087 menu "CPU Power Management"
2091 source "drivers/cpufreq/Kconfig"
2094 tristate "CPUfreq driver for i.MX CPUs"
2095 depends on ARCH_MXC && CPU_FREQ
2096 select CPU_FREQ_TABLE
2098 This enables the CPUfreq driver for i.MX CPUs.
2100 config CPU_FREQ_SA1100
2103 config CPU_FREQ_SA1110
2106 config CPU_FREQ_INTEGRATOR
2107 tristate "CPUfreq driver for ARM Integrator CPUs"
2108 depends on ARCH_INTEGRATOR && CPU_FREQ
2111 This enables the CPUfreq driver for ARM Integrator CPUs.
2113 For details, take a look at <file:Documentation/cpu-freq>.
2119 depends on CPU_FREQ && ARCH_PXA && PXA25x
2121 select CPU_FREQ_TABLE
2122 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2127 Internal configuration node for common cpufreq on Samsung SoC
2129 config CPU_FREQ_S3C24XX
2130 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2131 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2134 This enables the CPUfreq driver for the Samsung S3C24XX family
2137 For details, take a look at <file:Documentation/cpu-freq>.
2141 config CPU_FREQ_S3C24XX_PLL
2142 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2143 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2145 Compile in support for changing the PLL frequency from the
2146 S3C24XX series CPUfreq driver. The PLL takes time to settle
2147 after a frequency change, so by default it is not enabled.
2149 This also means that the PLL tables for the selected CPU(s) will
2150 be built which may increase the size of the kernel image.
2152 config CPU_FREQ_S3C24XX_DEBUG
2153 bool "Debug CPUfreq Samsung driver core"
2154 depends on CPU_FREQ_S3C24XX
2156 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2158 config CPU_FREQ_S3C24XX_IODEBUG
2159 bool "Debug CPUfreq Samsung driver IO timing"
2160 depends on CPU_FREQ_S3C24XX
2162 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2164 config CPU_FREQ_S3C24XX_DEBUGFS
2165 bool "Export debugfs for CPUFreq"
2166 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2168 Export status information via debugfs.
2172 source "drivers/cpuidle/Kconfig"
2176 menu "Floating point emulation"
2178 comment "At least one emulation must be selected"
2181 bool "NWFPE math emulation"
2182 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2184 Say Y to include the NWFPE floating point emulator in the kernel.
2185 This is necessary to run most binaries. Linux does not currently
2186 support floating point hardware so you need to say Y here even if
2187 your machine has an FPA or floating point co-processor podule.
2189 You may say N here if you are going to load the Acorn FPEmulator
2190 early in the bootup.
2193 bool "Support extended precision"
2194 depends on FPE_NWFPE
2196 Say Y to include 80-bit support in the kernel floating-point
2197 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2198 Note that gcc does not generate 80-bit operations by default,
2199 so in most cases this option only enlarges the size of the
2200 floating point emulator without any good reason.
2202 You almost surely want to say N here.
2205 bool "FastFPE math emulation (EXPERIMENTAL)"
2206 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2208 Say Y here to include the FAST floating point emulator in the kernel.
2209 This is an experimental much faster emulator which now also has full
2210 precision for the mantissa. It does not support any exceptions.
2211 It is very simple, and approximately 3-6 times faster than NWFPE.
2213 It should be sufficient for most programs. It may be not suitable
2214 for scientific calculations, but you have to check this for yourself.
2215 If you do not feel you need a faster FP emulation you should better
2219 bool "VFP-format floating point maths"
2220 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2222 Say Y to include VFP support code in the kernel. This is needed
2223 if your hardware includes a VFP unit.
2225 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2226 release notes and additional status information.
2228 Say N if your target does not have VFP hardware.
2236 bool "Advanced SIMD (NEON) Extension support"
2237 depends on VFPv3 && CPU_V7
2239 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2244 menu "Userspace binary formats"
2246 source "fs/Kconfig.binfmt"
2249 tristate "RISC OS personality"
2252 Say Y here to include the kernel code necessary if you want to run
2253 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2254 experimental; if this sounds frightening, say N and sleep in peace.
2255 You can also say M here to compile this support as a module (which
2256 will be called arthur).
2260 menu "Power management options"
2262 source "kernel/power/Kconfig"
2264 config ARCH_SUSPEND_POSSIBLE
2265 depends on !ARCH_S5PC100
2266 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2267 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2270 config ARM_CPU_SUSPEND
2275 source "net/Kconfig"
2277 source "drivers/Kconfig"
2281 source "arch/arm/Kconfig.debug"
2283 source "security/Kconfig"
2285 source "crypto/Kconfig"
2287 source "lib/Kconfig"