4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_MEMORY_H
284 select MULTI_IRQ_HANDLER
286 Support for ARM's Integrator platform.
289 bool "ARM Ltd. RealView family"
292 select HAVE_MACH_CLKDEV
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select PLAT_VERSATILE
297 select PLAT_VERSATILE_CLOCK
298 select PLAT_VERSATILE_CLCD
299 select ARM_TIMER_SP804
300 select GPIO_PL061 if GPIOLIB
301 select NEED_MACH_MEMORY_H
303 This enables support for ARM Ltd RealView boards.
305 config ARCH_VERSATILE
306 bool "ARM Ltd. Versatile family"
310 select HAVE_MACH_CLKDEV
312 select GENERIC_CLOCKEVENTS
313 select ARCH_WANT_OPTIONAL_GPIOLIB
314 select PLAT_VERSATILE
315 select PLAT_VERSATILE_CLOCK
316 select PLAT_VERSATILE_CLCD
317 select PLAT_VERSATILE_FPGA_IRQ
318 select ARM_TIMER_SP804
320 This enables support for ARM Ltd Versatile board.
323 bool "ARM Ltd. Versatile Express family"
324 select ARCH_WANT_OPTIONAL_GPIOLIB
326 select ARM_TIMER_SP804
329 select GENERIC_CLOCKEVENTS
331 select HAVE_PATA_PLATFORM
334 select PLAT_VERSATILE
335 select PLAT_VERSATILE_CLCD
336 select REGULATOR_FIXED_VOLTAGE if REGULATOR
338 This enables support for the ARM Ltd Versatile Express boards.
342 select ARCH_REQUIRE_GPIOLIB
346 select NEED_MACH_IO_H if PCCARD
348 This enables support for systems based on Atmel
349 AT91RM9200 and AT91SAM9* processors.
352 bool "Broadcom BCMRING"
356 select ARM_TIMER_SP804
358 select GENERIC_CLOCKEVENTS
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 Support for Broadcom's BCMRing platform.
364 bool "Calxeda Highbank-based"
365 select ARCH_WANT_OPTIONAL_GPIOLIB
368 select ARM_TIMER_SP804
373 select GENERIC_CLOCKEVENTS
379 Support for the Calxeda Highbank SoC based boards.
382 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
384 select ARCH_USES_GETTIMEOFFSET
385 select NEED_MACH_MEMORY_H
387 Support for Cirrus Logic 711x/721x/731x based boards.
390 bool "Cavium Networks CNS3XXX family"
392 select GENERIC_CLOCKEVENTS
394 select MIGHT_HAVE_CACHE_L2X0
395 select MIGHT_HAVE_PCI
396 select PCI_DOMAINS if PCI
398 Support for Cavium Networks CNS3XXX platform.
401 bool "Cortina Systems Gemini"
403 select ARCH_REQUIRE_GPIOLIB
404 select ARCH_USES_GETTIMEOFFSET
406 Support for the Cortina Systems Gemini family SoCs
411 select ARCH_REQUIRE_GPIOLIB
412 select GENERIC_CLOCKEVENTS
414 select GENERIC_IRQ_CHIP
415 select MIGHT_HAVE_CACHE_L2X0
420 Support for CSR SiRFprimaII/Marco/Polo platforms
427 select ARCH_USES_GETTIMEOFFSET
428 select NEED_MACH_IO_H
429 select NEED_MACH_MEMORY_H
431 This is an evaluation board for the StrongARM processor available
432 from Digital. It has limited hardware on-board, including an
433 Ethernet interface, two PCMCIA sockets, two serial ports and a
442 select ARCH_REQUIRE_GPIOLIB
443 select ARCH_HAS_HOLES_MEMORYMODEL
444 select ARCH_USES_GETTIMEOFFSET
445 select NEED_MACH_MEMORY_H
447 This enables support for the Cirrus EP93xx series of CPUs.
449 config ARCH_FOOTBRIDGE
453 select GENERIC_CLOCKEVENTS
455 select NEED_MACH_IO_H if !MMU
456 select NEED_MACH_MEMORY_H
458 Support for systems based on the DC21285 companion chip
459 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
462 bool "Freescale MXC/iMX-based"
463 select GENERIC_CLOCKEVENTS
464 select ARCH_REQUIRE_GPIOLIB
467 select GENERIC_IRQ_CHIP
468 select MULTI_IRQ_HANDLER
472 Support for Freescale MXC/iMX-based family of processors
475 bool "Freescale MXS-based"
476 select GENERIC_CLOCKEVENTS
477 select ARCH_REQUIRE_GPIOLIB
481 select HAVE_CLK_PREPARE
485 Support for Freescale MXS-based family of processors
488 bool "Hilscher NetX based"
492 select GENERIC_CLOCKEVENTS
494 This enables support for systems based on the Hilscher NetX Soc
497 bool "Hynix HMS720x-based"
500 select ARCH_USES_GETTIMEOFFSET
502 This enables support for systems based on the Hynix HMS720x
510 select ARCH_SUPPORTS_MSI
512 select NEED_MACH_MEMORY_H
513 select NEED_RET_TO_USER
515 Support for Intel's IOP13XX (XScale) family of processors.
521 select NEED_RET_TO_USER
524 select ARCH_REQUIRE_GPIOLIB
526 Support for Intel's 80219 and IOP32X (XScale) family of
533 select NEED_RET_TO_USER
536 select ARCH_REQUIRE_GPIOLIB
538 Support for Intel's IOP33X (XScale) family of processors.
543 select ARCH_HAS_DMA_SET_COHERENT_MASK
546 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
548 select MIGHT_HAVE_PCI
549 select NEED_MACH_IO_H
550 select DMABOUNCE if PCI
552 Support for Intel's IXP4XX (XScale) family of processors.
555 bool "Marvell SOCs with Device Tree support"
556 select GENERIC_CLOCKEVENTS
557 select MULTI_IRQ_HANDLER
560 select GENERIC_IRQ_CHIP
564 Support for the Marvell SoC Family with device tree support
570 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
574 Support for the Marvell Dove SoC 88AP510
577 bool "Marvell Kirkwood"
580 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
584 Support for the following Marvell Kirkwood series SoCs:
585 88F6180, 88F6192 and 88F6281.
591 select ARCH_REQUIRE_GPIOLIB
594 select USB_ARCH_HAS_OHCI
596 select GENERIC_CLOCKEVENTS
600 Support for the NXP LPC32XX family of processors
603 bool "Marvell MV78xx0"
606 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
610 Support for the following Marvell MV78xx0 series SoCs:
618 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
622 Support for the following Marvell Orion 5x series SoCs:
623 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
624 Orion-2 (5281), Orion-1-90 (6183).
627 bool "Marvell PXA168/910/MMP2"
629 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
636 select GENERIC_ALLOCATOR
638 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
641 bool "Micrel/Kendin KS8695"
643 select ARCH_REQUIRE_GPIOLIB
644 select ARCH_USES_GETTIMEOFFSET
645 select NEED_MACH_MEMORY_H
647 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
648 System-on-Chip devices.
651 bool "Nuvoton W90X900 CPU"
653 select ARCH_REQUIRE_GPIOLIB
656 select GENERIC_CLOCKEVENTS
658 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
659 At present, the w90x900 has been renamed nuc900, regarding
660 the ARM series product line, you can login the following
661 link address to know more.
663 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
664 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
670 select GENERIC_CLOCKEVENTS
674 select MIGHT_HAVE_CACHE_L2X0
675 select ARCH_HAS_CPUFREQ
678 This enables support for NVIDIA Tegra based systems (Tegra APX,
679 Tegra 6xx and Tegra 2 series).
681 config ARCH_PICOXCELL
682 bool "Picochip picoXcell"
683 select ARCH_REQUIRE_GPIOLIB
684 select ARM_PATCH_PHYS_VIRT
688 select DW_APB_TIMER_OF
689 select GENERIC_CLOCKEVENTS
696 This enables support for systems based on the Picochip picoXcell
697 family of Femtocell devices. The picoxcell support requires device tree
701 bool "Philips Nexperia PNX4008 Mobile"
704 select ARCH_USES_GETTIMEOFFSET
706 This enables support for Philips PNX4008 mobile platform.
709 bool "PXA2xx/PXA3xx-based"
712 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
716 select GENERIC_CLOCKEVENTS
721 select MULTI_IRQ_HANDLER
722 select ARM_CPU_SUSPEND if PM
725 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
730 select GENERIC_CLOCKEVENTS
731 select ARCH_REQUIRE_GPIOLIB
734 Support for Qualcomm MSM/QSD based systems. This runs on the
735 apps processor of the MSM/QSD and depends on a shared memory
736 interface to the modem processor which runs the baseband
737 stack and controls some vital subsystems
738 (clock and power control, etc).
741 bool "Renesas SH-Mobile / R-Mobile"
744 select HAVE_MACH_CLKDEV
746 select GENERIC_CLOCKEVENTS
747 select MIGHT_HAVE_CACHE_L2X0
750 select MULTI_IRQ_HANDLER
751 select PM_GENERIC_DOMAINS if PM
752 select NEED_MACH_MEMORY_H
754 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
760 select ARCH_MAY_HAVE_PC_FDC
761 select HAVE_PATA_PLATFORM
764 select ARCH_SPARSEMEM_ENABLE
765 select ARCH_USES_GETTIMEOFFSET
767 select NEED_MACH_IO_H
768 select NEED_MACH_MEMORY_H
770 On the Acorn Risc-PC, Linux can support the internal IDE disk and
771 CD-ROM interface, serial and parallel port, and the floppy drive.
778 select ARCH_SPARSEMEM_ENABLE
780 select ARCH_HAS_CPUFREQ
782 select GENERIC_CLOCKEVENTS
784 select ARCH_REQUIRE_GPIOLIB
786 select NEED_MACH_MEMORY_H
789 Support for StrongARM 11x0 based boards.
792 bool "Samsung S3C24XX SoCs"
794 select ARCH_HAS_CPUFREQ
797 select ARCH_USES_GETTIMEOFFSET
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C_RTC if RTC_CLASS
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select NEED_MACH_IO_H
803 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
804 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
805 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
806 Samsung SMDK2410 development board (and derivatives).
809 bool "Samsung S3C64XX"
817 select ARCH_USES_GETTIMEOFFSET
818 select ARCH_HAS_CPUFREQ
819 select ARCH_REQUIRE_GPIOLIB
820 select SAMSUNG_CLKSRC
821 select SAMSUNG_IRQ_VIC_TIMER
822 select S3C_GPIO_TRACK
824 select USB_ARCH_HAS_OHCI
825 select SAMSUNG_GPIOLIB_4BIT
826 select HAVE_S3C2410_I2C if I2C
827 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 Samsung S3C64XX series based systems
832 bool "Samsung S5P6440 S5P6450"
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select GENERIC_CLOCKEVENTS
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C_RTC if RTC_CLASS
843 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
847 bool "Samsung S5PC100"
852 select ARCH_USES_GETTIMEOFFSET
853 select HAVE_S3C2410_I2C if I2C
854 select HAVE_S3C_RTC if RTC_CLASS
855 select HAVE_S3C2410_WATCHDOG if WATCHDOG
857 Samsung S5PC100 series based systems
860 bool "Samsung S5PV210/S5PC110"
862 select ARCH_SPARSEMEM_ENABLE
863 select ARCH_HAS_HOLES_MEMORYMODEL
868 select ARCH_HAS_CPUFREQ
869 select GENERIC_CLOCKEVENTS
870 select HAVE_S3C2410_I2C if I2C
871 select HAVE_S3C_RTC if RTC_CLASS
872 select HAVE_S3C2410_WATCHDOG if WATCHDOG
873 select NEED_MACH_MEMORY_H
875 Samsung S5PV210/S5PC110 series based systems
878 bool "SAMSUNG EXYNOS"
880 select ARCH_SPARSEMEM_ENABLE
881 select ARCH_HAS_HOLES_MEMORYMODEL
885 select ARCH_HAS_CPUFREQ
886 select GENERIC_CLOCKEVENTS
887 select HAVE_S3C_RTC if RTC_CLASS
888 select HAVE_S3C2410_I2C if I2C
889 select HAVE_S3C2410_WATCHDOG if WATCHDOG
890 select NEED_MACH_MEMORY_H
892 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
901 select ARCH_USES_GETTIMEOFFSET
902 select NEED_MACH_MEMORY_H
904 Support for the StrongARM based Digital DNARD machine, also known
905 as "Shark" (<http://www.shark-linux.de/shark.html>).
908 bool "ST-Ericsson U300 Series"
914 select ARM_PATCH_PHYS_VIRT
916 select GENERIC_CLOCKEVENTS
920 select ARCH_REQUIRE_GPIOLIB
923 Support for ST-Ericsson U300 series mobile platforms.
926 bool "ST-Ericsson U8500 Series"
930 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
933 select ARCH_HAS_CPUFREQ
935 select MIGHT_HAVE_CACHE_L2X0
937 Support for ST-Ericsson's Ux500 architecture
940 bool "STMicroelectronics Nomadik"
945 select GENERIC_CLOCKEVENTS
947 select MIGHT_HAVE_CACHE_L2X0
948 select ARCH_REQUIRE_GPIOLIB
950 Support for the Nomadik platform by ST-Ericsson
954 select GENERIC_CLOCKEVENTS
955 select ARCH_REQUIRE_GPIOLIB
959 select GENERIC_ALLOCATOR
960 select GENERIC_IRQ_CHIP
961 select ARCH_HAS_HOLES_MEMORYMODEL
963 Support for TI's DaVinci platform.
969 select ARCH_REQUIRE_GPIOLIB
970 select ARCH_HAS_CPUFREQ
972 select GENERIC_CLOCKEVENTS
973 select ARCH_HAS_HOLES_MEMORYMODEL
975 Support for TI's OMAP platform (OMAP1/2/3/4).
980 select ARCH_REQUIRE_GPIOLIB
984 select GENERIC_CLOCKEVENTS
987 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
990 bool "VIA/WonderMedia 85xx"
993 select ARCH_HAS_CPUFREQ
994 select GENERIC_CLOCKEVENTS
995 select ARCH_REQUIRE_GPIOLIB
997 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1000 bool "Xilinx Zynq ARM Cortex A9 Platform"
1002 select GENERIC_CLOCKEVENTS
1003 select CLKDEV_LOOKUP
1007 select MIGHT_HAVE_CACHE_L2X0
1010 Support for Xilinx Zynq ARM Cortex A9 Platform
1014 # This is sorted alphabetically by mach-* pathname. However, plat-*
1015 # Kconfigs may be included either alphabetically (according to the
1016 # plat- suffix) or along side the corresponding mach-* source.
1018 source "arch/arm/mach-mvebu/Kconfig"
1020 source "arch/arm/mach-at91/Kconfig"
1022 source "arch/arm/mach-bcmring/Kconfig"
1024 source "arch/arm/mach-clps711x/Kconfig"
1026 source "arch/arm/mach-cns3xxx/Kconfig"
1028 source "arch/arm/mach-davinci/Kconfig"
1030 source "arch/arm/mach-dove/Kconfig"
1032 source "arch/arm/mach-ep93xx/Kconfig"
1034 source "arch/arm/mach-footbridge/Kconfig"
1036 source "arch/arm/mach-gemini/Kconfig"
1038 source "arch/arm/mach-h720x/Kconfig"
1040 source "arch/arm/mach-integrator/Kconfig"
1042 source "arch/arm/mach-iop32x/Kconfig"
1044 source "arch/arm/mach-iop33x/Kconfig"
1046 source "arch/arm/mach-iop13xx/Kconfig"
1048 source "arch/arm/mach-ixp4xx/Kconfig"
1050 source "arch/arm/mach-kirkwood/Kconfig"
1052 source "arch/arm/mach-ks8695/Kconfig"
1054 source "arch/arm/mach-msm/Kconfig"
1056 source "arch/arm/mach-mv78xx0/Kconfig"
1058 source "arch/arm/plat-mxc/Kconfig"
1060 source "arch/arm/mach-mxs/Kconfig"
1062 source "arch/arm/mach-netx/Kconfig"
1064 source "arch/arm/mach-nomadik/Kconfig"
1065 source "arch/arm/plat-nomadik/Kconfig"
1067 source "arch/arm/plat-omap/Kconfig"
1069 source "arch/arm/mach-omap1/Kconfig"
1071 source "arch/arm/mach-omap2/Kconfig"
1073 source "arch/arm/mach-orion5x/Kconfig"
1075 source "arch/arm/mach-pxa/Kconfig"
1076 source "arch/arm/plat-pxa/Kconfig"
1078 source "arch/arm/mach-mmp/Kconfig"
1080 source "arch/arm/mach-realview/Kconfig"
1082 source "arch/arm/mach-sa1100/Kconfig"
1084 source "arch/arm/plat-samsung/Kconfig"
1085 source "arch/arm/plat-s3c24xx/Kconfig"
1087 source "arch/arm/plat-spear/Kconfig"
1089 source "arch/arm/mach-s3c24xx/Kconfig"
1091 source "arch/arm/mach-s3c2412/Kconfig"
1092 source "arch/arm/mach-s3c2440/Kconfig"
1096 source "arch/arm/mach-s3c64xx/Kconfig"
1099 source "arch/arm/mach-s5p64x0/Kconfig"
1101 source "arch/arm/mach-s5pc100/Kconfig"
1103 source "arch/arm/mach-s5pv210/Kconfig"
1105 source "arch/arm/mach-exynos/Kconfig"
1107 source "arch/arm/mach-shmobile/Kconfig"
1109 source "arch/arm/mach-prima2/Kconfig"
1111 source "arch/arm/mach-tegra/Kconfig"
1113 source "arch/arm/mach-u300/Kconfig"
1115 source "arch/arm/mach-ux500/Kconfig"
1117 source "arch/arm/mach-versatile/Kconfig"
1119 source "arch/arm/mach-vexpress/Kconfig"
1120 source "arch/arm/plat-versatile/Kconfig"
1122 source "arch/arm/mach-vt8500/Kconfig"
1124 source "arch/arm/mach-w90x900/Kconfig"
1126 # Definitions to make life easier
1132 select GENERIC_CLOCKEVENTS
1137 select GENERIC_IRQ_CHIP
1144 config PLAT_VERSATILE
1147 config ARM_TIMER_SP804
1150 select HAVE_SCHED_CLOCK
1152 source arch/arm/mm/Kconfig
1156 default 16 if ARCH_EP93XX
1160 bool "Enable iWMMXt support"
1161 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1162 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1164 Enable support for iWMMXt context switching at run time if
1165 running on a CPU that supports it.
1169 depends on CPU_XSCALE
1173 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1174 (!ARCH_OMAP3 || OMAP3_EMU)
1178 config MULTI_IRQ_HANDLER
1181 Allow each machine to specify it's own IRQ handler at run time.
1184 source "arch/arm/Kconfig-nommu"
1187 config ARM_ERRATA_326103
1188 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1191 Executing a SWP instruction to read-only memory does not set bit 11
1192 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1193 treat the access as a read, preventing a COW from occurring and
1194 causing the faulting task to livelock.
1196 config ARM_ERRATA_411920
1197 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1198 depends on CPU_V6 || CPU_V6K
1200 Invalidation of the Instruction Cache operation can
1201 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1202 It does not affect the MPCore. This option enables the ARM Ltd.
1203 recommended workaround.
1205 config ARM_ERRATA_430973
1206 bool "ARM errata: Stale prediction on replaced interworking branch"
1209 This option enables the workaround for the 430973 Cortex-A8
1210 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1211 interworking branch is replaced with another code sequence at the
1212 same virtual address, whether due to self-modifying code or virtual
1213 to physical address re-mapping, Cortex-A8 does not recover from the
1214 stale interworking branch prediction. This results in Cortex-A8
1215 executing the new code sequence in the incorrect ARM or Thumb state.
1216 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1217 and also flushes the branch target cache at every context switch.
1218 Note that setting specific bits in the ACTLR register may not be
1219 available in non-secure mode.
1221 config ARM_ERRATA_458693
1222 bool "ARM errata: Processor deadlock when a false hazard is created"
1225 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1226 erratum. For very specific sequences of memory operations, it is
1227 possible for a hazard condition intended for a cache line to instead
1228 be incorrectly associated with a different cache line. This false
1229 hazard might then cause a processor deadlock. The workaround enables
1230 the L1 caching of the NEON accesses and disables the PLD instruction
1231 in the ACTLR register. Note that setting specific bits in the ACTLR
1232 register may not be available in non-secure mode.
1234 config ARM_ERRATA_460075
1235 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1238 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1239 erratum. Any asynchronous access to the L2 cache may encounter a
1240 situation in which recent store transactions to the L2 cache are lost
1241 and overwritten with stale memory contents from external memory. The
1242 workaround disables the write-allocate mode for the L2 cache via the
1243 ACTLR register. Note that setting specific bits in the ACTLR register
1244 may not be available in non-secure mode.
1246 config ARM_ERRATA_742230
1247 bool "ARM errata: DMB operation may be faulty"
1248 depends on CPU_V7 && SMP
1250 This option enables the workaround for the 742230 Cortex-A9
1251 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1252 between two write operations may not ensure the correct visibility
1253 ordering of the two writes. This workaround sets a specific bit in
1254 the diagnostic register of the Cortex-A9 which causes the DMB
1255 instruction to behave as a DSB, ensuring the correct behaviour of
1258 config ARM_ERRATA_742231
1259 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1260 depends on CPU_V7 && SMP
1262 This option enables the workaround for the 742231 Cortex-A9
1263 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1264 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1265 accessing some data located in the same cache line, may get corrupted
1266 data due to bad handling of the address hazard when the line gets
1267 replaced from one of the CPUs at the same time as another CPU is
1268 accessing it. This workaround sets specific bits in the diagnostic
1269 register of the Cortex-A9 which reduces the linefill issuing
1270 capabilities of the processor.
1272 config PL310_ERRATA_588369
1273 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1274 depends on CACHE_L2X0
1276 The PL310 L2 cache controller implements three types of Clean &
1277 Invalidate maintenance operations: by Physical Address
1278 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1279 They are architecturally defined to behave as the execution of a
1280 clean operation followed immediately by an invalidate operation,
1281 both performing to the same memory location. This functionality
1282 is not correctly implemented in PL310 as clean lines are not
1283 invalidated as a result of these operations.
1285 config ARM_ERRATA_720789
1286 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1289 This option enables the workaround for the 720789 Cortex-A9 (prior to
1290 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1291 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1292 As a consequence of this erratum, some TLB entries which should be
1293 invalidated are not, resulting in an incoherency in the system page
1294 tables. The workaround changes the TLB flushing routines to invalidate
1295 entries regardless of the ASID.
1297 config PL310_ERRATA_727915
1298 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1299 depends on CACHE_L2X0
1301 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1302 operation (offset 0x7FC). This operation runs in background so that
1303 PL310 can handle normal accesses while it is in progress. Under very
1304 rare circumstances, due to this erratum, write data can be lost when
1305 PL310 treats a cacheable write transaction during a Clean &
1306 Invalidate by Way operation.
1308 config ARM_ERRATA_743622
1309 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1312 This option enables the workaround for the 743622 Cortex-A9
1313 (r2p*) erratum. Under very rare conditions, a faulty
1314 optimisation in the Cortex-A9 Store Buffer may lead to data
1315 corruption. This workaround sets a specific bit in the diagnostic
1316 register of the Cortex-A9 which disables the Store Buffer
1317 optimisation, preventing the defect from occurring. This has no
1318 visible impact on the overall performance or power consumption of the
1321 config ARM_ERRATA_751472
1322 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1325 This option enables the workaround for the 751472 Cortex-A9 (prior
1326 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1327 completion of a following broadcasted operation if the second
1328 operation is received by a CPU before the ICIALLUIS has completed,
1329 potentially leading to corrupted entries in the cache or TLB.
1331 config PL310_ERRATA_753970
1332 bool "PL310 errata: cache sync operation may be faulty"
1333 depends on CACHE_PL310
1335 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1337 Under some condition the effect of cache sync operation on
1338 the store buffer still remains when the operation completes.
1339 This means that the store buffer is always asked to drain and
1340 this prevents it from merging any further writes. The workaround
1341 is to replace the normal offset of cache sync operation (0x730)
1342 by another offset targeting an unmapped PL310 register 0x740.
1343 This has the same effect as the cache sync operation: store buffer
1344 drain and waiting for all buffers empty.
1346 config ARM_ERRATA_754322
1347 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1350 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1351 r3p*) erratum. A speculative memory access may cause a page table walk
1352 which starts prior to an ASID switch but completes afterwards. This
1353 can populate the micro-TLB with a stale entry which may be hit with
1354 the new ASID. This workaround places two dsb instructions in the mm
1355 switching code so that no page table walks can cross the ASID switch.
1357 config ARM_ERRATA_754327
1358 bool "ARM errata: no automatic Store Buffer drain"
1359 depends on CPU_V7 && SMP
1361 This option enables the workaround for the 754327 Cortex-A9 (prior to
1362 r2p0) erratum. The Store Buffer does not have any automatic draining
1363 mechanism and therefore a livelock may occur if an external agent
1364 continuously polls a memory location waiting to observe an update.
1365 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1366 written polling loops from denying visibility of updates to memory.
1368 config ARM_ERRATA_364296
1369 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1370 depends on CPU_V6 && !SMP
1372 This options enables the workaround for the 364296 ARM1136
1373 r0p2 erratum (possible cache data corruption with
1374 hit-under-miss enabled). It sets the undocumented bit 31 in
1375 the auxiliary control register and the FI bit in the control
1376 register, thus disabling hit-under-miss without putting the
1377 processor into full low interrupt latency mode. ARM11MPCore
1380 config ARM_ERRATA_764369
1381 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1382 depends on CPU_V7 && SMP
1384 This option enables the workaround for erratum 764369
1385 affecting Cortex-A9 MPCore with two or more processors (all
1386 current revisions). Under certain timing circumstances, a data
1387 cache line maintenance operation by MVA targeting an Inner
1388 Shareable memory region may fail to proceed up to either the
1389 Point of Coherency or to the Point of Unification of the
1390 system. This workaround adds a DSB instruction before the
1391 relevant cache maintenance functions and sets a specific bit
1392 in the diagnostic control register of the SCU.
1394 config PL310_ERRATA_769419
1395 bool "PL310 errata: no automatic Store Buffer drain"
1396 depends on CACHE_L2X0
1398 On revisions of the PL310 prior to r3p2, the Store Buffer does
1399 not automatically drain. This can cause normal, non-cacheable
1400 writes to be retained when the memory system is idle, leading
1401 to suboptimal I/O performance for drivers using coherent DMA.
1402 This option adds a write barrier to the cpu_idle loop so that,
1403 on systems with an outer cache, the store buffer is drained
1408 source "arch/arm/common/Kconfig"
1418 Find out whether you have ISA slots on your motherboard. ISA is the
1419 name of a bus system, i.e. the way the CPU talks to the other stuff
1420 inside your box. Other bus systems are PCI, EISA, MicroChannel
1421 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1422 newer boards don't support it. If you have ISA, say Y, otherwise N.
1424 # Select ISA DMA controller support
1429 # Select ISA DMA interface
1434 bool "PCI support" if MIGHT_HAVE_PCI
1436 Find out whether you have a PCI motherboard. PCI is the name of a
1437 bus system, i.e. the way the CPU talks to the other stuff inside
1438 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1439 VESA. If you have PCI, say Y, otherwise N.
1445 config PCI_NANOENGINE
1446 bool "BSE nanoEngine PCI support"
1447 depends on SA1100_NANOENGINE
1449 Enable PCI on the BSE nanoEngine board.
1454 # Select the host bridge type
1455 config PCI_HOST_VIA82C505
1457 depends on PCI && ARCH_SHARK
1460 config PCI_HOST_ITE8152
1462 depends on PCI && MACH_ARMCORE
1466 source "drivers/pci/Kconfig"
1468 source "drivers/pcmcia/Kconfig"
1472 menu "Kernel Features"
1477 This option should be selected by machines which have an SMP-
1480 The only effect of this option is to make the SMP-related
1481 options available to the user for configuration.
1484 bool "Symmetric Multi-Processing"
1485 depends on CPU_V6K || CPU_V7
1486 depends on GENERIC_CLOCKEVENTS
1489 select USE_GENERIC_SMP_HELPERS
1490 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1492 This enables support for systems with more than one CPU. If you have
1493 a system with only one CPU, like most personal computers, say N. If
1494 you have a system with more than one CPU, say Y.
1496 If you say N here, the kernel will run on single and multiprocessor
1497 machines, but will use only one CPU of a multiprocessor machine. If
1498 you say Y here, the kernel will run on many, but not all, single
1499 processor machines. On a single processor machine, the kernel will
1500 run faster if you say N here.
1502 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1503 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1504 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1506 If you don't know what to do here, say N.
1509 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1510 depends on EXPERIMENTAL
1511 depends on SMP && !XIP_KERNEL
1514 SMP kernels contain instructions which fail on non-SMP processors.
1515 Enabling this option allows the kernel to modify itself to make
1516 these instructions safe. Disabling it allows about 1K of space
1519 If you don't know what to do here, say Y.
1521 config ARM_CPU_TOPOLOGY
1522 bool "Support cpu topology definition"
1523 depends on SMP && CPU_V7
1526 Support ARM cpu topology definition. The MPIDR register defines
1527 affinity between processors which is then used to describe the cpu
1528 topology of an ARM System.
1531 bool "Multi-core scheduler support"
1532 depends on ARM_CPU_TOPOLOGY
1534 Multi-core scheduler support improves the CPU scheduler's decision
1535 making when dealing with multi-core CPU chips at a cost of slightly
1536 increased overhead in some places. If unsure say N here.
1539 bool "SMT scheduler support"
1540 depends on ARM_CPU_TOPOLOGY
1542 Improves the CPU scheduler's decision making when dealing with
1543 MultiThreading at a cost of slightly increased overhead in some
1544 places. If unsure say N here.
1549 This option enables support for the ARM system coherency unit
1551 config ARM_ARCH_TIMER
1552 bool "Architected timer support"
1555 This option enables support for the ARM architected timer
1561 This options enables support for the ARM timer and watchdog unit
1564 prompt "Memory split"
1567 Select the desired split between kernel and user memory.
1569 If you are not absolutely sure what you are doing, leave this
1573 bool "3G/1G user/kernel split"
1575 bool "2G/2G user/kernel split"
1577 bool "1G/3G user/kernel split"
1582 default 0x40000000 if VMSPLIT_1G
1583 default 0x80000000 if VMSPLIT_2G
1587 int "Maximum number of CPUs (2-32)"
1593 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1594 depends on SMP && HOTPLUG && EXPERIMENTAL
1596 Say Y here to experiment with turning CPUs off and on. CPUs
1597 can be controlled through /sys/devices/system/cpu.
1600 bool "Use local timer interrupts"
1603 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1605 Enable support for local timers on SMP platforms, rather then the
1606 legacy IPI broadcast method. Local timers allows the system
1607 accounting to be spread across the timer interval, preventing a
1608 "thundering herd" at every timer tick.
1612 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1613 default 355 if ARCH_U8500
1614 default 264 if MACH_H4700
1615 default 512 if SOC_OMAP5
1618 Maximum number of GPIOs in the system.
1620 If unsure, leave the default value.
1622 source kernel/Kconfig.preempt
1626 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1627 ARCH_S5PV210 || ARCH_EXYNOS4
1628 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1629 default AT91_TIMER_HZ if ARCH_AT91
1630 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1633 config THUMB2_KERNEL
1634 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1635 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1637 select ARM_ASM_UNIFIED
1640 By enabling this option, the kernel will be compiled in
1641 Thumb-2 mode. A compiler/assembler that understand the unified
1642 ARM-Thumb syntax is needed.
1646 config THUMB2_AVOID_R_ARM_THM_JUMP11
1647 bool "Work around buggy Thumb-2 short branch relocations in gas"
1648 depends on THUMB2_KERNEL && MODULES
1651 Various binutils versions can resolve Thumb-2 branches to
1652 locally-defined, preemptible global symbols as short-range "b.n"
1653 branch instructions.
1655 This is a problem, because there's no guarantee the final
1656 destination of the symbol, or any candidate locations for a
1657 trampoline, are within range of the branch. For this reason, the
1658 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1659 relocation in modules at all, and it makes little sense to add
1662 The symptom is that the kernel fails with an "unsupported
1663 relocation" error when loading some modules.
1665 Until fixed tools are available, passing
1666 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1667 code which hits this problem, at the cost of a bit of extra runtime
1668 stack usage in some cases.
1670 The problem is described in more detail at:
1671 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1673 Only Thumb-2 kernels are affected.
1675 Unless you are sure your tools don't have this problem, say Y.
1677 config ARM_ASM_UNIFIED
1681 bool "Use the ARM EABI to compile the kernel"
1683 This option allows for the kernel to be compiled using the latest
1684 ARM ABI (aka EABI). This is only useful if you are using a user
1685 space environment that is also compiled with EABI.
1687 Since there are major incompatibilities between the legacy ABI and
1688 EABI, especially with regard to structure member alignment, this
1689 option also changes the kernel syscall calling convention to
1690 disambiguate both ABIs and allow for backward compatibility support
1691 (selected with CONFIG_OABI_COMPAT).
1693 To use this you need GCC version 4.0.0 or later.
1696 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1697 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1700 This option preserves the old syscall interface along with the
1701 new (ARM EABI) one. It also provides a compatibility layer to
1702 intercept syscalls that have structure arguments which layout
1703 in memory differs between the legacy ABI and the new ARM EABI
1704 (only for non "thumb" binaries). This option adds a tiny
1705 overhead to all syscalls and produces a slightly larger kernel.
1706 If you know you'll be using only pure EABI user space then you
1707 can say N here. If this option is not selected and you attempt
1708 to execute a legacy ABI binary then the result will be
1709 UNPREDICTABLE (in fact it can be predicted that it won't work
1710 at all). If in doubt say Y.
1712 config ARCH_HAS_HOLES_MEMORYMODEL
1715 config ARCH_SPARSEMEM_ENABLE
1718 config ARCH_SPARSEMEM_DEFAULT
1719 def_bool ARCH_SPARSEMEM_ENABLE
1721 config ARCH_SELECT_MEMORY_MODEL
1722 def_bool ARCH_SPARSEMEM_ENABLE
1724 config HAVE_ARCH_PFN_VALID
1725 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1728 bool "High Memory Support"
1731 The address space of ARM processors is only 4 Gigabytes large
1732 and it has to accommodate user address space, kernel address
1733 space as well as some memory mapped IO. That means that, if you
1734 have a large amount of physical memory and/or IO, not all of the
1735 memory can be "permanently mapped" by the kernel. The physical
1736 memory that is not permanently mapped is called "high memory".
1738 Depending on the selected kernel/user memory split, minimum
1739 vmalloc space and actual amount of RAM, you may not need this
1740 option which should result in a slightly faster kernel.
1745 bool "Allocate 2nd-level pagetables from highmem"
1748 config HW_PERF_EVENTS
1749 bool "Enable hardware performance counter support for perf events"
1750 depends on PERF_EVENTS && CPU_HAS_PMU
1753 Enable hardware performance counter support for perf events. If
1754 disabled, perf events will use software events only.
1758 config FORCE_MAX_ZONEORDER
1759 int "Maximum zone order" if ARCH_SHMOBILE
1760 range 11 64 if ARCH_SHMOBILE
1761 default "9" if SA1111
1764 The kernel memory allocator divides physically contiguous memory
1765 blocks into "zones", where each zone is a power of two number of
1766 pages. This option selects the largest power of two that the kernel
1767 keeps in the memory allocator. If you need to allocate very large
1768 blocks of physically contiguous memory, then you may need to
1769 increase this value.
1771 This config option is actually maximum order plus one. For example,
1772 a value of 11 means that the largest free memory block is 2^10 pages.
1775 bool "Timer and CPU usage LEDs"
1776 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1777 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1778 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1779 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1780 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1781 ARCH_AT91 || ARCH_DAVINCI || \
1782 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1784 If you say Y here, the LEDs on your machine will be used
1785 to provide useful information about your current system status.
1787 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1788 be able to select which LEDs are active using the options below. If
1789 you are compiling a kernel for the EBSA-110 or the LART however, the
1790 red LED will simply flash regularly to indicate that the system is
1791 still functional. It is safe to say Y here if you have a CATS
1792 system, but the driver will do nothing.
1795 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1796 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1797 || MACH_OMAP_PERSEUS2
1799 depends on !GENERIC_CLOCKEVENTS
1800 default y if ARCH_EBSA110
1802 If you say Y here, one of the system LEDs (the green one on the
1803 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1804 will flash regularly to indicate that the system is still
1805 operational. This is mainly useful to kernel hackers who are
1806 debugging unstable kernels.
1808 The LART uses the same LED for both Timer LED and CPU usage LED
1809 functions. You may choose to use both, but the Timer LED function
1810 will overrule the CPU usage LED.
1813 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1815 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1816 || MACH_OMAP_PERSEUS2
1819 If you say Y here, the red LED will be used to give a good real
1820 time indication of CPU usage, by lighting whenever the idle task
1821 is not currently executing.
1823 The LART uses the same LED for both Timer LED and CPU usage LED
1824 functions. You may choose to use both, but the Timer LED function
1825 will overrule the CPU usage LED.
1827 config ALIGNMENT_TRAP
1829 depends on CPU_CP15_MMU
1830 default y if !ARCH_EBSA110
1831 select HAVE_PROC_CPU if PROC_FS
1833 ARM processors cannot fetch/store information which is not
1834 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1835 address divisible by 4. On 32-bit ARM processors, these non-aligned
1836 fetch/store instructions will be emulated in software if you say
1837 here, which has a severe performance impact. This is necessary for
1838 correct operation of some network protocols. With an IP-only
1839 configuration it is safe to say N, otherwise say Y.
1841 config UACCESS_WITH_MEMCPY
1842 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1843 depends on MMU && EXPERIMENTAL
1844 default y if CPU_FEROCEON
1846 Implement faster copy_to_user and clear_user methods for CPU
1847 cores where a 8-word STM instruction give significantly higher
1848 memory write throughput than a sequence of individual 32bit stores.
1850 A possible side effect is a slight increase in scheduling latency
1851 between threads sharing the same address space if they invoke
1852 such copy operations with large buffers.
1854 However, if the CPU data cache is using a write-allocate mode,
1855 this option is unlikely to provide any performance gain.
1859 prompt "Enable seccomp to safely compute untrusted bytecode"
1861 This kernel feature is useful for number crunching applications
1862 that may need to compute untrusted bytecode during their
1863 execution. By using pipes or other transports made available to
1864 the process as file descriptors supporting the read/write
1865 syscalls, it's possible to isolate those applications in
1866 their own address space using seccomp. Once seccomp is
1867 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1868 and the task is only allowed to execute a few safe syscalls
1869 defined by each seccomp mode.
1871 config CC_STACKPROTECTOR
1872 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1873 depends on EXPERIMENTAL
1875 This option turns on the -fstack-protector GCC feature. This
1876 feature puts, at the beginning of functions, a canary value on
1877 the stack just before the return address, and validates
1878 the value just before actually returning. Stack based buffer
1879 overflows (that need to overwrite this return address) now also
1880 overwrite the canary, which gets detected and the attack is then
1881 neutralized via a kernel panic.
1882 This feature requires gcc version 4.2 or above.
1884 config DEPRECATED_PARAM_STRUCT
1885 bool "Provide old way to pass kernel parameters"
1887 This was deprecated in 2001 and announced to live on for 5 years.
1888 Some old boot loaders still use this way.
1895 bool "Flattened Device Tree support"
1897 select OF_EARLY_FLATTREE
1900 Include support for flattened device tree machine descriptions.
1902 # Compressed boot loader in ROM. Yes, we really want to ask about
1903 # TEXT and BSS so we preserve their values in the config files.
1904 config ZBOOT_ROM_TEXT
1905 hex "Compressed ROM boot loader base address"
1908 The physical address at which the ROM-able zImage is to be
1909 placed in the target. Platforms which normally make use of
1910 ROM-able zImage formats normally set this to a suitable
1911 value in their defconfig file.
1913 If ZBOOT_ROM is not enabled, this has no effect.
1915 config ZBOOT_ROM_BSS
1916 hex "Compressed ROM boot loader BSS address"
1919 The base address of an area of read/write memory in the target
1920 for the ROM-able zImage which must be available while the
1921 decompressor is running. It must be large enough to hold the
1922 entire decompressed kernel plus an additional 128 KiB.
1923 Platforms which normally make use of ROM-able zImage formats
1924 normally set this to a suitable value in their defconfig file.
1926 If ZBOOT_ROM is not enabled, this has no effect.
1929 bool "Compressed boot loader in ROM/flash"
1930 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1932 Say Y here if you intend to execute your compressed kernel image
1933 (zImage) directly from ROM or flash. If unsure, say N.
1936 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1937 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1938 default ZBOOT_ROM_NONE
1940 Include experimental SD/MMC loading code in the ROM-able zImage.
1941 With this enabled it is possible to write the ROM-able zImage
1942 kernel image to an MMC or SD card and boot the kernel straight
1943 from the reset vector. At reset the processor Mask ROM will load
1944 the first part of the ROM-able zImage which in turn loads the
1945 rest the kernel image to RAM.
1947 config ZBOOT_ROM_NONE
1948 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1950 Do not load image from SD or MMC
1952 config ZBOOT_ROM_MMCIF
1953 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1955 Load image from MMCIF hardware block.
1957 config ZBOOT_ROM_SH_MOBILE_SDHI
1958 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1960 Load image from SDHI hardware block
1964 config ARM_APPENDED_DTB
1965 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1966 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1968 With this option, the boot code will look for a device tree binary
1969 (DTB) appended to zImage
1970 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1972 This is meant as a backward compatibility convenience for those
1973 systems with a bootloader that can't be upgraded to accommodate
1974 the documented boot protocol using a device tree.
1976 Beware that there is very little in terms of protection against
1977 this option being confused by leftover garbage in memory that might
1978 look like a DTB header after a reboot if no actual DTB is appended
1979 to zImage. Do not leave this option active in a production kernel
1980 if you don't intend to always append a DTB. Proper passing of the
1981 location into r2 of a bootloader provided DTB is always preferable
1984 config ARM_ATAG_DTB_COMPAT
1985 bool "Supplement the appended DTB with traditional ATAG information"
1986 depends on ARM_APPENDED_DTB
1988 Some old bootloaders can't be updated to a DTB capable one, yet
1989 they provide ATAGs with memory configuration, the ramdisk address,
1990 the kernel cmdline string, etc. Such information is dynamically
1991 provided by the bootloader and can't always be stored in a static
1992 DTB. To allow a device tree enabled kernel to be used with such
1993 bootloaders, this option allows zImage to extract the information
1994 from the ATAG list and store it at run time into the appended DTB.
1997 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1998 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2000 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2001 bool "Use bootloader kernel arguments if available"
2003 Uses the command-line options passed by the boot loader instead of
2004 the device tree bootargs property. If the boot loader doesn't provide
2005 any, the device tree bootargs property will be used.
2007 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2008 bool "Extend with bootloader kernel arguments"
2010 The command-line arguments provided by the boot loader will be
2011 appended to the the device tree bootargs property.
2016 string "Default kernel command string"
2019 On some architectures (EBSA110 and CATS), there is currently no way
2020 for the boot loader to pass arguments to the kernel. For these
2021 architectures, you should supply some command-line options at build
2022 time by entering them here. As a minimum, you should specify the
2023 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2026 prompt "Kernel command line type" if CMDLINE != ""
2027 default CMDLINE_FROM_BOOTLOADER
2029 config CMDLINE_FROM_BOOTLOADER
2030 bool "Use bootloader kernel arguments if available"
2032 Uses the command-line options passed by the boot loader. If
2033 the boot loader doesn't provide any, the default kernel command
2034 string provided in CMDLINE will be used.
2036 config CMDLINE_EXTEND
2037 bool "Extend bootloader kernel arguments"
2039 The command-line arguments provided by the boot loader will be
2040 appended to the default kernel command string.
2042 config CMDLINE_FORCE
2043 bool "Always use the default kernel command string"
2045 Always use the default kernel command string, even if the boot
2046 loader passes other arguments to the kernel.
2047 This is useful if you cannot or don't want to change the
2048 command-line options your boot loader passes to the kernel.
2052 bool "Kernel Execute-In-Place from ROM"
2053 depends on !ZBOOT_ROM && !ARM_LPAE
2055 Execute-In-Place allows the kernel to run from non-volatile storage
2056 directly addressable by the CPU, such as NOR flash. This saves RAM
2057 space since the text section of the kernel is not loaded from flash
2058 to RAM. Read-write sections, such as the data section and stack,
2059 are still copied to RAM. The XIP kernel is not compressed since
2060 it has to run directly from flash, so it will take more space to
2061 store it. The flash address used to link the kernel object files,
2062 and for storing it, is configuration dependent. Therefore, if you
2063 say Y here, you must know the proper physical address where to
2064 store the kernel image depending on your own flash memory usage.
2066 Also note that the make target becomes "make xipImage" rather than
2067 "make zImage" or "make Image". The final kernel binary to put in
2068 ROM memory will be arch/arm/boot/xipImage.
2072 config XIP_PHYS_ADDR
2073 hex "XIP Kernel Physical Location"
2074 depends on XIP_KERNEL
2075 default "0x00080000"
2077 This is the physical address in your flash memory the kernel will
2078 be linked for and stored to. This address is dependent on your
2082 bool "Kexec system call (EXPERIMENTAL)"
2083 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2085 kexec is a system call that implements the ability to shutdown your
2086 current kernel, and to start another kernel. It is like a reboot
2087 but it is independent of the system firmware. And like a reboot
2088 you can start any kernel with it, not just Linux.
2090 It is an ongoing process to be certain the hardware in a machine
2091 is properly shutdown, so do not be surprised if this code does not
2092 initially work for you. It may help to enable device hotplugging
2096 bool "Export atags in procfs"
2100 Should the atags used to boot the kernel be exported in an "atags"
2101 file in procfs. Useful with kexec.
2104 bool "Build kdump crash kernel (EXPERIMENTAL)"
2105 depends on EXPERIMENTAL
2107 Generate crash dump after being started by kexec. This should
2108 be normally only set in special crash dump kernels which are
2109 loaded in the main kernel with kexec-tools into a specially
2110 reserved region and then later executed after a crash by
2111 kdump/kexec. The crash dump kernel must be compiled to a
2112 memory address not used by the main kernel
2114 For more details see Documentation/kdump/kdump.txt
2116 config AUTO_ZRELADDR
2117 bool "Auto calculation of the decompressed kernel image address"
2118 depends on !ZBOOT_ROM && !ARCH_U300
2120 ZRELADDR is the physical address where the decompressed kernel
2121 image will be placed. If AUTO_ZRELADDR is selected, the address
2122 will be determined at run-time by masking the current IP with
2123 0xf8000000. This assumes the zImage being placed in the first 128MB
2124 from start of memory.
2128 menu "CPU Power Management"
2132 source "drivers/cpufreq/Kconfig"
2135 tristate "CPUfreq driver for i.MX CPUs"
2136 depends on ARCH_MXC && CPU_FREQ
2138 This enables the CPUfreq driver for i.MX CPUs.
2140 config CPU_FREQ_SA1100
2143 config CPU_FREQ_SA1110
2146 config CPU_FREQ_INTEGRATOR
2147 tristate "CPUfreq driver for ARM Integrator CPUs"
2148 depends on ARCH_INTEGRATOR && CPU_FREQ
2151 This enables the CPUfreq driver for ARM Integrator CPUs.
2153 For details, take a look at <file:Documentation/cpu-freq>.
2159 depends on CPU_FREQ && ARCH_PXA && PXA25x
2161 select CPU_FREQ_TABLE
2162 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2167 Internal configuration node for common cpufreq on Samsung SoC
2169 config CPU_FREQ_S3C24XX
2170 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2171 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2174 This enables the CPUfreq driver for the Samsung S3C24XX family
2177 For details, take a look at <file:Documentation/cpu-freq>.
2181 config CPU_FREQ_S3C24XX_PLL
2182 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2183 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2185 Compile in support for changing the PLL frequency from the
2186 S3C24XX series CPUfreq driver. The PLL takes time to settle
2187 after a frequency change, so by default it is not enabled.
2189 This also means that the PLL tables for the selected CPU(s) will
2190 be built which may increase the size of the kernel image.
2192 config CPU_FREQ_S3C24XX_DEBUG
2193 bool "Debug CPUfreq Samsung driver core"
2194 depends on CPU_FREQ_S3C24XX
2196 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2198 config CPU_FREQ_S3C24XX_IODEBUG
2199 bool "Debug CPUfreq Samsung driver IO timing"
2200 depends on CPU_FREQ_S3C24XX
2202 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2204 config CPU_FREQ_S3C24XX_DEBUGFS
2205 bool "Export debugfs for CPUFreq"
2206 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2208 Export status information via debugfs.
2212 source "drivers/cpuidle/Kconfig"
2216 menu "Floating point emulation"
2218 comment "At least one emulation must be selected"
2221 bool "NWFPE math emulation"
2222 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2224 Say Y to include the NWFPE floating point emulator in the kernel.
2225 This is necessary to run most binaries. Linux does not currently
2226 support floating point hardware so you need to say Y here even if
2227 your machine has an FPA or floating point co-processor podule.
2229 You may say N here if you are going to load the Acorn FPEmulator
2230 early in the bootup.
2233 bool "Support extended precision"
2234 depends on FPE_NWFPE
2236 Say Y to include 80-bit support in the kernel floating-point
2237 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2238 Note that gcc does not generate 80-bit operations by default,
2239 so in most cases this option only enlarges the size of the
2240 floating point emulator without any good reason.
2242 You almost surely want to say N here.
2245 bool "FastFPE math emulation (EXPERIMENTAL)"
2246 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2248 Say Y here to include the FAST floating point emulator in the kernel.
2249 This is an experimental much faster emulator which now also has full
2250 precision for the mantissa. It does not support any exceptions.
2251 It is very simple, and approximately 3-6 times faster than NWFPE.
2253 It should be sufficient for most programs. It may be not suitable
2254 for scientific calculations, but you have to check this for yourself.
2255 If you do not feel you need a faster FP emulation you should better
2259 bool "VFP-format floating point maths"
2260 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2262 Say Y to include VFP support code in the kernel. This is needed
2263 if your hardware includes a VFP unit.
2265 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2266 release notes and additional status information.
2268 Say N if your target does not have VFP hardware.
2276 bool "Advanced SIMD (NEON) Extension support"
2277 depends on VFPv3 && CPU_V7
2279 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2284 menu "Userspace binary formats"
2286 source "fs/Kconfig.binfmt"
2289 tristate "RISC OS personality"
2292 Say Y here to include the kernel code necessary if you want to run
2293 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2294 experimental; if this sounds frightening, say N and sleep in peace.
2295 You can also say M here to compile this support as a module (which
2296 will be called arthur).
2300 menu "Power management options"
2302 source "kernel/power/Kconfig"
2304 config ARCH_SUSPEND_POSSIBLE
2305 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2306 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2307 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2310 config ARM_CPU_SUSPEND
2315 source "net/Kconfig"
2317 source "drivers/Kconfig"
2321 source "arch/arm/Kconfig.debug"
2323 source "security/Kconfig"
2325 source "crypto/Kconfig"
2327 source "lib/Kconfig"