5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 source "init/Kconfig"
231 source "kernel/Kconfig.freezer"
236 bool "MMU-based Paged Memory Management Support"
239 Select if you want MMU-based virtualised addressing space
240 support by paged memory management. If unsure, say 'Y'.
243 # The "ARM system type" choice list is ordered alphabetically by option
244 # text. Please add new entries in the option alphabetic order.
247 prompt "ARM system type"
248 default ARCH_VERSATILE
250 config ARCH_INTEGRATOR
251 bool "ARM Ltd. Integrator family"
253 select ARCH_HAS_CPUFREQ
255 select HAVE_MACH_CLKDEV
257 select GENERIC_CLOCKEVENTS
258 select PLAT_VERSATILE
259 select PLAT_VERSATILE_FPGA_IRQ
260 select NEED_MACH_MEMORY_H
262 Support for ARM's Integrator platform.
265 bool "ARM Ltd. RealView family"
268 select HAVE_MACH_CLKDEV
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select ARM_TIMER_SP804
275 select GPIO_PL061 if GPIOLIB
276 select NEED_MACH_MEMORY_H
278 This enables support for ARM Ltd RealView boards.
280 config ARCH_VERSATILE
281 bool "ARM Ltd. Versatile family"
285 select HAVE_MACH_CLKDEV
287 select GENERIC_CLOCKEVENTS
288 select ARCH_WANT_OPTIONAL_GPIOLIB
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
291 select PLAT_VERSATILE_FPGA_IRQ
292 select ARM_TIMER_SP804
294 This enables support for ARM Ltd Versatile board.
297 bool "ARM Ltd. Versatile Express family"
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select ARM_TIMER_SP804
302 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
305 select HAVE_PATA_PLATFORM
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
310 This enables support for the ARM Ltd Versatile Express boards.
314 select ARCH_REQUIRE_GPIOLIB
318 This enables support for systems based on the Atmel AT91RM9200,
319 AT91SAM9 and AT91CAP9 processors.
322 bool "Broadcom BCMRING"
326 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 Support for Broadcom's BCMRing platform.
334 bool "Cirrus Logic CLPS711x/EP721x-based"
336 select ARCH_USES_GETTIMEOFFSET
337 select NEED_MACH_MEMORY_H
339 Support for Cirrus Logic 711x/721x based boards.
342 bool "Cavium Networks CNS3XXX family"
344 select GENERIC_CLOCKEVENTS
346 select MIGHT_HAVE_PCI
347 select PCI_DOMAINS if PCI
349 Support for Cavium Networks CNS3XXX platform.
352 bool "Cortina Systems Gemini"
354 select ARCH_REQUIRE_GPIOLIB
355 select ARCH_USES_GETTIMEOFFSET
357 Support for the Cortina Systems Gemini family SoCs
360 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
364 select GENERIC_CLOCKEVENTS
366 select GENERIC_IRQ_CHIP
370 Support for CSR SiRFSoC ARM Cortex A9 Platform
377 select ARCH_USES_GETTIMEOFFSET
378 select NEED_MACH_MEMORY_H
380 This is an evaluation board for the StrongARM processor available
381 from Digital. It has limited hardware on-board, including an
382 Ethernet interface, two PCMCIA sockets, two serial ports and a
391 select ARCH_REQUIRE_GPIOLIB
392 select ARCH_HAS_HOLES_MEMORYMODEL
393 select ARCH_USES_GETTIMEOFFSET
396 This enables support for the Cirrus EP93xx series of CPUs.
398 config ARCH_FOOTBRIDGE
402 select GENERIC_CLOCKEVENTS
403 select NEED_MACH_MEMORY_H
405 Support for systems based on the DC21285 companion chip
406 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
409 bool "Freescale MXC/iMX-based"
410 select GENERIC_CLOCKEVENTS
411 select ARCH_REQUIRE_GPIOLIB
414 select GENERIC_IRQ_CHIP
415 select HAVE_SCHED_CLOCK
417 Support for Freescale MXC/iMX-based family of processors
420 bool "Freescale MXS-based"
421 select GENERIC_CLOCKEVENTS
422 select ARCH_REQUIRE_GPIOLIB
426 Support for Freescale MXS-based family of processors
429 bool "Hilscher NetX based"
433 select GENERIC_CLOCKEVENTS
435 This enables support for systems based on the Hilscher NetX Soc
438 bool "Hynix HMS720x-based"
441 select ARCH_USES_GETTIMEOFFSET
443 This enables support for systems based on the Hynix HMS720x
451 select ARCH_SUPPORTS_MSI
453 select NEED_MACH_MEMORY_H
455 Support for Intel's IOP13XX (XScale) family of processors.
463 select ARCH_REQUIRE_GPIOLIB
465 Support for Intel's 80219 and IOP32X (XScale) family of
474 select ARCH_REQUIRE_GPIOLIB
476 Support for Intel's IOP33X (XScale) family of processors.
483 select ARCH_USES_GETTIMEOFFSET
484 select NEED_MACH_MEMORY_H
486 Support for Intel's IXP23xx (XScale) family of processors.
489 bool "IXP2400/2800-based"
493 select ARCH_USES_GETTIMEOFFSET
494 select NEED_MACH_MEMORY_H
496 Support for Intel's IXP2400/2800 (XScale) family of processors.
504 select GENERIC_CLOCKEVENTS
505 select HAVE_SCHED_CLOCK
506 select MIGHT_HAVE_PCI
507 select DMABOUNCE if PCI
509 Support for Intel's IXP4XX (XScale) family of processors.
515 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
519 Support for the Marvell Dove SoC 88AP510
522 bool "Marvell Kirkwood"
525 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
529 Support for the following Marvell Kirkwood series SoCs:
530 88F6180, 88F6192 and 88F6281.
536 select ARCH_REQUIRE_GPIOLIB
539 select USB_ARCH_HAS_OHCI
542 select GENERIC_CLOCKEVENTS
544 Support for the NXP LPC32XX family of processors
547 bool "Marvell MV78xx0"
550 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 Support for the following Marvell MV78xx0 series SoCs:
562 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
566 Support for the following Marvell Orion 5x series SoCs:
567 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
568 Orion-2 (5281), Orion-1-90 (6183).
571 bool "Marvell PXA168/910/MMP2"
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
576 select HAVE_SCHED_CLOCK
581 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
584 bool "Micrel/Kendin KS8695"
586 select ARCH_REQUIRE_GPIOLIB
587 select ARCH_USES_GETTIMEOFFSET
588 select NEED_MACH_MEMORY_H
590 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
591 System-on-Chip devices.
594 bool "Nuvoton W90X900 CPU"
596 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
601 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
602 At present, the w90x900 has been renamed nuc900, regarding
603 the ARM series product line, you can login the following
604 link address to know more.
606 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
607 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
610 bool "Nuvoton NUC93X CPU"
614 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
615 low-power and high performance MPEG-4/JPEG multimedia controller chip.
622 select GENERIC_CLOCKEVENTS
625 select HAVE_SCHED_CLOCK
626 select ARCH_HAS_CPUFREQ
628 This enables support for NVIDIA Tegra based systems (Tegra APX,
629 Tegra 6xx and Tegra 2 series).
632 bool "Philips Nexperia PNX4008 Mobile"
635 select ARCH_USES_GETTIMEOFFSET
637 This enables support for Philips PNX4008 mobile platform.
640 bool "PXA2xx/PXA3xx-based"
643 select ARCH_HAS_CPUFREQ
646 select ARCH_REQUIRE_GPIOLIB
647 select GENERIC_CLOCKEVENTS
648 select HAVE_SCHED_CLOCK
653 select MULTI_IRQ_HANDLER
655 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
660 select GENERIC_CLOCKEVENTS
661 select ARCH_REQUIRE_GPIOLIB
664 Support for Qualcomm MSM/QSD based systems. This runs on the
665 apps processor of the MSM/QSD and depends on a shared memory
666 interface to the modem processor which runs the baseband
667 stack and controls some vital subsystems
668 (clock and power control, etc).
671 bool "Renesas SH-Mobile / R-Mobile"
674 select HAVE_MACH_CLKDEV
675 select GENERIC_CLOCKEVENTS
678 select MULTI_IRQ_HANDLER
679 select PM_GENERIC_DOMAINS if PM
680 select NEED_MACH_MEMORY_H
682 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
689 select ARCH_MAY_HAVE_PC_FDC
690 select HAVE_PATA_PLATFORM
693 select ARCH_SPARSEMEM_ENABLE
694 select ARCH_USES_GETTIMEOFFSET
695 select NEED_MACH_MEMORY_H
697 On the Acorn Risc-PC, Linux can support the internal IDE disk and
698 CD-ROM interface, serial and parallel port, and the floppy drive.
705 select ARCH_SPARSEMEM_ENABLE
707 select ARCH_HAS_CPUFREQ
709 select GENERIC_CLOCKEVENTS
711 select HAVE_SCHED_CLOCK
713 select ARCH_REQUIRE_GPIOLIB
714 select NEED_MACH_MEMORY_H
716 Support for StrongARM 11x0 based boards.
719 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
721 select ARCH_HAS_CPUFREQ
724 select ARCH_USES_GETTIMEOFFSET
725 select HAVE_S3C2410_I2C if I2C
727 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
728 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
729 the Samsung SMDK2410 development board (and derivatives).
731 Note, the S3C2416 and the S3C2450 are so close that they even share
732 the same SoC ID code. This means that there is no separate machine
733 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
736 bool "Samsung S3C64XX"
743 select ARCH_USES_GETTIMEOFFSET
744 select ARCH_HAS_CPUFREQ
745 select ARCH_REQUIRE_GPIOLIB
746 select SAMSUNG_CLKSRC
747 select SAMSUNG_IRQ_VIC_TIMER
748 select SAMSUNG_IRQ_UART
749 select S3C_GPIO_TRACK
750 select S3C_GPIO_PULL_UPDOWN
751 select S3C_GPIO_CFG_S3C24XX
752 select S3C_GPIO_CFG_S3C64XX
754 select USB_ARCH_HAS_OHCI
755 select SAMSUNG_GPIOLIB_4BIT
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
759 Samsung S3C64XX series based systems
762 bool "Samsung S5P6440 S5P6450"
768 select HAVE_S3C2410_WATCHDOG if WATCHDOG
769 select GENERIC_CLOCKEVENTS
770 select HAVE_SCHED_CLOCK
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C_RTC if RTC_CLASS
774 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
778 bool "Samsung S5PC100"
783 select ARM_L1_CACHE_SHIFT_6
784 select ARCH_USES_GETTIMEOFFSET
785 select HAVE_S3C2410_I2C if I2C
786 select HAVE_S3C_RTC if RTC_CLASS
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 Samsung S5PC100 series based systems
792 bool "Samsung S5PV210/S5PC110"
794 select ARCH_SPARSEMEM_ENABLE
795 select ARCH_HAS_HOLES_MEMORYMODEL
800 select ARM_L1_CACHE_SHIFT_6
801 select ARCH_HAS_CPUFREQ
802 select GENERIC_CLOCKEVENTS
803 select HAVE_SCHED_CLOCK
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C_RTC if RTC_CLASS
806 select HAVE_S3C2410_WATCHDOG if WATCHDOG
807 select NEED_MACH_MEMORY_H
809 Samsung S5PV210/S5PC110 series based systems
812 bool "Samsung EXYNOS4"
814 select ARCH_SPARSEMEM_ENABLE
815 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_HAS_CPUFREQ
820 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C_RTC if RTC_CLASS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select NEED_MACH_MEMORY_H
826 Samsung EXYNOS4 series based systems
835 select ARCH_USES_GETTIMEOFFSET
836 select NEED_MACH_MEMORY_H
838 Support for the StrongARM based Digital DNARD machine, also known
839 as "Shark" (<http://www.shark-linux.de/shark.html>).
842 bool "Telechips TCC ARM926-based systems"
847 select GENERIC_CLOCKEVENTS
849 Support for Telechips TCC ARM926-based systems.
852 bool "ST-Ericsson U300 Series"
856 select HAVE_SCHED_CLOCK
860 select GENERIC_CLOCKEVENTS
862 select HAVE_MACH_CLKDEV
864 select NEED_MACH_MEMORY_H
866 Support for ST-Ericsson U300 series mobile platforms.
869 bool "ST-Ericsson U8500 Series"
872 select GENERIC_CLOCKEVENTS
874 select ARCH_REQUIRE_GPIOLIB
875 select ARCH_HAS_CPUFREQ
877 Support for ST-Ericsson's Ux500 architecture
880 bool "STMicroelectronics Nomadik"
885 select GENERIC_CLOCKEVENTS
886 select ARCH_REQUIRE_GPIOLIB
888 Support for the Nomadik platform by ST-Ericsson
892 select GENERIC_CLOCKEVENTS
893 select ARCH_REQUIRE_GPIOLIB
897 select GENERIC_ALLOCATOR
898 select GENERIC_IRQ_CHIP
899 select ARCH_HAS_HOLES_MEMORYMODEL
901 Support for TI's DaVinci platform.
906 select ARCH_REQUIRE_GPIOLIB
907 select ARCH_HAS_CPUFREQ
909 select GENERIC_CLOCKEVENTS
910 select HAVE_SCHED_CLOCK
911 select ARCH_HAS_HOLES_MEMORYMODEL
913 Support for TI's OMAP platform (OMAP1/2/3/4).
918 select ARCH_REQUIRE_GPIOLIB
921 select GENERIC_CLOCKEVENTS
924 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 bool "VIA/WonderMedia 85xx"
930 select ARCH_HAS_CPUFREQ
931 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
935 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
938 bool "Xilinx Zynq ARM Cortex A9 Platform"
941 select GENERIC_CLOCKEVENTS
948 Support for Xilinx Zynq ARM Cortex A9 Platform
952 # This is sorted alphabetically by mach-* pathname. However, plat-*
953 # Kconfigs may be included either alphabetically (according to the
954 # plat- suffix) or along side the corresponding mach-* source.
956 source "arch/arm/mach-at91/Kconfig"
958 source "arch/arm/mach-bcmring/Kconfig"
960 source "arch/arm/mach-clps711x/Kconfig"
962 source "arch/arm/mach-cns3xxx/Kconfig"
964 source "arch/arm/mach-davinci/Kconfig"
966 source "arch/arm/mach-dove/Kconfig"
968 source "arch/arm/mach-ep93xx/Kconfig"
970 source "arch/arm/mach-footbridge/Kconfig"
972 source "arch/arm/mach-gemini/Kconfig"
974 source "arch/arm/mach-h720x/Kconfig"
976 source "arch/arm/mach-integrator/Kconfig"
978 source "arch/arm/mach-iop32x/Kconfig"
980 source "arch/arm/mach-iop33x/Kconfig"
982 source "arch/arm/mach-iop13xx/Kconfig"
984 source "arch/arm/mach-ixp4xx/Kconfig"
986 source "arch/arm/mach-ixp2000/Kconfig"
988 source "arch/arm/mach-ixp23xx/Kconfig"
990 source "arch/arm/mach-kirkwood/Kconfig"
992 source "arch/arm/mach-ks8695/Kconfig"
994 source "arch/arm/mach-lpc32xx/Kconfig"
996 source "arch/arm/mach-msm/Kconfig"
998 source "arch/arm/mach-mv78xx0/Kconfig"
1000 source "arch/arm/plat-mxc/Kconfig"
1002 source "arch/arm/mach-mxs/Kconfig"
1004 source "arch/arm/mach-netx/Kconfig"
1006 source "arch/arm/mach-nomadik/Kconfig"
1007 source "arch/arm/plat-nomadik/Kconfig"
1009 source "arch/arm/mach-nuc93x/Kconfig"
1011 source "arch/arm/plat-omap/Kconfig"
1013 source "arch/arm/mach-omap1/Kconfig"
1015 source "arch/arm/mach-omap2/Kconfig"
1017 source "arch/arm/mach-orion5x/Kconfig"
1019 source "arch/arm/mach-pxa/Kconfig"
1020 source "arch/arm/plat-pxa/Kconfig"
1022 source "arch/arm/mach-mmp/Kconfig"
1024 source "arch/arm/mach-realview/Kconfig"
1026 source "arch/arm/mach-sa1100/Kconfig"
1028 source "arch/arm/plat-samsung/Kconfig"
1029 source "arch/arm/plat-s3c24xx/Kconfig"
1030 source "arch/arm/plat-s5p/Kconfig"
1032 source "arch/arm/plat-spear/Kconfig"
1034 source "arch/arm/plat-tcc/Kconfig"
1037 source "arch/arm/mach-s3c2410/Kconfig"
1038 source "arch/arm/mach-s3c2412/Kconfig"
1039 source "arch/arm/mach-s3c2416/Kconfig"
1040 source "arch/arm/mach-s3c2440/Kconfig"
1041 source "arch/arm/mach-s3c2443/Kconfig"
1045 source "arch/arm/mach-s3c64xx/Kconfig"
1048 source "arch/arm/mach-s5p64x0/Kconfig"
1050 source "arch/arm/mach-s5pc100/Kconfig"
1052 source "arch/arm/mach-s5pv210/Kconfig"
1054 source "arch/arm/mach-exynos4/Kconfig"
1056 source "arch/arm/mach-shmobile/Kconfig"
1058 source "arch/arm/mach-tegra/Kconfig"
1060 source "arch/arm/mach-u300/Kconfig"
1062 source "arch/arm/mach-ux500/Kconfig"
1064 source "arch/arm/mach-versatile/Kconfig"
1066 source "arch/arm/mach-vexpress/Kconfig"
1067 source "arch/arm/plat-versatile/Kconfig"
1069 source "arch/arm/mach-vt8500/Kconfig"
1071 source "arch/arm/mach-w90x900/Kconfig"
1073 # Definitions to make life easier
1079 select GENERIC_CLOCKEVENTS
1080 select HAVE_SCHED_CLOCK
1085 select GENERIC_IRQ_CHIP
1086 select HAVE_SCHED_CLOCK
1091 config PLAT_VERSATILE
1094 config ARM_TIMER_SP804
1098 source arch/arm/mm/Kconfig
1101 bool "Enable iWMMXt support"
1102 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1103 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1105 Enable support for iWMMXt context switching at run time if
1106 running on a CPU that supports it.
1108 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1111 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1115 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1116 (!ARCH_OMAP3 || OMAP3_EMU)
1120 config MULTI_IRQ_HANDLER
1123 Allow each machine to specify it's own IRQ handler at run time.
1126 source "arch/arm/Kconfig-nommu"
1129 config ARM_ERRATA_411920
1130 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1131 depends on CPU_V6 || CPU_V6K
1133 Invalidation of the Instruction Cache operation can
1134 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1135 It does not affect the MPCore. This option enables the ARM Ltd.
1136 recommended workaround.
1138 config ARM_ERRATA_430973
1139 bool "ARM errata: Stale prediction on replaced interworking branch"
1142 This option enables the workaround for the 430973 Cortex-A8
1143 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1144 interworking branch is replaced with another code sequence at the
1145 same virtual address, whether due to self-modifying code or virtual
1146 to physical address re-mapping, Cortex-A8 does not recover from the
1147 stale interworking branch prediction. This results in Cortex-A8
1148 executing the new code sequence in the incorrect ARM or Thumb state.
1149 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1150 and also flushes the branch target cache at every context switch.
1151 Note that setting specific bits in the ACTLR register may not be
1152 available in non-secure mode.
1154 config ARM_ERRATA_458693
1155 bool "ARM errata: Processor deadlock when a false hazard is created"
1158 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1159 erratum. For very specific sequences of memory operations, it is
1160 possible for a hazard condition intended for a cache line to instead
1161 be incorrectly associated with a different cache line. This false
1162 hazard might then cause a processor deadlock. The workaround enables
1163 the L1 caching of the NEON accesses and disables the PLD instruction
1164 in the ACTLR register. Note that setting specific bits in the ACTLR
1165 register may not be available in non-secure mode.
1167 config ARM_ERRATA_460075
1168 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1171 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1172 erratum. Any asynchronous access to the L2 cache may encounter a
1173 situation in which recent store transactions to the L2 cache are lost
1174 and overwritten with stale memory contents from external memory. The
1175 workaround disables the write-allocate mode for the L2 cache via the
1176 ACTLR register. Note that setting specific bits in the ACTLR register
1177 may not be available in non-secure mode.
1179 config ARM_ERRATA_742230
1180 bool "ARM errata: DMB operation may be faulty"
1181 depends on CPU_V7 && SMP
1183 This option enables the workaround for the 742230 Cortex-A9
1184 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1185 between two write operations may not ensure the correct visibility
1186 ordering of the two writes. This workaround sets a specific bit in
1187 the diagnostic register of the Cortex-A9 which causes the DMB
1188 instruction to behave as a DSB, ensuring the correct behaviour of
1191 config ARM_ERRATA_742231
1192 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1193 depends on CPU_V7 && SMP
1195 This option enables the workaround for the 742231 Cortex-A9
1196 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1197 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1198 accessing some data located in the same cache line, may get corrupted
1199 data due to bad handling of the address hazard when the line gets
1200 replaced from one of the CPUs at the same time as another CPU is
1201 accessing it. This workaround sets specific bits in the diagnostic
1202 register of the Cortex-A9 which reduces the linefill issuing
1203 capabilities of the processor.
1205 config PL310_ERRATA_588369
1206 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1207 depends on CACHE_L2X0
1209 The PL310 L2 cache controller implements three types of Clean &
1210 Invalidate maintenance operations: by Physical Address
1211 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1212 They are architecturally defined to behave as the execution of a
1213 clean operation followed immediately by an invalidate operation,
1214 both performing to the same memory location. This functionality
1215 is not correctly implemented in PL310 as clean lines are not
1216 invalidated as a result of these operations.
1218 config ARM_ERRATA_720789
1219 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1220 depends on CPU_V7 && SMP
1222 This option enables the workaround for the 720789 Cortex-A9 (prior to
1223 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1224 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1225 As a consequence of this erratum, some TLB entries which should be
1226 invalidated are not, resulting in an incoherency in the system page
1227 tables. The workaround changes the TLB flushing routines to invalidate
1228 entries regardless of the ASID.
1230 config PL310_ERRATA_727915
1231 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1232 depends on CACHE_L2X0
1234 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1235 operation (offset 0x7FC). This operation runs in background so that
1236 PL310 can handle normal accesses while it is in progress. Under very
1237 rare circumstances, due to this erratum, write data can be lost when
1238 PL310 treats a cacheable write transaction during a Clean &
1239 Invalidate by Way operation.
1241 config ARM_ERRATA_743622
1242 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1245 This option enables the workaround for the 743622 Cortex-A9
1246 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1247 optimisation in the Cortex-A9 Store Buffer may lead to data
1248 corruption. This workaround sets a specific bit in the diagnostic
1249 register of the Cortex-A9 which disables the Store Buffer
1250 optimisation, preventing the defect from occurring. This has no
1251 visible impact on the overall performance or power consumption of the
1254 config ARM_ERRATA_751472
1255 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 751472 Cortex-A9 (prior
1259 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1260 completion of a following broadcasted operation if the second
1261 operation is received by a CPU before the ICIALLUIS has completed,
1262 potentially leading to corrupted entries in the cache or TLB.
1264 config ARM_ERRATA_753970
1265 bool "ARM errata: cache sync operation may be faulty"
1266 depends on CACHE_PL310
1268 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1270 Under some condition the effect of cache sync operation on
1271 the store buffer still remains when the operation completes.
1272 This means that the store buffer is always asked to drain and
1273 this prevents it from merging any further writes. The workaround
1274 is to replace the normal offset of cache sync operation (0x730)
1275 by another offset targeting an unmapped PL310 register 0x740.
1276 This has the same effect as the cache sync operation: store buffer
1277 drain and waiting for all buffers empty.
1279 config ARM_ERRATA_754322
1280 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1283 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1284 r3p*) erratum. A speculative memory access may cause a page table walk
1285 which starts prior to an ASID switch but completes afterwards. This
1286 can populate the micro-TLB with a stale entry which may be hit with
1287 the new ASID. This workaround places two dsb instructions in the mm
1288 switching code so that no page table walks can cross the ASID switch.
1290 config ARM_ERRATA_754327
1291 bool "ARM errata: no automatic Store Buffer drain"
1292 depends on CPU_V7 && SMP
1294 This option enables the workaround for the 754327 Cortex-A9 (prior to
1295 r2p0) erratum. The Store Buffer does not have any automatic draining
1296 mechanism and therefore a livelock may occur if an external agent
1297 continuously polls a memory location waiting to observe an update.
1298 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1299 written polling loops from denying visibility of updates to memory.
1301 config ARM_ERRATA_364296
1302 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1303 depends on CPU_V6 && !SMP
1305 This options enables the workaround for the 364296 ARM1136
1306 r0p2 erratum (possible cache data corruption with
1307 hit-under-miss enabled). It sets the undocumented bit 31 in
1308 the auxiliary control register and the FI bit in the control
1309 register, thus disabling hit-under-miss without putting the
1310 processor into full low interrupt latency mode. ARM11MPCore
1313 config ARM_ERRATA_764369
1314 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1315 depends on CPU_V7 && SMP
1317 This option enables the workaround for erratum 764369
1318 affecting Cortex-A9 MPCore with two or more processors (all
1319 current revisions). Under certain timing circumstances, a data
1320 cache line maintenance operation by MVA targeting an Inner
1321 Shareable memory region may fail to proceed up to either the
1322 Point of Coherency or to the Point of Unification of the
1323 system. This workaround adds a DSB instruction before the
1324 relevant cache maintenance functions and sets a specific bit
1325 in the diagnostic control register of the SCU.
1329 source "arch/arm/common/Kconfig"
1339 Find out whether you have ISA slots on your motherboard. ISA is the
1340 name of a bus system, i.e. the way the CPU talks to the other stuff
1341 inside your box. Other bus systems are PCI, EISA, MicroChannel
1342 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1343 newer boards don't support it. If you have ISA, say Y, otherwise N.
1345 # Select ISA DMA controller support
1350 # Select ISA DMA interface
1355 bool "PCI support" if MIGHT_HAVE_PCI
1357 Find out whether you have a PCI motherboard. PCI is the name of a
1358 bus system, i.e. the way the CPU talks to the other stuff inside
1359 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1360 VESA. If you have PCI, say Y, otherwise N.
1366 config PCI_NANOENGINE
1367 bool "BSE nanoEngine PCI support"
1368 depends on SA1100_NANOENGINE
1370 Enable PCI on the BSE nanoEngine board.
1375 # Select the host bridge type
1376 config PCI_HOST_VIA82C505
1378 depends on PCI && ARCH_SHARK
1381 config PCI_HOST_ITE8152
1383 depends on PCI && MACH_ARMCORE
1387 source "drivers/pci/Kconfig"
1389 source "drivers/pcmcia/Kconfig"
1393 menu "Kernel Features"
1395 source "kernel/time/Kconfig"
1398 bool "Symmetric Multi-Processing"
1399 depends on CPU_V6K || CPU_V7
1400 depends on GENERIC_CLOCKEVENTS
1401 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1402 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1403 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1404 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1405 select USE_GENERIC_SMP_HELPERS
1406 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1408 This enables support for systems with more than one CPU. If you have
1409 a system with only one CPU, like most personal computers, say N. If
1410 you have a system with more than one CPU, say Y.
1412 If you say N here, the kernel will run on single and multiprocessor
1413 machines, but will use only one CPU of a multiprocessor machine. If
1414 you say Y here, the kernel will run on many, but not all, single
1415 processor machines. On a single processor machine, the kernel will
1416 run faster if you say N here.
1418 See also <file:Documentation/i386/IO-APIC.txt>,
1419 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1420 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1422 If you don't know what to do here, say N.
1425 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1426 depends on EXPERIMENTAL
1427 depends on SMP && !XIP_KERNEL
1430 SMP kernels contain instructions which fail on non-SMP processors.
1431 Enabling this option allows the kernel to modify itself to make
1432 these instructions safe. Disabling it allows about 1K of space
1435 If you don't know what to do here, say Y.
1437 config ARM_CPU_TOPOLOGY
1438 bool "Support cpu topology definition"
1439 depends on SMP && CPU_V7
1442 Support ARM cpu topology definition. The MPIDR register defines
1443 affinity between processors which is then used to describe the cpu
1444 topology of an ARM System.
1447 bool "Multi-core scheduler support"
1448 depends on ARM_CPU_TOPOLOGY
1450 Multi-core scheduler support improves the CPU scheduler's decision
1451 making when dealing with multi-core CPU chips at a cost of slightly
1452 increased overhead in some places. If unsure say N here.
1455 bool "SMT scheduler support"
1456 depends on ARM_CPU_TOPOLOGY
1458 Improves the CPU scheduler's decision making when dealing with
1459 MultiThreading at a cost of slightly increased overhead in some
1460 places. If unsure say N here.
1465 This option enables support for the ARM system coherency unit
1472 This options enables support for the ARM timer and watchdog unit
1475 prompt "Memory split"
1478 Select the desired split between kernel and user memory.
1480 If you are not absolutely sure what you are doing, leave this
1484 bool "3G/1G user/kernel split"
1486 bool "2G/2G user/kernel split"
1488 bool "1G/3G user/kernel split"
1493 default 0x40000000 if VMSPLIT_1G
1494 default 0x80000000 if VMSPLIT_2G
1498 int "Maximum number of CPUs (2-32)"
1504 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1505 depends on SMP && HOTPLUG && EXPERIMENTAL
1507 Say Y here to experiment with turning CPUs off and on. CPUs
1508 can be controlled through /sys/devices/system/cpu.
1511 bool "Use local timer interrupts"
1514 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1516 Enable support for local timers on SMP platforms, rather then the
1517 legacy IPI broadcast method. Local timers allows the system
1518 accounting to be spread across the timer interval, preventing a
1519 "thundering herd" at every timer tick.
1521 source kernel/Kconfig.preempt
1525 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1526 ARCH_S5PV210 || ARCH_EXYNOS4
1527 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1528 default AT91_TIMER_HZ if ARCH_AT91
1529 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1532 config THUMB2_KERNEL
1533 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1534 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1536 select ARM_ASM_UNIFIED
1538 By enabling this option, the kernel will be compiled in
1539 Thumb-2 mode. A compiler/assembler that understand the unified
1540 ARM-Thumb syntax is needed.
1544 config THUMB2_AVOID_R_ARM_THM_JUMP11
1545 bool "Work around buggy Thumb-2 short branch relocations in gas"
1546 depends on THUMB2_KERNEL && MODULES
1549 Various binutils versions can resolve Thumb-2 branches to
1550 locally-defined, preemptible global symbols as short-range "b.n"
1551 branch instructions.
1553 This is a problem, because there's no guarantee the final
1554 destination of the symbol, or any candidate locations for a
1555 trampoline, are within range of the branch. For this reason, the
1556 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1557 relocation in modules at all, and it makes little sense to add
1560 The symptom is that the kernel fails with an "unsupported
1561 relocation" error when loading some modules.
1563 Until fixed tools are available, passing
1564 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1565 code which hits this problem, at the cost of a bit of extra runtime
1566 stack usage in some cases.
1568 The problem is described in more detail at:
1569 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1571 Only Thumb-2 kernels are affected.
1573 Unless you are sure your tools don't have this problem, say Y.
1575 config ARM_ASM_UNIFIED
1579 bool "Use the ARM EABI to compile the kernel"
1581 This option allows for the kernel to be compiled using the latest
1582 ARM ABI (aka EABI). This is only useful if you are using a user
1583 space environment that is also compiled with EABI.
1585 Since there are major incompatibilities between the legacy ABI and
1586 EABI, especially with regard to structure member alignment, this
1587 option also changes the kernel syscall calling convention to
1588 disambiguate both ABIs and allow for backward compatibility support
1589 (selected with CONFIG_OABI_COMPAT).
1591 To use this you need GCC version 4.0.0 or later.
1594 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1595 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1598 This option preserves the old syscall interface along with the
1599 new (ARM EABI) one. It also provides a compatibility layer to
1600 intercept syscalls that have structure arguments which layout
1601 in memory differs between the legacy ABI and the new ARM EABI
1602 (only for non "thumb" binaries). This option adds a tiny
1603 overhead to all syscalls and produces a slightly larger kernel.
1604 If you know you'll be using only pure EABI user space then you
1605 can say N here. If this option is not selected and you attempt
1606 to execute a legacy ABI binary then the result will be
1607 UNPREDICTABLE (in fact it can be predicted that it won't work
1608 at all). If in doubt say Y.
1610 config ARCH_HAS_HOLES_MEMORYMODEL
1613 config ARCH_SPARSEMEM_ENABLE
1616 config ARCH_SPARSEMEM_DEFAULT
1617 def_bool ARCH_SPARSEMEM_ENABLE
1619 config ARCH_SELECT_MEMORY_MODEL
1620 def_bool ARCH_SPARSEMEM_ENABLE
1622 config HAVE_ARCH_PFN_VALID
1623 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1626 bool "High Memory Support"
1629 The address space of ARM processors is only 4 Gigabytes large
1630 and it has to accommodate user address space, kernel address
1631 space as well as some memory mapped IO. That means that, if you
1632 have a large amount of physical memory and/or IO, not all of the
1633 memory can be "permanently mapped" by the kernel. The physical
1634 memory that is not permanently mapped is called "high memory".
1636 Depending on the selected kernel/user memory split, minimum
1637 vmalloc space and actual amount of RAM, you may not need this
1638 option which should result in a slightly faster kernel.
1643 bool "Allocate 2nd-level pagetables from highmem"
1646 config HW_PERF_EVENTS
1647 bool "Enable hardware performance counter support for perf events"
1648 depends on PERF_EVENTS && CPU_HAS_PMU
1651 Enable hardware performance counter support for perf events. If
1652 disabled, perf events will use software events only.
1656 config FORCE_MAX_ZONEORDER
1657 int "Maximum zone order" if ARCH_SHMOBILE
1658 range 11 64 if ARCH_SHMOBILE
1659 default "9" if SA1111
1662 The kernel memory allocator divides physically contiguous memory
1663 blocks into "zones", where each zone is a power of two number of
1664 pages. This option selects the largest power of two that the kernel
1665 keeps in the memory allocator. If you need to allocate very large
1666 blocks of physically contiguous memory, then you may need to
1667 increase this value.
1669 This config option is actually maximum order plus one. For example,
1670 a value of 11 means that the largest free memory block is 2^10 pages.
1673 bool "Timer and CPU usage LEDs"
1674 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1675 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1676 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1677 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1678 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1679 ARCH_AT91 || ARCH_DAVINCI || \
1680 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1682 If you say Y here, the LEDs on your machine will be used
1683 to provide useful information about your current system status.
1685 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1686 be able to select which LEDs are active using the options below. If
1687 you are compiling a kernel for the EBSA-110 or the LART however, the
1688 red LED will simply flash regularly to indicate that the system is
1689 still functional. It is safe to say Y here if you have a CATS
1690 system, but the driver will do nothing.
1693 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1694 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1695 || MACH_OMAP_PERSEUS2
1697 depends on !GENERIC_CLOCKEVENTS
1698 default y if ARCH_EBSA110
1700 If you say Y here, one of the system LEDs (the green one on the
1701 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1702 will flash regularly to indicate that the system is still
1703 operational. This is mainly useful to kernel hackers who are
1704 debugging unstable kernels.
1706 The LART uses the same LED for both Timer LED and CPU usage LED
1707 functions. You may choose to use both, but the Timer LED function
1708 will overrule the CPU usage LED.
1711 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1713 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1714 || MACH_OMAP_PERSEUS2
1717 If you say Y here, the red LED will be used to give a good real
1718 time indication of CPU usage, by lighting whenever the idle task
1719 is not currently executing.
1721 The LART uses the same LED for both Timer LED and CPU usage LED
1722 functions. You may choose to use both, but the Timer LED function
1723 will overrule the CPU usage LED.
1725 config ALIGNMENT_TRAP
1727 depends on CPU_CP15_MMU
1728 default y if !ARCH_EBSA110
1729 select HAVE_PROC_CPU if PROC_FS
1731 ARM processors cannot fetch/store information which is not
1732 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1733 address divisible by 4. On 32-bit ARM processors, these non-aligned
1734 fetch/store instructions will be emulated in software if you say
1735 here, which has a severe performance impact. This is necessary for
1736 correct operation of some network protocols. With an IP-only
1737 configuration it is safe to say N, otherwise say Y.
1739 config UACCESS_WITH_MEMCPY
1740 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1741 depends on MMU && EXPERIMENTAL
1742 default y if CPU_FEROCEON
1744 Implement faster copy_to_user and clear_user methods for CPU
1745 cores where a 8-word STM instruction give significantly higher
1746 memory write throughput than a sequence of individual 32bit stores.
1748 A possible side effect is a slight increase in scheduling latency
1749 between threads sharing the same address space if they invoke
1750 such copy operations with large buffers.
1752 However, if the CPU data cache is using a write-allocate mode,
1753 this option is unlikely to provide any performance gain.
1757 prompt "Enable seccomp to safely compute untrusted bytecode"
1759 This kernel feature is useful for number crunching applications
1760 that may need to compute untrusted bytecode during their
1761 execution. By using pipes or other transports made available to
1762 the process as file descriptors supporting the read/write
1763 syscalls, it's possible to isolate those applications in
1764 their own address space using seccomp. Once seccomp is
1765 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1766 and the task is only allowed to execute a few safe syscalls
1767 defined by each seccomp mode.
1769 config CC_STACKPROTECTOR
1770 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1771 depends on EXPERIMENTAL
1773 This option turns on the -fstack-protector GCC feature. This
1774 feature puts, at the beginning of functions, a canary value on
1775 the stack just before the return address, and validates
1776 the value just before actually returning. Stack based buffer
1777 overflows (that need to overwrite this return address) now also
1778 overwrite the canary, which gets detected and the attack is then
1779 neutralized via a kernel panic.
1780 This feature requires gcc version 4.2 or above.
1782 config DEPRECATED_PARAM_STRUCT
1783 bool "Provide old way to pass kernel parameters"
1785 This was deprecated in 2001 and announced to live on for 5 years.
1786 Some old boot loaders still use this way.
1793 bool "Flattened Device Tree support"
1795 select OF_EARLY_FLATTREE
1798 Include support for flattened device tree machine descriptions.
1800 # Compressed boot loader in ROM. Yes, we really want to ask about
1801 # TEXT and BSS so we preserve their values in the config files.
1802 config ZBOOT_ROM_TEXT
1803 hex "Compressed ROM boot loader base address"
1806 The physical address at which the ROM-able zImage is to be
1807 placed in the target. Platforms which normally make use of
1808 ROM-able zImage formats normally set this to a suitable
1809 value in their defconfig file.
1811 If ZBOOT_ROM is not enabled, this has no effect.
1813 config ZBOOT_ROM_BSS
1814 hex "Compressed ROM boot loader BSS address"
1817 The base address of an area of read/write memory in the target
1818 for the ROM-able zImage which must be available while the
1819 decompressor is running. It must be large enough to hold the
1820 entire decompressed kernel plus an additional 128 KiB.
1821 Platforms which normally make use of ROM-able zImage formats
1822 normally set this to a suitable value in their defconfig file.
1824 If ZBOOT_ROM is not enabled, this has no effect.
1827 bool "Compressed boot loader in ROM/flash"
1828 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1830 Say Y here if you intend to execute your compressed kernel image
1831 (zImage) directly from ROM or flash. If unsure, say N.
1834 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1835 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1836 default ZBOOT_ROM_NONE
1838 Include experimental SD/MMC loading code in the ROM-able zImage.
1839 With this enabled it is possible to write the the ROM-able zImage
1840 kernel image to an MMC or SD card and boot the kernel straight
1841 from the reset vector. At reset the processor Mask ROM will load
1842 the first part of the the ROM-able zImage which in turn loads the
1843 rest the kernel image to RAM.
1845 config ZBOOT_ROM_NONE
1846 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1848 Do not load image from SD or MMC
1850 config ZBOOT_ROM_MMCIF
1851 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1853 Load image from MMCIF hardware block.
1855 config ZBOOT_ROM_SH_MOBILE_SDHI
1856 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1858 Load image from SDHI hardware block
1862 config ARM_APPENDED_DTB
1863 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1864 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1866 With this option, the boot code will look for a device tree binary
1867 (DTB) appended to zImage
1868 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1870 This is meant as a backward compatibility convenience for those
1871 systems with a bootloader that can't be upgraded to accommodate
1872 the documented boot protocol using a device tree.
1874 Beware that there is very little in terms of protection against
1875 this option being confused by leftover garbage in memory that might
1876 look like a DTB header after a reboot if no actual DTB is appended
1877 to zImage. Do not leave this option active in a production kernel
1878 if you don't intend to always append a DTB. Proper passing of the
1879 location into r2 of a bootloader provided DTB is always preferable
1882 config ARM_ATAG_DTB_COMPAT
1883 bool "Supplement the appended DTB with traditional ATAG information"
1884 depends on ARM_APPENDED_DTB
1886 Some old bootloaders can't be updated to a DTB capable one, yet
1887 they provide ATAGs with memory configuration, the ramdisk address,
1888 the kernel cmdline string, etc. Such information is dynamically
1889 provided by the bootloader and can't always be stored in a static
1890 DTB. To allow a device tree enabled kernel to be used with such
1891 bootloaders, this option allows zImage to extract the information
1892 from the ATAG list and store it at run time into the appended DTB.
1895 string "Default kernel command string"
1898 On some architectures (EBSA110 and CATS), there is currently no way
1899 for the boot loader to pass arguments to the kernel. For these
1900 architectures, you should supply some command-line options at build
1901 time by entering them here. As a minimum, you should specify the
1902 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1905 prompt "Kernel command line type" if CMDLINE != ""
1906 default CMDLINE_FROM_BOOTLOADER
1908 config CMDLINE_FROM_BOOTLOADER
1909 bool "Use bootloader kernel arguments if available"
1911 Uses the command-line options passed by the boot loader. If
1912 the boot loader doesn't provide any, the default kernel command
1913 string provided in CMDLINE will be used.
1915 config CMDLINE_EXTEND
1916 bool "Extend bootloader kernel arguments"
1918 The command-line arguments provided by the boot loader will be
1919 appended to the default kernel command string.
1921 config CMDLINE_FORCE
1922 bool "Always use the default kernel command string"
1924 Always use the default kernel command string, even if the boot
1925 loader passes other arguments to the kernel.
1926 This is useful if you cannot or don't want to change the
1927 command-line options your boot loader passes to the kernel.
1931 bool "Kernel Execute-In-Place from ROM"
1932 depends on !ZBOOT_ROM
1934 Execute-In-Place allows the kernel to run from non-volatile storage
1935 directly addressable by the CPU, such as NOR flash. This saves RAM
1936 space since the text section of the kernel is not loaded from flash
1937 to RAM. Read-write sections, such as the data section and stack,
1938 are still copied to RAM. The XIP kernel is not compressed since
1939 it has to run directly from flash, so it will take more space to
1940 store it. The flash address used to link the kernel object files,
1941 and for storing it, is configuration dependent. Therefore, if you
1942 say Y here, you must know the proper physical address where to
1943 store the kernel image depending on your own flash memory usage.
1945 Also note that the make target becomes "make xipImage" rather than
1946 "make zImage" or "make Image". The final kernel binary to put in
1947 ROM memory will be arch/arm/boot/xipImage.
1951 config XIP_PHYS_ADDR
1952 hex "XIP Kernel Physical Location"
1953 depends on XIP_KERNEL
1954 default "0x00080000"
1956 This is the physical address in your flash memory the kernel will
1957 be linked for and stored to. This address is dependent on your
1961 bool "Kexec system call (EXPERIMENTAL)"
1962 depends on EXPERIMENTAL
1964 kexec is a system call that implements the ability to shutdown your
1965 current kernel, and to start another kernel. It is like a reboot
1966 but it is independent of the system firmware. And like a reboot
1967 you can start any kernel with it, not just Linux.
1969 It is an ongoing process to be certain the hardware in a machine
1970 is properly shutdown, so do not be surprised if this code does not
1971 initially work for you. It may help to enable device hotplugging
1975 bool "Export atags in procfs"
1979 Should the atags used to boot the kernel be exported in an "atags"
1980 file in procfs. Useful with kexec.
1983 bool "Build kdump crash kernel (EXPERIMENTAL)"
1984 depends on EXPERIMENTAL
1986 Generate crash dump after being started by kexec. This should
1987 be normally only set in special crash dump kernels which are
1988 loaded in the main kernel with kexec-tools into a specially
1989 reserved region and then later executed after a crash by
1990 kdump/kexec. The crash dump kernel must be compiled to a
1991 memory address not used by the main kernel
1993 For more details see Documentation/kdump/kdump.txt
1995 config AUTO_ZRELADDR
1996 bool "Auto calculation of the decompressed kernel image address"
1997 depends on !ZBOOT_ROM && !ARCH_U300
1999 ZRELADDR is the physical address where the decompressed kernel
2000 image will be placed. If AUTO_ZRELADDR is selected, the address
2001 will be determined at run-time by masking the current IP with
2002 0xf8000000. This assumes the zImage being placed in the first 128MB
2003 from start of memory.
2007 menu "CPU Power Management"
2011 source "drivers/cpufreq/Kconfig"
2014 tristate "CPUfreq driver for i.MX CPUs"
2015 depends on ARCH_MXC && CPU_FREQ
2017 This enables the CPUfreq driver for i.MX CPUs.
2019 config CPU_FREQ_SA1100
2022 config CPU_FREQ_SA1110
2025 config CPU_FREQ_INTEGRATOR
2026 tristate "CPUfreq driver for ARM Integrator CPUs"
2027 depends on ARCH_INTEGRATOR && CPU_FREQ
2030 This enables the CPUfreq driver for ARM Integrator CPUs.
2032 For details, take a look at <file:Documentation/cpu-freq>.
2038 depends on CPU_FREQ && ARCH_PXA && PXA25x
2040 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2045 Internal configuration node for common cpufreq on Samsung SoC
2047 config CPU_FREQ_S3C24XX
2048 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2049 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2052 This enables the CPUfreq driver for the Samsung S3C24XX family
2055 For details, take a look at <file:Documentation/cpu-freq>.
2059 config CPU_FREQ_S3C24XX_PLL
2060 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2061 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2063 Compile in support for changing the PLL frequency from the
2064 S3C24XX series CPUfreq driver. The PLL takes time to settle
2065 after a frequency change, so by default it is not enabled.
2067 This also means that the PLL tables for the selected CPU(s) will
2068 be built which may increase the size of the kernel image.
2070 config CPU_FREQ_S3C24XX_DEBUG
2071 bool "Debug CPUfreq Samsung driver core"
2072 depends on CPU_FREQ_S3C24XX
2074 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2076 config CPU_FREQ_S3C24XX_IODEBUG
2077 bool "Debug CPUfreq Samsung driver IO timing"
2078 depends on CPU_FREQ_S3C24XX
2080 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2082 config CPU_FREQ_S3C24XX_DEBUGFS
2083 bool "Export debugfs for CPUFreq"
2084 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2086 Export status information via debugfs.
2090 source "drivers/cpuidle/Kconfig"
2094 menu "Floating point emulation"
2096 comment "At least one emulation must be selected"
2099 bool "NWFPE math emulation"
2100 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2102 Say Y to include the NWFPE floating point emulator in the kernel.
2103 This is necessary to run most binaries. Linux does not currently
2104 support floating point hardware so you need to say Y here even if
2105 your machine has an FPA or floating point co-processor podule.
2107 You may say N here if you are going to load the Acorn FPEmulator
2108 early in the bootup.
2111 bool "Support extended precision"
2112 depends on FPE_NWFPE
2114 Say Y to include 80-bit support in the kernel floating-point
2115 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2116 Note that gcc does not generate 80-bit operations by default,
2117 so in most cases this option only enlarges the size of the
2118 floating point emulator without any good reason.
2120 You almost surely want to say N here.
2123 bool "FastFPE math emulation (EXPERIMENTAL)"
2124 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2126 Say Y here to include the FAST floating point emulator in the kernel.
2127 This is an experimental much faster emulator which now also has full
2128 precision for the mantissa. It does not support any exceptions.
2129 It is very simple, and approximately 3-6 times faster than NWFPE.
2131 It should be sufficient for most programs. It may be not suitable
2132 for scientific calculations, but you have to check this for yourself.
2133 If you do not feel you need a faster FP emulation you should better
2137 bool "VFP-format floating point maths"
2138 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2140 Say Y to include VFP support code in the kernel. This is needed
2141 if your hardware includes a VFP unit.
2143 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2144 release notes and additional status information.
2146 Say N if your target does not have VFP hardware.
2154 bool "Advanced SIMD (NEON) Extension support"
2155 depends on VFPv3 && CPU_V7
2157 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2162 menu "Userspace binary formats"
2164 source "fs/Kconfig.binfmt"
2167 tristate "RISC OS personality"
2170 Say Y here to include the kernel code necessary if you want to run
2171 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2172 experimental; if this sounds frightening, say N and sleep in peace.
2173 You can also say M here to compile this support as a module (which
2174 will be called arthur).
2178 menu "Power management options"
2180 source "kernel/power/Kconfig"
2182 config ARCH_SUSPEND_POSSIBLE
2183 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2184 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2185 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2190 source "net/Kconfig"
2192 source "drivers/Kconfig"
2196 source "arch/arm/Kconfig.debug"
2198 source "security/Kconfig"
2200 source "crypto/Kconfig"
2202 source "lib/Kconfig"