2 * linux/arch/alpha/kernel/sys_titan.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 * Copyright (C) 1999, 2000 Jeff Wiedemeier
9 * Code supporting TITAN systems (EV6+TITAN), currently:
15 #include <linux/config.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
19 #include <linux/sched.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/bitops.h>
24 #include <asm/ptrace.h>
25 #include <asm/system.h>
28 #include <asm/mmu_context.h>
30 #include <asm/pgtable.h>
31 #include <asm/core_titan.h>
32 #include <asm/hwrpb.h>
33 #include <asm/tlbflush.h>
38 #include "machvec_impl.h"
47 * Titan supports up to 4 CPUs
49 static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
52 * Mask is set (1) if enabled
54 static unsigned long titan_cached_irq_mask;
57 * Need SMP-safe access to interrupt CSRs
59 DEFINE_SPINLOCK(titan_irq_lock);
62 titan_update_irq_hw(unsigned long mask)
64 register titan_cchip *cchip = TITAN_cchip;
65 unsigned long isa_enable = 1UL << 55;
66 register int bcpu = boot_cpuid;
69 cpumask_t cpm = cpu_present_map;
70 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
71 unsigned long mask0, mask1, mask2, mask3, dummy;
74 mask0 = mask & titan_cpu_irq_affinity[0];
75 mask1 = mask & titan_cpu_irq_affinity[1];
76 mask2 = mask & titan_cpu_irq_affinity[2];
77 mask3 = mask & titan_cpu_irq_affinity[3];
79 if (bcpu == 0) mask0 |= isa_enable;
80 else if (bcpu == 1) mask1 |= isa_enable;
81 else if (bcpu == 2) mask2 |= isa_enable;
82 else mask3 |= isa_enable;
84 dim0 = &cchip->dim0.csr;
85 dim1 = &cchip->dim1.csr;
86 dim2 = &cchip->dim2.csr;
87 dim3 = &cchip->dim3.csr;
88 if (!cpu_isset(0, cpm)) dim0 = &dummy;
89 if (!cpu_isset(1, cpm)) dim1 = &dummy;
90 if (!cpu_isset(2, cpm)) dim2 = &dummy;
91 if (!cpu_isset(3, cpm)) dim3 = &dummy;
103 volatile unsigned long *dimB;
104 dimB = &cchip->dim0.csr;
105 if (bcpu == 1) dimB = &cchip->dim1.csr;
106 else if (bcpu == 2) dimB = &cchip->dim2.csr;
107 else if (bcpu == 3) dimB = &cchip->dim3.csr;
109 *dimB = mask | isa_enable;
116 titan_enable_irq(unsigned int irq)
118 spin_lock(&titan_irq_lock);
119 titan_cached_irq_mask |= 1UL << (irq - 16);
120 titan_update_irq_hw(titan_cached_irq_mask);
121 spin_unlock(&titan_irq_lock);
125 titan_disable_irq(unsigned int irq)
127 spin_lock(&titan_irq_lock);
128 titan_cached_irq_mask &= ~(1UL << (irq - 16));
129 titan_update_irq_hw(titan_cached_irq_mask);
130 spin_unlock(&titan_irq_lock);
134 titan_startup_irq(unsigned int irq)
136 titan_enable_irq(irq);
137 return 0; /* never anything pending */
141 titan_end_irq(unsigned int irq)
143 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
144 titan_enable_irq(irq);
148 titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
152 for (cpu = 0; cpu < 4; cpu++) {
153 if (cpu_isset(cpu, affinity))
154 titan_cpu_irq_affinity[cpu] |= 1UL << irq;
156 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
162 titan_set_irq_affinity(unsigned int irq, cpumask_t affinity)
164 spin_lock(&titan_irq_lock);
165 titan_cpu_set_irq_affinity(irq - 16, affinity);
166 titan_update_irq_hw(titan_cached_irq_mask);
167 spin_unlock(&titan_irq_lock);
171 titan_device_interrupt(unsigned long vector, struct pt_regs * regs)
173 printk("titan_device_interrupt: NOT IMPLEMENTED YET!! \n");
177 titan_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
181 irq = (vector - 0x800) >> 4;
182 handle_irq(irq, regs);
187 init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax)
190 for (i = imin; i <= imax; ++i) {
191 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
192 irq_desc[i].handler = ops;
196 static struct hw_interrupt_type titan_irq_type = {
198 .startup = titan_startup_irq,
199 .shutdown = titan_disable_irq,
200 .enable = titan_enable_irq,
201 .disable = titan_disable_irq,
202 .ack = titan_disable_irq,
203 .end = titan_end_irq,
204 .set_affinity = titan_set_irq_affinity,
208 titan_intr_nop(int irq, void *dev_id, struct pt_regs *regs)
211 * This is a NOP interrupt handler for the purposes of
212 * event counting -- just return.
220 if (alpha_using_srm && !alpha_mv.device_interrupt)
221 alpha_mv.device_interrupt = titan_srm_device_interrupt;
222 if (!alpha_mv.device_interrupt)
223 alpha_mv.device_interrupt = titan_device_interrupt;
225 titan_update_irq_hw(0);
227 init_titan_irqs(&titan_irq_type, 16, 63 + 16);
231 titan_legacy_init_irq(void)
233 /* init the legacy dma controller */
234 outb(0, DMA1_RESET_REG);
235 outb(0, DMA2_RESET_REG);
236 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
237 outb(0, DMA2_MASK_REG);
239 /* init the legacy irq controller */
242 /* init the titan irqs */
247 titan_dispatch_irqs(u64 mask, struct pt_regs *regs)
249 unsigned long vector;
252 * Mask down to those interrupts which are enable on this processor
254 mask &= titan_cpu_irq_affinity[smp_processor_id()];
257 * Dispatch all requested interrupts
260 /* convert to SRM vector... priority is <63> -> <0> */
261 __asm__("ctlz %1, %0" : "=r"(vector) : "r"(mask));
262 vector = 63 - vector;
263 mask &= ~(1UL << vector); /* clear it out */
264 vector = 0x900 + (vector << 4); /* convert to SRM vector */
267 alpha_mv.device_interrupt(vector, regs);
276 titan_late_init(void)
279 * Enable the system error interrupts. These interrupts are
280 * all reported to the kernel as machine checks, so the handler
281 * is a nop so it can be called to count the individual events.
283 request_irq(63+16, titan_intr_nop, SA_INTERRUPT,
284 "CChip Error", NULL);
285 request_irq(62+16, titan_intr_nop, SA_INTERRUPT,
286 "PChip 0 H_Error", NULL);
287 request_irq(61+16, titan_intr_nop, SA_INTERRUPT,
288 "PChip 1 H_Error", NULL);
289 request_irq(60+16, titan_intr_nop, SA_INTERRUPT,
290 "PChip 0 C_Error", NULL);
291 request_irq(59+16, titan_intr_nop, SA_INTERRUPT,
292 "PChip 1 C_Error", NULL);
295 * Register our error handlers.
297 titan_register_error_handlers();
300 * Check if the console left us any error logs.
302 cdl_check_console_data_log();
307 titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
312 /* Get the current intline. */
313 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
316 /* Is it explicitly routed through ISA? */
317 if ((irq & 0xF0) == 0xE0)
320 /* Offset by 16 to make room for ISA interrupts 0 - 15. */
328 * This isn't really the right place, but there's some init
329 * that needs to be done after everything is basically up.
336 #ifdef CONFIG_VGA_HOSE
337 locate_and_init_vga(NULL);
346 privateer_init_pci(void)
349 * Hook a couple of extra err interrupts that the
350 * common titan code won't.
352 request_irq(53+16, titan_intr_nop, SA_INTERRUPT,
354 request_irq(50+16, titan_intr_nop, SA_INTERRUPT,
355 "Temperature Warning", NULL);
358 * Finish with the common version.
360 return titan_init_pci();
365 * The System Vectors.
367 struct alpha_machine_vector titan_mv __initmv = {
368 .vector_name = "TITAN",
372 .machine_check = titan_machine_check,
373 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
374 .min_io_address = DEFAULT_IO_BASE,
375 .min_mem_address = DEFAULT_MEM_BASE,
376 .pci_dac_offset = TITAN_DAC_OFFSET,
378 .nr_irqs = 80, /* 64 + 16 */
379 /* device_interrupt will be filled in by titan_init_irq */
381 .agp_info = titan_agp_info,
383 .init_arch = titan_init_arch,
384 .init_irq = titan_legacy_init_irq,
385 .init_rtc = common_init_rtc,
386 .init_pci = titan_init_pci,
388 .kill_arch = titan_kill_arch,
389 .pci_map_irq = titan_map_irq,
390 .pci_swizzle = common_swizzle,
394 struct alpha_machine_vector privateer_mv __initmv = {
395 .vector_name = "PRIVATEER",
399 .machine_check = privateer_machine_check,
400 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
401 .min_io_address = DEFAULT_IO_BASE,
402 .min_mem_address = DEFAULT_MEM_BASE,
403 .pci_dac_offset = TITAN_DAC_OFFSET,
405 .nr_irqs = 80, /* 64 + 16 */
406 /* device_interrupt will be filled in by titan_init_irq */
408 .agp_info = titan_agp_info,
410 .init_arch = titan_init_arch,
411 .init_irq = titan_legacy_init_irq,
412 .init_rtc = common_init_rtc,
413 .init_pci = privateer_init_pci,
415 .kill_arch = titan_kill_arch,
416 .pci_map_irq = titan_map_irq,
417 .pci_swizzle = common_swizzle,
419 /* No alpha_mv alias for privateer since we compile it
420 in unconditionally with titan; setup_arch knows how to cope. */