2 * linux/arch/alpha/kernel/sys_mikasa.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
8 * Code supporting the MIKASA (AlphaServer 1000).
11 #include <linux/kernel.h>
12 #include <linux/types.h>
14 #include <linux/sched.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/bitops.h>
19 #include <asm/ptrace.h>
20 #include <asm/system.h>
23 #include <asm/mmu_context.h>
25 #include <asm/pgtable.h>
26 #include <asm/core_apecs.h>
27 #include <asm/core_cia.h>
28 #include <asm/tlbflush.h>
33 #include "machvec_impl.h"
36 /* Note mask bit is true for ENABLED irqs. */
37 static int cached_irq_mask;
40 mikasa_update_irq_hw(int mask)
46 mikasa_enable_irq(unsigned int irq)
48 mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
52 mikasa_disable_irq(unsigned int irq)
54 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
57 static struct irq_chip mikasa_irq_type = {
59 .unmask = mikasa_enable_irq,
60 .mask = mikasa_disable_irq,
61 .mask_ack = mikasa_disable_irq,
65 mikasa_device_interrupt(unsigned long vector)
70 /* Read the interrupt summary registers */
71 pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
72 | (((unsigned long) inb(0xa0)) << 8)
76 * Now for every possible bit set, work through them and call
77 * the appropriate interrupt handler.
81 pld &= pld - 1; /* clear least bit set */
83 isa_device_interrupt(vector);
96 alpha_mv.device_interrupt = srm_device_interrupt;
98 mikasa_update_irq_hw(0);
100 for (i = 16; i < 32; ++i) {
101 irq_to_desc(i)->status |= IRQ_LEVEL;
102 set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
106 common_init_isa_dma();
111 * PCI Fixup configuration.
115 * 0 Interrupt Line A from slot 0
116 * 1 Interrupt Line B from slot 0
117 * 2 Interrupt Line C from slot 0
118 * 3 Interrupt Line D from slot 0
119 * 4 Interrupt Line A from slot 1
120 * 5 Interrupt line B from slot 1
121 * 6 Interrupt Line C from slot 1
122 * 7 Interrupt Line D from slot 1
123 * 8 Interrupt Line A from slot 2
124 * 9 Interrupt Line B from slot 2
125 *10 Interrupt Line C from slot 2
126 *11 Interrupt Line D from slot 2
128 *13 Power Supply Fail
132 * The device to slot mapping looks like:
135 * 6 NCR SCSI controller
136 * 7 Intel PCI-EISA bridge chip
137 * 11 PCI on board slot 0
138 * 12 PCI on board slot 1
139 * 13 PCI on board slot 2
142 * This two layered interrupt approach means that we allocate IRQ 16 and
143 * above for PCI interrupts. The IRQ relates to which bit the interrupt
144 * comes in on. This makes interrupt processing much easier.
148 mikasa_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
150 static char irq_tab[8][5] __initdata = {
151 /*INT INTA INTB INTC INTD */
152 {16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 17, SCSI */
153 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
154 { -1, -1, -1, -1, -1}, /* IdSel 19, ???? */
155 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
156 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
157 { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */
158 { 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
159 { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */
161 const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
162 return COMMON_TABLE_LOOKUP;
166 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
168 mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
170 #define MCHK_NO_DEVSEL 0x205U
171 #define MCHK_NO_TABT 0x204U
173 struct el_common *mchk_header;
176 mchk_header = (struct el_common *)la_ptr;
178 /* Clear the error before any reporting. */
186 code = mchk_header->code;
187 process_mcheck_info(vector, la_ptr, "MIKASA APECS",
189 && (code == MCHK_NO_DEVSEL
190 || code == MCHK_NO_TABT)));
199 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
200 struct alpha_machine_vector mikasa_mv __initmv = {
201 .vector_name = "Mikasa",
205 .machine_check = mikasa_apecs_machine_check,
206 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
207 .min_io_address = DEFAULT_IO_BASE,
208 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
211 .device_interrupt = mikasa_device_interrupt,
213 .init_arch = apecs_init_arch,
214 .init_irq = mikasa_init_irq,
215 .init_rtc = common_init_rtc,
216 .init_pci = common_init_pci,
217 .pci_map_irq = mikasa_map_irq,
218 .pci_swizzle = common_swizzle,
223 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
224 struct alpha_machine_vector mikasa_primo_mv __initmv = {
225 .vector_name = "Mikasa-Primo",
229 .machine_check = cia_machine_check,
230 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
231 .min_io_address = DEFAULT_IO_BASE,
232 .min_mem_address = CIA_DEFAULT_MEM_BASE,
235 .device_interrupt = mikasa_device_interrupt,
237 .init_arch = cia_init_arch,
238 .init_irq = mikasa_init_irq,
239 .init_rtc = common_init_rtc,
240 .init_pci = cia_init_pci,
241 .kill_arch = cia_kill_arch,
242 .pci_map_irq = mikasa_map_irq,
243 .pci_swizzle = common_swizzle,
245 ALIAS_MV(mikasa_primo)