2 * linux/arch/alpha/kernel/sys_dp264.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
8 * Modified by Christopher C. Chimelis, 2001 to
9 * add support for the addition of Shark to the
12 * Code supporting the DP264 (EV6+TSUNAMI).
15 #include <linux/kernel.h>
16 #include <linux/types.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/bitops.h>
23 #include <asm/ptrace.h>
24 #include <asm/system.h>
27 #include <asm/mmu_context.h>
29 #include <asm/pgtable.h>
30 #include <asm/core_tsunami.h>
31 #include <asm/hwrpb.h>
32 #include <asm/tlbflush.h>
37 #include "machvec_impl.h"
40 /* Note mask bit is true for ENABLED irqs. */
41 static unsigned long cached_irq_mask;
42 /* dp264 boards handle at max four CPUs */
43 static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
45 DEFINE_SPINLOCK(dp264_irq_lock);
48 tsunami_update_irq_hw(unsigned long mask)
50 register tsunami_cchip *cchip = TSUNAMI_cchip;
51 unsigned long isa_enable = 1UL << 55;
52 register int bcpu = boot_cpuid;
55 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
56 unsigned long mask0, mask1, mask2, mask3, dummy;
59 mask0 = mask & cpu_irq_affinity[0];
60 mask1 = mask & cpu_irq_affinity[1];
61 mask2 = mask & cpu_irq_affinity[2];
62 mask3 = mask & cpu_irq_affinity[3];
64 if (bcpu == 0) mask0 |= isa_enable;
65 else if (bcpu == 1) mask1 |= isa_enable;
66 else if (bcpu == 2) mask2 |= isa_enable;
67 else mask3 |= isa_enable;
69 dim0 = &cchip->dim0.csr;
70 dim1 = &cchip->dim1.csr;
71 dim2 = &cchip->dim2.csr;
72 dim3 = &cchip->dim3.csr;
73 if (!cpu_possible(0)) dim0 = &dummy;
74 if (!cpu_possible(1)) dim1 = &dummy;
75 if (!cpu_possible(2)) dim2 = &dummy;
76 if (!cpu_possible(3)) dim3 = &dummy;
88 volatile unsigned long *dimB;
89 if (bcpu == 0) dimB = &cchip->dim0.csr;
90 else if (bcpu == 1) dimB = &cchip->dim1.csr;
91 else if (bcpu == 2) dimB = &cchip->dim2.csr;
92 else dimB = &cchip->dim3.csr;
94 *dimB = mask | isa_enable;
101 dp264_enable_irq(unsigned int irq)
103 spin_lock(&dp264_irq_lock);
104 cached_irq_mask |= 1UL << irq;
105 tsunami_update_irq_hw(cached_irq_mask);
106 spin_unlock(&dp264_irq_lock);
110 dp264_disable_irq(unsigned int irq)
112 spin_lock(&dp264_irq_lock);
113 cached_irq_mask &= ~(1UL << irq);
114 tsunami_update_irq_hw(cached_irq_mask);
115 spin_unlock(&dp264_irq_lock);
119 clipper_enable_irq(unsigned int irq)
121 spin_lock(&dp264_irq_lock);
122 cached_irq_mask |= 1UL << (irq - 16);
123 tsunami_update_irq_hw(cached_irq_mask);
124 spin_unlock(&dp264_irq_lock);
128 clipper_disable_irq(unsigned int irq)
130 spin_lock(&dp264_irq_lock);
131 cached_irq_mask &= ~(1UL << (irq - 16));
132 tsunami_update_irq_hw(cached_irq_mask);
133 spin_unlock(&dp264_irq_lock);
137 cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
141 for (cpu = 0; cpu < 4; cpu++) {
142 unsigned long aff = cpu_irq_affinity[cpu];
143 if (cpu_isset(cpu, affinity))
146 aff &= ~(1UL << irq);
147 cpu_irq_affinity[cpu] = aff;
152 dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
154 spin_lock(&dp264_irq_lock);
155 cpu_set_irq_affinity(irq, *affinity);
156 tsunami_update_irq_hw(cached_irq_mask);
157 spin_unlock(&dp264_irq_lock);
163 clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
165 spin_lock(&dp264_irq_lock);
166 cpu_set_irq_affinity(irq - 16, *affinity);
167 tsunami_update_irq_hw(cached_irq_mask);
168 spin_unlock(&dp264_irq_lock);
173 static struct irq_chip dp264_irq_type = {
175 .unmask = dp264_enable_irq,
176 .mask = dp264_disable_irq,
177 .mask_ack = dp264_disable_irq,
178 .set_affinity = dp264_set_affinity,
181 static struct irq_chip clipper_irq_type = {
183 .unmask = clipper_enable_irq,
184 .mask = clipper_disable_irq,
185 .mask_ack = clipper_disable_irq,
186 .set_affinity = clipper_set_affinity,
190 dp264_device_interrupt(unsigned long vector)
193 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n");
198 /* Read the interrupt summary register of TSUNAMI */
199 pld = TSUNAMI_cchip->dir0.csr;
202 * Now for every possible bit set, work through them and call
203 * the appropriate interrupt handler.
207 pld &= pld - 1; /* clear least bit set */
209 isa_device_interrupt(vector);
213 TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
214 tmp = TSUNAMI_cchip->dir0.csr;
221 dp264_srm_device_interrupt(unsigned long vector)
225 irq = (vector - 0x800) >> 4;
228 * The SRM console reports PCI interrupts with a vector calculated by:
230 * 0x900 + (0x10 * DRIR-bit)
232 * So bit 16 shows up as IRQ 32, etc.
234 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
235 * that many of the low order bits of the DRIR are not used, and
236 * so we don't count them.
245 clipper_srm_device_interrupt(unsigned long vector)
249 irq = (vector - 0x800) >> 4;
252 * The SRM console reports PCI interrupts with a vector calculated by:
254 * 0x900 + (0x10 * DRIR-bit)
256 * So bit 16 shows up as IRQ 32, etc.
258 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
259 * to scale down the vector reported, we just use it.
261 * Eg IRQ 24 is DRIR bit 8, etc, etc
267 init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
270 for (i = imin; i <= imax; ++i) {
271 irq_to_desc(i)->status |= IRQ_LEVEL;
272 set_irq_chip_and_handler(i, ops, handle_level_irq);
279 outb(0, DMA1_RESET_REG);
280 outb(0, DMA2_RESET_REG);
281 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
282 outb(0, DMA2_MASK_REG);
285 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
287 tsunami_update_irq_hw(0);
290 init_tsunami_irqs(&dp264_irq_type, 16, 47);
294 clipper_init_irq(void)
296 outb(0, DMA1_RESET_REG);
297 outb(0, DMA2_RESET_REG);
298 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
299 outb(0, DMA2_MASK_REG);
302 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
304 tsunami_update_irq_hw(0);
307 init_tsunami_irqs(&clipper_irq_type, 24, 63);
312 * PCI Fixup configuration.
314 * Summary @ TSUNAMI_CSR_DIM0:
317 *18 Interrupt SCSI B (Adaptec 7895 builtin)
318 *19 Interrupt SCSI A (Adaptec 7895 builtin)
319 *20 Interrupt Line D from slot 2 PCI0
320 *21 Interrupt Line C from slot 2 PCI0
321 *22 Interrupt Line B from slot 2 PCI0
322 *23 Interrupt Line A from slot 2 PCI0
323 *24 Interrupt Line D from slot 1 PCI0
324 *25 Interrupt Line C from slot 1 PCI0
325 *26 Interrupt Line B from slot 1 PCI0
326 *27 Interrupt Line A from slot 1 PCI0
327 *28 Interrupt Line D from slot 0 PCI0
328 *29 Interrupt Line C from slot 0 PCI0
329 *30 Interrupt Line B from slot 0 PCI0
330 *31 Interrupt Line A from slot 0 PCI0
332 *32 Interrupt Line D from slot 3 PCI1
333 *33 Interrupt Line C from slot 3 PCI1
334 *34 Interrupt Line B from slot 3 PCI1
335 *35 Interrupt Line A from slot 3 PCI1
336 *36 Interrupt Line D from slot 2 PCI1
337 *37 Interrupt Line C from slot 2 PCI1
338 *38 Interrupt Line B from slot 2 PCI1
339 *39 Interrupt Line A from slot 2 PCI1
340 *40 Interrupt Line D from slot 1 PCI1
341 *41 Interrupt Line C from slot 1 PCI1
342 *42 Interrupt Line B from slot 1 PCI1
343 *43 Interrupt Line A from slot 1 PCI1
344 *44 Interrupt Line D from slot 0 PCI1
345 *45 Interrupt Line C from slot 0 PCI1
346 *46 Interrupt Line B from slot 0 PCI1
347 *47 Interrupt Line A from slot 0 PCI1
349 *53 PCI0 NMI (from Cypress)
350 *54 PCI0 SMI INT (from Cypress)
351 *55 PCI0 ISA Interrupt (from Cypress)
358 * 5 Cypress Bridge I/O
359 * 6 SCSI Adaptec builtin
360 * 7 64 bit PCI option slot 0 (all busses)
361 * 8 64 bit PCI option slot 1 (all busses)
362 * 9 64 bit PCI option slot 2 (all busses)
363 * 10 64 bit PCI option slot 3 (not bus 0)
367 isa_irq_fixup(struct pci_dev *dev, int irq)
374 /* This interrupt is routed via ISA bridge, so we'll
375 just have to trust whatever value the console might
377 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
383 dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
385 static char irq_tab[6][5] __initdata = {
386 /*INT INTA INTB INTC INTD */
387 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
388 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
389 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
390 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
391 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
392 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
394 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
395 struct pci_controller *hose = dev->sysdata;
396 int irq = COMMON_TABLE_LOOKUP;
399 irq += 16 * hose->index;
401 return isa_irq_fixup(dev, irq);
405 monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
407 static char irq_tab[13][5] __initdata = {
408 /*INT INTA INTB INTC INTD */
409 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
410 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
411 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
412 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
413 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
414 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
416 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
417 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
419 { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
420 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
422 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
423 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
424 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
425 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
426 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
428 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
430 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
434 monet_swizzle(struct pci_dev *dev, u8 *pinp)
436 struct pci_controller *hose = dev->sysdata;
437 int slot, pin = *pinp;
439 if (!dev->bus->parent) {
440 slot = PCI_SLOT(dev->devfn);
442 /* Check for the built-in bridge on hose 1. */
443 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
444 slot = PCI_SLOT(dev->devfn);
446 /* Must be a card-based bridge. */
448 /* Check for built-in bridge on hose 1. */
449 if (hose->index == 1 &&
450 PCI_SLOT(dev->bus->self->devfn) == 8) {
451 slot = PCI_SLOT(dev->devfn);
454 pin = pci_swizzle_interrupt_pin(dev, pin);
456 /* Move up the chain of bridges. */
457 dev = dev->bus->self;
458 /* Slot of the next bridge. */
459 slot = PCI_SLOT(dev->devfn);
460 } while (dev->bus->self);
467 webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
469 static char irq_tab[13][5] __initdata = {
470 /*INT INTA INTB INTC INTD */
471 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
472 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
473 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
474 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
475 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
476 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
477 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
478 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
479 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
480 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
481 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
483 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
485 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
489 clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
491 static char irq_tab[7][5] __initdata = {
492 /*INT INTA INTB INTC INTD */
493 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
494 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
495 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
496 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
497 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
498 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
499 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
501 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
502 struct pci_controller *hose = dev->sysdata;
503 int irq = COMMON_TABLE_LOOKUP;
506 irq += 16 * hose->index;
508 return isa_irq_fixup(dev, irq);
516 locate_and_init_vga(NULL);
525 locate_and_init_vga(NULL);
529 clipper_init_pci(void)
532 locate_and_init_vga(NULL);
536 webbrick_init_arch(void)
540 /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
541 hose_head->sg_isa->align_entry = 4;
542 hose_head->sg_pci->align_entry = 4;
550 struct alpha_machine_vector dp264_mv __initmv = {
551 .vector_name = "DP264",
555 .machine_check = tsunami_machine_check,
556 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
557 .min_io_address = DEFAULT_IO_BASE,
558 .min_mem_address = DEFAULT_MEM_BASE,
559 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
562 .device_interrupt = dp264_device_interrupt,
564 .init_arch = tsunami_init_arch,
565 .init_irq = dp264_init_irq,
566 .init_rtc = common_init_rtc,
567 .init_pci = dp264_init_pci,
568 .kill_arch = tsunami_kill_arch,
569 .pci_map_irq = dp264_map_irq,
570 .pci_swizzle = common_swizzle,
574 struct alpha_machine_vector monet_mv __initmv = {
575 .vector_name = "Monet",
579 .machine_check = tsunami_machine_check,
580 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
581 .min_io_address = DEFAULT_IO_BASE,
582 .min_mem_address = DEFAULT_MEM_BASE,
583 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
586 .device_interrupt = dp264_device_interrupt,
588 .init_arch = tsunami_init_arch,
589 .init_irq = dp264_init_irq,
590 .init_rtc = common_init_rtc,
591 .init_pci = monet_init_pci,
592 .kill_arch = tsunami_kill_arch,
593 .pci_map_irq = monet_map_irq,
594 .pci_swizzle = monet_swizzle,
597 struct alpha_machine_vector webbrick_mv __initmv = {
598 .vector_name = "Webbrick",
602 .machine_check = tsunami_machine_check,
603 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
604 .min_io_address = DEFAULT_IO_BASE,
605 .min_mem_address = DEFAULT_MEM_BASE,
606 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
609 .device_interrupt = dp264_device_interrupt,
611 .init_arch = webbrick_init_arch,
612 .init_irq = dp264_init_irq,
613 .init_rtc = common_init_rtc,
614 .init_pci = common_init_pci,
615 .kill_arch = tsunami_kill_arch,
616 .pci_map_irq = webbrick_map_irq,
617 .pci_swizzle = common_swizzle,
620 struct alpha_machine_vector clipper_mv __initmv = {
621 .vector_name = "Clipper",
625 .machine_check = tsunami_machine_check,
626 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
627 .min_io_address = DEFAULT_IO_BASE,
628 .min_mem_address = DEFAULT_MEM_BASE,
629 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
632 .device_interrupt = dp264_device_interrupt,
634 .init_arch = tsunami_init_arch,
635 .init_irq = clipper_init_irq,
636 .init_rtc = common_init_rtc,
637 .init_pci = clipper_init_pci,
638 .kill_arch = tsunami_kill_arch,
639 .pci_map_irq = clipper_map_irq,
640 .pci_swizzle = common_swizzle,
643 /* Sharks strongly resemble Clipper, at least as far
644 * as interrupt routing, etc, so we're using the
645 * same functions as Clipper does
648 struct alpha_machine_vector shark_mv __initmv = {
649 .vector_name = "Shark",
653 .machine_check = tsunami_machine_check,
654 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
655 .min_io_address = DEFAULT_IO_BASE,
656 .min_mem_address = DEFAULT_MEM_BASE,
657 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
660 .device_interrupt = dp264_device_interrupt,
662 .init_arch = tsunami_init_arch,
663 .init_irq = clipper_init_irq,
664 .init_rtc = common_init_rtc,
665 .init_pci = common_init_pci,
666 .kill_arch = tsunami_kill_arch,
667 .pci_map_irq = clipper_map_irq,
668 .pci_swizzle = common_swizzle,
671 /* No alpha_mv alias for webbrick/monet/clipper, since we compile them
672 in unconditionally with DP264; setup_arch knows how to cope. */