5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
56 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
60 bool "ARM architecture"
61 select ARCH_SUPPORTS_LTO
62 select CREATE_ARCH_SYMLINK
63 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select USE_PRIVATE_LIBGCC
71 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
73 select SYS_CACHE_SHIFT_4
74 select SUPPORT_OF_CONTROL
77 bool "MicroBlaze architecture"
78 select SUPPORT_OF_CONTROL
80 imply SPL_REGMAP if SPL
81 imply SPL_TIMER if SPL
86 bool "MIPS architecture"
87 select HAVE_ARCH_IOREMAP
88 select HAVE_PRIVATE_LIBGCC
89 select SUPPORT_OF_CONTROL
90 select SPL_SEPARATE_BSS if SPL
93 bool "Nios II architecture"
98 select SUPPORT_OF_CONTROL
102 bool "PowerPC architecture"
103 select HAVE_PRIVATE_LIBGCC
104 select SUPPORT_OF_CONTROL
105 select SYS_BOOT_GET_CMDLINE
106 select SYS_BOOT_GET_KBD
109 bool "RISC-V architecture"
110 select CREATE_ARCH_SYMLINK
112 select SUPPORT_OF_CONTROL
116 imply SPL_SEPARATE_BSS if SPL
128 imply SPL_LIBCOMMON_SUPPORT
129 imply SPL_LIBGENERIC_SUPPORT
135 select ARCH_SUPPORTS_LTO
136 select BOARD_LATE_INIT
138 select CMD_POWEROFF if CMDLINE
141 select DM_FUZZING_ENGINE
149 select GZIP_COMPRESSED
153 select OF_BOARD_SETUP
156 select SUPPORT_OF_CONTROL
157 select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
158 select SYS_CACHE_SHIFT_4
160 select SUPPORT_EXTENSION_SCAN if CMDLINE
177 imply FUZZING_ENGINE_SANDBOX
184 imply PARTITION_TYPE_GUID
187 imply UDP_FUNCTION_FASTBOOT
201 imply ACPI_PMC_SANDBOX
211 imply GENERATE_ACPI_TABLE
215 imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
216 imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
217 imply CMD_SYSBOOT if BOOTSTD_FULL
220 bool "SuperH architecture"
221 select HAVE_PRIVATE_LIBGCC
222 select SUPPORT_OF_CONTROL
225 bool "x86 architecture"
228 select CREATE_ARCH_SYMLINK
230 select HAVE_ARCH_IOMAP
231 select HAVE_PRIVATE_LIBGCC
235 select SUPPORT_OF_CONTROL
236 select SYS_CACHE_SHIFT_6
238 select USE_PRIVATE_LIBGCC
241 imply HAS_ROM if X86_RESET_VECTOR
244 imply CMD_FPGA_LOADMK
262 imply LAST_STAGE_INIT
268 imply USB_ETHER_SMSC95XX
274 imply ACPIGEN if !QEMU && !EFI_APP
275 imply SYSINFO if GENERATE_SMBIOS_TABLE
276 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
279 # Thing to enable for when SPL/TPL are enabled: SPL
282 imply SPL_DRIVERS_MISC
285 imply SPL_LIBCOMMON_SUPPORT
286 imply SPL_LIBGENERIC_SUPPORT
288 imply SPL_SPI_FLASH_SUPPORT
296 imply TPL_DRIVERS_MISC
299 imply TPL_LIBCOMMON_SUPPORT
300 imply TPL_LIBGENERIC_SUPPORT
308 bool "Xtensa architecture"
309 select CREATE_ARCH_SYMLINK
310 select SUPPORT_OF_CONTROL
317 This option should contain the architecture name to build the
318 appropriate arch/<CONFIG_SYS_ARCH> directory.
319 All the architectures should specify this option correctly.
324 This option should contain the CPU name to build the correct
325 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
327 This is optional. For those targets without the CPU directory,
328 leave this option empty.
333 This option should contain the SoC name to build the directory
334 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
336 This is optional. For those targets without the SoC directory,
337 leave this option empty.
342 This option should contain the vendor name of the target board.
344 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
345 directory is compiled.
346 If CONFIG_SYS_BOARD is also set, the sources under
347 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
349 This is optional. For those targets without the vendor directory,
350 leave this option empty.
355 This option should contain the name of the target board.
356 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
357 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
358 whether CONFIG_SYS_VENDOR is set or not.
360 This is optional. For those targets without the board directory,
361 leave this option empty.
363 config SYS_CONFIG_NAME
366 This option should contain the base name of board header file.
367 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
368 should be included from include/config.h.
370 config SYS_DISABLE_DCACHE_OPS
373 This option disables dcache flush and dcache invalidation
374 operations. For example, on coherent systems where cache
375 operatios are not required, enable this option to avoid them.
376 Note that, its up to the individual architectures to implement
380 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
381 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
382 default 0xFF000000 if MPC8xx
383 default 0xF0000000 if ARCH_MPC8313
384 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
385 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
386 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
387 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
389 default SYS_CCSRBAR_DEFAULT
391 Address for the Internal Memory-Mapped Registers (IMMR) window used
392 to configure the features of many Freescale / NXP SoCs.
394 config MONITOR_IS_IN_RAM
395 bool "U-Boot is loaded in to RAM by a pre-loader"
396 depends on M68K || NIOS2
398 menu "Skipping low level initialization functions"
399 depends on ARM || MIPS || RISCV
401 config SKIP_LOWLEVEL_INIT
402 bool "Skip calls to certain low level initialization functions"
404 If enabled, then certain low level initializations (like setting up
405 the memory controller) are omitted and/or U-Boot does not relocate
407 Normally this variable MUST NOT be defined. The only exception is
408 when U-Boot is loaded (to RAM) by some other boot loader or by a
409 debugger which performs these initializations itself.
411 config SPL_SKIP_LOWLEVEL_INIT
412 bool "Skip calls to certain low level initialization functions in SPL"
415 If enabled, then certain low level initializations (like setting up
416 the memory controller) are omitted and/or U-Boot does not relocate
418 Normally this variable MUST NOT be defined. The only exception is
419 when U-Boot is loaded (to RAM) by some other boot loader or by a
420 debugger which performs these initializations itself.
422 config TPL_SKIP_LOWLEVEL_INIT
423 bool "Skip calls to certain low level initialization functions in TPL"
424 depends on SPL && ARM
426 If enabled, then certain low level initializations (like setting up
427 the memory controller) are omitted and/or U-Boot does not relocate
429 Normally this variable MUST NOT be defined. The only exception is
430 when U-Boot is loaded (to RAM) by some other boot loader or by a
431 debugger which performs these initializations itself.
433 config SKIP_LOWLEVEL_INIT_ONLY
434 bool "Skip call to lowlevel_init during early boot ONLY"
437 This allows just the call to lowlevel_init() to be skipped. The
438 normal CP15 init (such as enabling the instruction cache) is still
441 config SPL_SKIP_LOWLEVEL_INIT_ONLY
442 bool "Skip call to lowlevel_init during early SPL boot ONLY"
443 depends on SPL && ARM
445 This allows just the call to lowlevel_init() to be skipped. The
446 normal CP15 init (such as enabling the instruction cache) is still
449 config TPL_SKIP_LOWLEVEL_INIT_ONLY
450 bool "Skip call to lowlevel_init during early TPL boot ONLY"
451 depends on TPL && ARM
453 This allows just the call to lowlevel_init() to be skipped. The
454 normal CP15 init (such as enabling the instruction cache) is still
459 config SYS_HAS_NONCACHED_MEMORY
460 bool "Enable reserving a non-cached memory area for drivers"
461 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
463 This is useful for drivers that would otherwise require a lot of
464 explicit cache maintenance. For some drivers it's also impossible to
465 properly maintain the cache. For example if the regions that need to
466 be flushed are not a multiple of the cache-line size, *and* padding
467 cannot be allocated between the regions to align them (i.e. if the
468 HW requires a contiguous array of regions, and the size of each
469 region is not cache-aligned), then a flush of one region may result
470 in overwriting data that hardware has written to another region in
471 the same cache-line. This can happen for example in network drivers
472 where descriptors for buffers are typically smaller than the CPU
473 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
475 config SYS_NONCACHED_MEMORY
476 hex "Size in bytes of the non-cached memory area"
477 depends on SYS_HAS_NONCACHED_MEMORY
480 Size of non-cached memory area. This area of memory will be typically
481 located right below the malloc() area and mapped uncached in the MMU.
483 source "arch/arc/Kconfig"
484 source "arch/arm/Kconfig"
485 source "arch/m68k/Kconfig"
486 source "arch/microblaze/Kconfig"
487 source "arch/mips/Kconfig"
488 source "arch/nios2/Kconfig"
489 source "arch/powerpc/Kconfig"
490 source "arch/sandbox/Kconfig"
491 source "arch/sh/Kconfig"
492 source "arch/x86/Kconfig"
493 source "arch/xtensa/Kconfig"
494 source "arch/riscv/Kconfig"
496 if ARM || M68K || PPC
498 source "arch/Kconfig.nxp"
502 source "board/keymile/Kconfig"
504 if MIPS || MICROBLAZE
507 prompt "Endianness selection"
509 Some MIPS boards can be configured for either little or big endian
510 byte order. These modes require different U-Boot images. In general there
511 is one preferred byteorder for a particular system but some systems are
512 just as commonly used in the one or the other endianness.
514 config SYS_BIG_ENDIAN
516 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
518 config SYS_LITTLE_ENDIAN
520 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE