1 PXA2xx SPI on SSP driver HOWTO
2 ===================================================
3 This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
4 synchronous serial port into a SPI master controller
5 (see Documentation/spi/spi_summary). The driver has the following features
7 - Support for any PXA2xx SSP
8 - SSP PIO and SSP DMA data transfers.
9 - External and Internal (SSPFRM) chip selects.
10 - Per slave device (chip) configuration.
11 - Full suspend, freeze, resume support.
13 The driver is built around a "spi_message" fifo serviced by workqueue and a
14 tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
15 (pump_transfer) is responsible for queuing SPI transactions and setting up and
16 launching the dma/interrupt driven transfers.
18 Declaring PXA2xx Master Controllers
19 -----------------------------------
20 Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
21 "platform device". The master configuration is passed to the driver via a table
22 found in arch/arm/mach-pxa/include/mach/pxa2xx_spi.h:
24 struct pxa2xx_spi_master {
25 enum pxa_ssp_type ssp_type;
31 The "pxa2xx_spi_master.ssp_type" field must have a value between 1 and 3 and
32 informs the driver which features a particular SSP supports.
34 The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the
35 corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
36 the "PXA2xx Developer Manual" section "Clocks and Power Management".
38 The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of
39 slave device (chips) attached to this SPI master.
41 The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
42 be used. This caused the driver to acquire two DMA channels: rx_channel and
43 tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
44 See the "PXA2xx Developer Manual" section "DMA Controller".
48 Below is a sample configuration using the PXA255 NSSP.
50 static struct resource pxa_spi_nssp_resources[] = {
52 .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
53 .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
54 .flags = IORESOURCE_MEM,
57 .start = IRQ_NSSP, /* NSSP IRQ */
59 .flags = IORESOURCE_IRQ,
63 static struct pxa2xx_spi_master pxa_nssp_master_info = {
64 .ssp_type = PXA25x_NSSP, /* Type of SSP */
65 .clock_enable = CKEN_NSSP, /* NSSP Peripheral clock */
66 .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
67 .enable_dma = 1, /* Enables NSSP DMA */
70 static struct platform_device pxa_spi_nssp = {
71 .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
72 .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
73 .resource = pxa_spi_nssp_resources,
74 .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
76 .platform_data = &pxa_nssp_master_info, /* Passed to driver */
80 static struct platform_device *devices[] __initdata = {
84 static void __init board_init(void)
86 (void)platform_add_device(devices, ARRAY_SIZE(devices));
89 Declaring Slave Devices
90 -----------------------
91 Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
92 using the "spi_board_info" structure found in "linux/spi/spi.h". See
93 "Documentation/spi/spi_summary" for additional information.
95 Each slave device attached to the PXA must provide slave specific configuration
96 information via the structure "pxa2xx_spi_chip" found in
97 "arch/arm/mach-pxa/include/mach/pxa2xx_spi.h". The pxa2xx_spi master controller driver
98 will uses the configuration whenever the driver communicates with the slave
99 device. All fields are optional.
101 struct pxa2xx_spi_chip {
107 void (*cs_control)(u32 command);
110 The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
111 used to configure the SSP hardware fifo. These fields are critical to the
112 performance of pxa2xx_spi driver and misconfiguration will result in rx
113 fifo overruns (especially in PIO mode transfers). Good default values are
118 The range is 1 to 16 where zero indicates "use default".
120 The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
121 engine and is related the "spi_device.bits_per_word" field. Read and understand
122 the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
123 to determine the correct value. An SSP configured for byte-wide transfers would
124 use a value of 8. The driver will determine a reasonable default if
127 The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
128 trailing bytes in the SSP receiver fifo. The correct value for this field is
129 dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
130 slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
131 timeouts and must busy-wait any trailing bytes.
133 The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
134 into internal loopback mode. In this mode the SSP controller internally
135 connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
138 The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
139 function for asserting/deasserting a slave device chip select. If the field is
140 NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
141 configured to use SSPFRM instead.
143 NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
144 chipselect is dropped after each spi_transfer. Most devices need chip select
145 asserted around the complete message. Use SSPFRM as a GPIO (through cs_control)
146 to accomodate these chips.
151 The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
152 "spi_board_info.controller_data" field. Below is a sample configuration using
155 /* Chip Select control for the CS8415A SPI slave device */
156 static void cs8415a_cs_control(u32 command)
158 if (command & PXA2XX_CS_ASSERT)
159 GPCR(2) = GPIO_bit(2);
161 GPSR(2) = GPIO_bit(2);
164 /* Chip Select control for the CS8405A SPI slave device */
165 static void cs8405a_cs_control(u32 command)
167 if (command & PXA2XX_CS_ASSERT)
168 GPCR(3) = GPIO_bit(3);
170 GPSR(3) = GPIO_bit(3);
173 static struct pxa2xx_spi_chip cs8415a_chip_info = {
174 .tx_threshold = 8, /* SSP hardward FIFO threshold */
175 .rx_threshold = 8, /* SSP hardward FIFO threshold */
176 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
177 .timeout = 235, /* See Intel documentation */
178 .cs_control = cs8415a_cs_control, /* Use external chip select */
181 static struct pxa2xx_spi_chip cs8405a_chip_info = {
182 .tx_threshold = 8, /* SSP hardward FIFO threshold */
183 .rx_threshold = 8, /* SSP hardward FIFO threshold */
184 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
185 .timeout = 235, /* See Intel documentation */
186 .cs_control = cs8405a_cs_control, /* Use external chip select */
189 static struct spi_board_info streetracer_spi_board_info[] __initdata = {
191 .modalias = "cs8415a", /* Name of spi_driver for this device */
192 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
193 .bus_num = 2, /* Framework bus number */
194 .chip_select = 0, /* Framework chip select */
195 .platform_data = NULL; /* No spi_driver specific config */
196 .controller_data = &cs8415a_chip_info, /* Master chip config */
197 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
200 .modalias = "cs8405a", /* Name of spi_driver for this device */
201 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
202 .bus_num = 2, /* Framework bus number */
203 .chip_select = 1, /* Framework chip select */
204 .controller_data = &cs8405a_chip_info, /* Master chip config */
205 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
209 static void __init streetracer_init(void)
211 spi_register_board_info(streetracer_spi_board_info,
212 ARRAY_SIZE(streetracer_spi_board_info));
216 DMA and PIO I/O Support
217 -----------------------
218 The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
219 transfers. The driver defaults to PIO mode and DMA transfers must be enabled
220 by setting the "enable_dma" flag in the "pxa2xx_spi_master" structure. The DMA
221 mode supports both coherent and stream based DMA mappings.
223 The following logic is used to determine the type of I/O to be used on
224 a per "spi_transfer" basis:
227 always use PIO transfers
229 if spi_message.len > 8191 then
230 print "rate limited" warning
233 if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
234 use coherent DMA mode
236 if rx_buf and tx_buf are aligned on 8 byte boundary then
237 use streaming DMA mode
245 David Brownell and others for mentoring the development of this driver.