1 PINCTRL (PIN CONTROL) subsystem
2 This document outlines the pin control subsystem in Linux
4 This subsystem deals with:
6 - Enumerating and naming controllable pins
8 - Multiplexing of pins, pads, fingers (etc) see below for details
10 - Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Definition of PIN CONTROLLER:
19 - A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
21 set drive strength, etc. for individual pins or groups of pins.
25 - PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
32 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
33 pin control framework, and this descriptor contains an array of pin descriptors
34 describing the pins handled by this specific pin controller.
36 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
56 To register a pin controller and name all the pins on this package we can do
59 #include <linux/pinctrl/pinctrl.h>
61 const struct pinctrl_pin_desc foo_pins[] = {
66 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
71 static struct pinctrl_desc foo_desc = {
74 .npins = ARRAY_SIZE(foo_pins),
79 int __init foo_probe(void)
81 struct pinctrl_dev *pctl;
83 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
85 pr_err("could not register foo pin driver\n");
88 To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89 selected drivers, you need to select them from your machine's Kconfig entry,
90 since these are so tightly integrated with the machines they are used on.
91 See for example arch/arm/mach-u300/Kconfig for an example.
93 Pins usually have fancier names than this. You can find these in the datasheet
94 for your chip. Notice that the core pinctrl.h file provides a fancy macro
95 called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
96 the pins from 0 in the upper left corner to 63 in the lower right corner.
97 This enumeration was arbitrarily chosen, in practice you need to think
98 through your numbering system so that it matches the layout of registers
99 and such things in your driver, or the code may become complicated. You must
100 also consider matching of offsets to the GPIO ranges that may be handled by
103 For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104 like this, walking around the edge of the chip, which seems to be industry
105 standard too (all these pads had names, too):
119 Many controllers need to deal with groups of pins, so the pin controller
120 subsystem has a mechanism for enumerating groups of pins and retrieving the
121 actual enumerated pins that are part of a certain group.
123 For example, say that we have a group of pins dealing with an SPI interface
124 on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
127 These two groups are presented to the pin control subsystem by implementing
128 some generic pinctrl_ops like this:
130 #include <linux/pinctrl/pinctrl.h>
134 const unsigned int *pins;
135 const unsigned num_pins;
138 static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139 static const unsigned int i2c0_pins[] = { 24, 25 };
141 static const struct foo_group foo_groups[] = {
145 .num_pins = ARRAY_SIZE(spi0_pins),
150 .num_pins = ARRAY_SIZE(i2c0_pins),
155 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
157 return ARRAY_SIZE(foo_groups);
160 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
163 return foo_groups[selector].name;
166 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167 unsigned ** const pins,
168 unsigned * const num_pins)
170 *pins = (unsigned *) foo_groups[selector].pins;
171 *num_pins = foo_groups[selector].num_pins;
175 static struct pinctrl_ops foo_pctrl_ops = {
176 .get_groups_count = foo_get_groups_count,
177 .get_group_name = foo_get_group_name,
178 .get_group_pins = foo_get_group_pins,
182 static struct pinctrl_desc foo_desc = {
184 .pctlops = &foo_pctrl_ops,
187 The pin control subsystem will call the .get_groups_count() function to
188 determine the total number of legal selectors, then it will call the other functions
189 to retrieve the name and pins of the group. Maintaining the data structure of
190 the groups is up to the driver, this is just a simple example - in practice you
191 may need more entries in your group structure, for example specific register
192 ranges associated with each group and so on.
198 Pins can sometimes be software-configured in various ways, mostly related
199 to their electronic properties when used as inputs or outputs. For example you
200 may be able to make an output pin high impedance, or "tristate" meaning it is
201 effectively disconnected. You may be able to connect an input pin to VDD or GND
202 using a certain resistor value - pull up and pull down - so that the pin has a
203 stable value when nothing is driving the rail it is connected to, or when it's
206 Pin configuration can be programmed by adding configuration entries into the
207 mapping table; see section "Board/machine configuration" below.
209 The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
210 above, is entirely defined by the pin controller driver.
212 The pin configuration driver implements callbacks for changing pin
213 configuration in the pin controller ops like this:
215 #include <linux/pinctrl/pinctrl.h>
216 #include <linux/pinctrl/pinconf.h>
217 #include "platform_x_pindefs.h"
219 static int foo_pin_config_get(struct pinctrl_dev *pctldev,
221 unsigned long *config)
223 struct my_conftype conf;
225 ... Find setting for pin @ offset ...
227 *config = (unsigned long) conf;
230 static int foo_pin_config_set(struct pinctrl_dev *pctldev,
232 unsigned long config)
234 struct my_conftype *conf = (struct my_conftype *) config;
237 case PLATFORM_X_PULL_UP:
243 static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
245 unsigned long *config)
250 static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
252 unsigned long config)
257 static struct pinconf_ops foo_pconf_ops = {
258 .pin_config_get = foo_pin_config_get,
259 .pin_config_set = foo_pin_config_set,
260 .pin_config_group_get = foo_pin_config_group_get,
261 .pin_config_group_set = foo_pin_config_group_set,
264 /* Pin config operations are handled by some pin controller */
265 static struct pinctrl_desc foo_desc = {
267 .confops = &foo_pconf_ops,
270 Since some controllers have special logic for handling entire groups of pins
271 they can exploit the special whole-group pin control function. The
272 pin_config_group_set() callback is allowed to return the error code -EAGAIN,
273 for groups it does not want to handle, or if it just wants to do some
274 group-level handling and then fall through to iterate over all pins, in which
275 case each individual pin will be treated by separate pin_config_set() calls as
279 Interaction with the GPIO subsystem
280 ===================================
282 The GPIO drivers may want to perform operations of various types on the same
283 physical pins that are also registered as pin controller pins.
285 First and foremost, the two subsystems can be used as completely orthogonal,
286 see the section named "pin control requests from drivers" and
287 "drivers needing both pin control and GPIOs" below for details. But in some
288 situations a cross-subsystem mapping between pins and GPIOs is needed.
290 Since the pin controller subsystem have its pinspace local to the pin
291 controller we need a mapping so that the pin control subsystem can figure out
292 which pin controller handles control of a certain GPIO pin. Since a single
293 pin controller may be muxing several GPIO ranges (typically SoCs that have
294 one set of pins, but internally several GPIO silicon blocks, each modelled as
295 a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
298 struct gpio_chip chip_a;
299 struct gpio_chip chip_b;
301 static struct pinctrl_gpio_range gpio_range_a = {
310 static struct pinctrl_gpio_range gpio_range_b = {
320 struct pinctrl_dev *pctl;
322 pinctrl_add_gpio_range(pctl, &gpio_range_a);
323 pinctrl_add_gpio_range(pctl, &gpio_range_b);
326 So this complex system has one pin controller handling two different
327 GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
328 "chip b" have different .pin_base, which means a start pin number of the
331 The GPIO range of "chip a" starts from the GPIO base of 32 and actual
332 pin range also starts from 32. However "chip b" has different starting
333 offset for the GPIO range and pin range. The GPIO range of "chip b" starts
334 from GPIO number 48, while the pin range of "chip b" starts from 64.
336 We can convert a gpio number to actual pin number using this "pin_base".
337 They are mapped in the global GPIO pin space at:
340 - GPIO range : [32 .. 47]
341 - pin range : [32 .. 47]
343 - GPIO range : [48 .. 55]
344 - pin range : [64 .. 71]
346 The above examples assume the mapping between the GPIOs and pins is
347 linear. If the mapping is sparse or haphazard, an array of arbitrary pin
348 numbers can be encoded in the range like this:
350 static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
352 static struct pinctrl_gpio_range gpio_range = {
357 .npins = ARRAY_SIZE(range_pins),
361 In this case the pin_base property will be ignored. If the name of a pin
362 group is known, the pins and npins elements of the above structure can be
363 initialised using the function pinctrl_get_group_pins(), e.g. for pin
366 pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
368 When GPIO-specific functions in the pin control subsystem are called, these
369 ranges will be used to look up the appropriate pin controller by inspecting
370 and matching the pin to the pin ranges across all controllers. When a
371 pin controller handling the matching range is found, GPIO-specific functions
372 will be called on that specific pin controller.
374 For all functionalities dealing with pin biasing, pin muxing etc, the pin
375 controller subsystem will look up the corresponding pin number from the passed
376 in gpio number, and use the range's internals to retrieve a pin number. After
377 that, the subsystem passes it on to the pin control driver, so the driver
378 will get a pin number into its handled number range. Further it is also passed
379 the range ID value, so that the pin controller knows which range it should
382 Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
383 section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
384 pinctrl and gpio drivers.
390 These calls use the pinmux_* naming prefix. No other calls should use that
397 PINMUX, also known as padmux, ballmux, alternate functions or mission modes
398 is a way for chip vendors producing some kind of electrical packages to use
399 a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
400 functions, depending on the application. By "application" in this context
401 we usually mean a way of soldering or wiring the package into an electronic
402 system, even though the framework makes it possible to also change the function
405 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
409 8 | o | o o o o o o o
411 7 | o | o o o o o o o
413 6 | o | o o o o o o o
415 5 | o | o | o o o o o o
417 4 o o o o o o | o | o
419 3 o o o o o o | o | o
421 2 o o o o o o | o | o
422 +-------+-------+-------+---+---+
423 1 | o o | o o | o o | o | o |
424 +-------+-------+-------+---+---+
426 This is not tetris. The game to think of is chess. Not all PGA/BGA packages
427 are chessboard-like, big ones have "holes" in some arrangement according to
428 different design patterns, but we're using this as a simple example. Of the
429 pins you see some will be taken by things like a few VCC and GND to feed power
430 to the chip, and quite a few will be taken by large ports like an external
431 memory interface. The remaining pins will often be subject to pin multiplexing.
433 The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
434 to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
435 pinctrl_register_pins() and a suitable data set as shown earlier.
437 In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
438 (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
439 some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
440 be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
441 we cannot use the SPI port and I2C port at the same time. However in the inside
442 of the package the silicon performing the SPI logic can alternatively be routed
443 out on pins { G4, G3, G2, G1 }.
445 On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
446 special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
447 consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
448 { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
449 port on pins { G4, G3, G2, G1 } of course.
451 This way the silicon blocks present inside the chip can be multiplexed "muxed"
452 out on different pin ranges. Often contemporary SoC (systems on chip) will
453 contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
454 different pins by pinmux settings.
456 Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
457 common to be able to use almost any pin as a GPIO pin if it is not currently
458 in use by some other I/O port.
464 The purpose of the pinmux functionality in the pin controller subsystem is to
465 abstract and provide pinmux settings to the devices you choose to instantiate
466 in your machine configuration. It is inspired by the clk, GPIO and regulator
467 subsystems, so devices will request their mux setting, but it's also possible
468 to request a single pin for e.g. GPIO.
472 - FUNCTIONS can be switched in and out by a driver residing with the pin
473 control subsystem in the drivers/pinctrl/* directory of the kernel. The
474 pin control driver knows the possible functions. In the example above you can
475 identify three pinmux functions, one for spi, one for i2c and one for mmc.
477 - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
478 In this case the array could be something like: { spi0, i2c0, mmc0 }
479 for the three available functions.
481 - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
482 function is *always* associated with a certain set of pin groups, could
483 be just a single one, but could also be many. In the example above the
484 function i2c is associated with the pins { A5, B5 }, enumerated as
485 { 24, 25 } in the controller pin space.
487 The Function spi is associated with pin groups { A8, A7, A6, A5 }
488 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
489 { 38, 46, 54, 62 } respectively.
491 Group names must be unique per pin controller, no two groups on the same
492 controller may have the same name.
494 - The combination of a FUNCTION and a PIN GROUP determine a certain function
495 for a certain set of pins. The knowledge of the functions and pin groups
496 and their machine-specific particulars are kept inside the pinmux driver,
497 from the outside only the enumerators are known, and the driver core can:
499 - Request the name of a function with a certain selector (>= 0)
500 - A list of groups associated with a certain function
501 - Request that a certain group in that list to be activated for a certain
504 As already described above, pin groups are in turn self-descriptive, so
505 the core will retrieve the actual pin range in a certain group from the
508 - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
509 device by the board file, device tree or similar machine setup configuration
510 mechanism, similar to how regulators are connected to devices, usually by
511 name. Defining a pin controller, function and group thus uniquely identify
512 the set of pins to be used by a certain device. (If only one possible group
513 of pins is available for the function, no group name need to be supplied -
514 the core will simply select the first and only group available.)
516 In the example case we can define that this particular machine shall
517 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
518 fi2c0 group gi2c0, on the primary pin controller, we get mappings
522 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
523 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
526 Every map must be assigned a state name, pin controller, device and
527 function. The group is not compulsory - if it is omitted the first group
528 presented by the driver as applicable for the function will be selected,
529 which is useful for simple cases.
531 It is possible to map several groups to the same combination of device,
532 pin controller and function. This is for cases where a certain function on
533 a certain pin controller may use different sets of pins in different
536 - PINS for a certain FUNCTION using a certain PIN GROUP on a certain
537 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
538 other device mux setting or GPIO pin request has already taken your physical
539 pin, you will be denied the use of it. To get (activate) a new setting, the
540 old one has to be put (deactivated) first.
542 Sometimes the documentation and hardware registers will be oriented around
543 pads (or "fingers") rather than pins - these are the soldering surfaces on the
544 silicon inside the package, and may or may not match the actual number of
545 pins/balls underneath the capsule. Pick some enumeration that makes sense to
546 you. Define enumerators only for the pins you can control if that makes sense.
550 We assume that the number of possible function maps to pin groups is limited by
551 the hardware. I.e. we assume that there is no system where any function can be
552 mapped to any pin, like in a phone exchange. So the available pin groups for
553 a certain function will be limited to a few choices (say up to eight or so),
554 not hundreds or any amount of choices. This is the characteristic we have found
555 by inspecting available pinmux hardware, and a necessary assumption since we
556 expect pinmux drivers to present *all* possible function vs pin group mappings
563 The pinmux core takes care of preventing conflicts on pins and calling
564 the pin controller driver to execute different settings.
566 It is the responsibility of the pinmux driver to impose further restrictions
567 (say for example infer electronic limitations due to load, etc.) to determine
568 whether or not the requested function can actually be allowed, and in case it
569 is possible to perform the requested mux setting, poke the hardware so that
572 Pinmux drivers are required to supply a few callback functions, some are
573 optional. Usually the enable() and disable() functions are implemented,
574 writing values into some certain registers to activate a certain mux setting
577 A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
578 into some register named MUX to select a certain function with a certain
579 group of pins would work something like this:
581 #include <linux/pinctrl/pinctrl.h>
582 #include <linux/pinctrl/pinmux.h>
586 const unsigned int *pins;
587 const unsigned num_pins;
590 static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
591 static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
592 static const unsigned i2c0_pins[] = { 24, 25 };
593 static const unsigned mmc0_1_pins[] = { 56, 57 };
594 static const unsigned mmc0_2_pins[] = { 58, 59 };
595 static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
597 static const struct foo_group foo_groups[] = {
599 .name = "spi0_0_grp",
601 .num_pins = ARRAY_SIZE(spi0_0_pins),
604 .name = "spi0_1_grp",
606 .num_pins = ARRAY_SIZE(spi0_1_pins),
611 .num_pins = ARRAY_SIZE(i2c0_pins),
614 .name = "mmc0_1_grp",
616 .num_pins = ARRAY_SIZE(mmc0_1_pins),
619 .name = "mmc0_2_grp",
621 .num_pins = ARRAY_SIZE(mmc0_2_pins),
624 .name = "mmc0_3_grp",
626 .num_pins = ARRAY_SIZE(mmc0_3_pins),
631 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
633 return ARRAY_SIZE(foo_groups);
636 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
639 return foo_groups[selector].name;
642 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
643 unsigned ** const pins,
644 unsigned * const num_pins)
646 *pins = (unsigned *) foo_groups[selector].pins;
647 *num_pins = foo_groups[selector].num_pins;
651 static struct pinctrl_ops foo_pctrl_ops = {
652 .get_groups_count = foo_get_groups_count,
653 .get_group_name = foo_get_group_name,
654 .get_group_pins = foo_get_group_pins,
657 struct foo_pmx_func {
659 const char * const *groups;
660 const unsigned num_groups;
663 static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
664 static const char * const i2c0_groups[] = { "i2c0_grp" };
665 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
668 static const struct foo_pmx_func foo_functions[] = {
671 .groups = spi0_groups,
672 .num_groups = ARRAY_SIZE(spi0_groups),
676 .groups = i2c0_groups,
677 .num_groups = ARRAY_SIZE(i2c0_groups),
681 .groups = mmc0_groups,
682 .num_groups = ARRAY_SIZE(mmc0_groups),
686 int foo_get_functions_count(struct pinctrl_dev *pctldev)
688 return ARRAY_SIZE(foo_functions);
691 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
693 return foo_functions[selector].name;
696 static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
697 const char * const **groups,
698 unsigned * const num_groups)
700 *groups = foo_functions[selector].groups;
701 *num_groups = foo_functions[selector].num_groups;
705 int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
708 u8 regbit = (1 << selector + group);
710 writeb((readb(MUX)|regbit), MUX)
714 void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
717 u8 regbit = (1 << selector + group);
719 writeb((readb(MUX) & ~(regbit)), MUX)
723 struct pinmux_ops foo_pmxops = {
724 .get_functions_count = foo_get_functions_count,
725 .get_function_name = foo_get_fname,
726 .get_function_groups = foo_get_groups,
727 .enable = foo_enable,
728 .disable = foo_disable,
731 /* Pinmux operations are handled by some pin controller */
732 static struct pinctrl_desc foo_desc = {
734 .pctlops = &foo_pctrl_ops,
735 .pmxops = &foo_pmxops,
738 In the example activating muxing 0 and 1 at the same time setting bits
739 0 and 1, uses one pin in common so they would collide.
741 The beauty of the pinmux subsystem is that since it keeps track of all
742 pins and who is using them, it will already have denied an impossible
743 request like that, so the driver does not need to worry about such
744 things - when it gets a selector passed in, the pinmux subsystem makes
745 sure no other device or GPIO assignment is already using the selected
746 pins. Thus bits 0 and 1 in the control register will never be set at the
749 All the above functions are mandatory to implement for a pinmux driver.
752 Pin control interaction with the GPIO subsystem
753 ===============================================
755 Note that the following implies that the use case is to use a certain pin
756 from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
757 and similar functions. There are cases where you may be using something
758 that your datasheet calls "GPIO mode", but actually is just an electrical
759 configuration for a certain device. See the section below named
760 "GPIO mode pitfalls" for more details on this scenario.
762 The public pinmux API contains two functions named pinctrl_request_gpio()
763 and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
764 gpiolib-based drivers as part of their gpio_request() and
765 gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
766 shall only be called from within respective gpio_direction_[input|output]
767 gpiolib implementation.
769 NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
770 controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
771 that driver request proper muxing and other control for its pins.
773 The function list could become long, especially if you can convert every
774 individual pin into a GPIO pin independent of any other pins, and then try
775 the approach to define every pin as a function.
777 In this case, the function array would become 64 entries for each GPIO
778 setting and then the device functions.
780 For this reason there are two functions a pin control driver can implement
781 to enable only GPIO on an individual pin: .gpio_request_enable() and
782 .gpio_disable_free().
784 This function will pass in the affected GPIO range identified by the pin
785 controller core, so you know which GPIO pins are being affected by the request
788 If your driver needs to have an indication from the framework of whether the
789 GPIO pin shall be used for input or output you can implement the
790 .gpio_set_direction() function. As described this shall be called from the
791 gpiolib driver and the affected GPIO range, pin offset and desired direction
792 will be passed along to this function.
794 Alternatively to using these special functions, it is fully allowed to use
795 named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
796 obtain the function "gpioN" where "N" is the global GPIO pin number if no
797 special GPIO-handler is registered.
803 Due to the naming conventions used by hardware engineers, where "GPIO"
804 is taken to mean different things than what the kernel does, the developer
805 may be confused by a datasheet talking about a pin being possible to set
806 into "GPIO mode". It appears that what hardware engineers mean with
807 "GPIO mode" is not necessarily the use case that is implied in the kernel
808 interface <linux/gpio.h>: a pin that you grab from kernel code and then
809 either listen for input or drive high/low to assert/deassert some
812 Rather hardware engineers think that "GPIO mode" means that you can
813 software-control a few electrical properties of the pin that you would
814 not be able to control if the pin was in some other mode, such as muxed in
817 The GPIO portions of a pin and its relation to a certain pin controller
818 configuration and muxing logic can be constructed in several ways. Here
825 Physical pins --- pad --- pinmux -+- I2C
832 Here some electrical properties of the pin can be configured no matter
833 whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
834 pin, you can also drive it high/low from "GPIO" registers.
835 Alternatively, the pin can be controlled by a certain peripheral, while
836 still applying desired pin config properties. GPIO functionality is thus
837 orthogonal to any other device using the pin.
839 In this arrangement the registers for the GPIO portions of the pin controller,
840 or the registers for the GPIO hardware module are likely to reside in a
841 separate memory range only intended for GPIO driving, and the register
842 range dealing with pin config and pin multiplexing get placed into a
843 different memory range and a separate section of the data sheet.
850 Physical pins --- pad --- pinmux -+- I2C
857 In this arrangement, the GPIO functionality can always be enabled, such that
858 e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
859 pulsed out. It is likely possible to disrupt the traffic on the pin by doing
860 wrong things on the GPIO block, as it is never really disconnected. It is
861 possible that the GPIO, pin config and pin multiplex registers are placed into
862 the same memory range and the same section of the data sheet, although that
863 need not be the case.
865 From a kernel point of view, however, these are different aspects of the
866 hardware and shall be put into different subsystems:
868 - Registers (or fields within registers) that control electrical
869 properties of the pin such as biasing and drive strength should be
870 exposed through the pinctrl subsystem, as "pin configuration" settings.
872 - Registers (or fields within registers) that control muxing of signals
873 from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
874 be exposed through the pinctrl subsystem, as mux functions.
876 - Registers (or fields within registers) that control GPIO functionality
877 such as setting a GPIO's output value, reading a GPIO's input value, or
878 setting GPIO pin direction should be exposed through the GPIO subsystem,
879 and if they also support interrupt capabilities, through the irqchip
882 Depending on the exact HW register design, some functions exposed by the
883 GPIO subsystem may call into the pinctrl subsystem in order to
884 co-ordinate register settings across HW modules. In particular, this may
885 be needed for HW with separate GPIO and pin controller HW modules, where
886 e.g. GPIO direction is determined by a register in the pin controller HW
887 module rather than the GPIO HW module.
889 Electrical properties of the pin such as biasing and drive strength
890 may be placed at some pin-specific register in all cases or as part
891 of the GPIO register in case (B) especially. This doesn't mean that such
892 properties necessarily pertain to what the Linux kernel calls "GPIO".
894 Example: a pin is usually muxed in to be used as a UART TX line. But during
895 system sleep, we need to put this pin into "GPIO mode" and ground it.
897 If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
898 to think that you need to come up with something really complex, that the
899 pin shall be used for UART TX and GPIO at the same time, that you will grab
900 a pin control handle and set it to a certain state to enable UART TX to be
901 muxed in, then twist it over to GPIO mode and use gpio_direction_output()
902 to drive it low during sleep, then mux it over to UART TX again when you
903 wake up and maybe even gpio_request/gpio_free as part of this cycle. This
904 all gets very complicated.
906 The solution is to not think that what the datasheet calls "GPIO mode"
907 has to be handled by the <linux/gpio.h> interface. Instead view this as
908 a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
909 and you find this in the documentation:
911 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
912 1 to indicate high level, argument 0 to indicate low level.
914 So it is perfectly possible to push a pin into "GPIO mode" and drive the
915 line low as part of the usual pin control map. So for example your UART
916 driver may look like this:
918 #include <linux/pinctrl/consumer.h>
920 struct pinctrl *pinctrl;
921 struct pinctrl_state *pins_default;
922 struct pinctrl_state *pins_sleep;
924 pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
925 pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
928 retval = pinctrl_select_state(pinctrl, pins_default);
930 retval = pinctrl_select_state(pinctrl, pins_sleep);
932 And your machine configuration may look like this:
933 --------------------------------------------------
935 static unsigned long uart_default_mode[] = {
936 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
939 static unsigned long uart_sleep_mode[] = {
940 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
943 static struct pinctrl_map pinmap[] __initdata = {
944 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
946 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
947 "UART_TX_PIN", uart_default_mode),
948 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
949 "u0_group", "gpio-mode"),
950 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
951 "UART_TX_PIN", uart_sleep_mode),
955 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
958 Here the pins we want to control are in the "u0_group" and there is some
959 function called "u0" that can be enabled on this group of pins, and then
960 everything is UART business as usual. But there is also some function
961 named "gpio-mode" that can be mapped onto the same pins to move them into
964 This will give the desired effect without any bogus interaction with the
965 GPIO subsystem. It is just an electrical configuration used by that device
966 when going to sleep, it might imply that the pin is set into something the
967 datasheet calls "GPIO mode", but that is not the point: it is still used
968 by that UART device to control the pins that pertain to that very UART
969 driver, putting them into modes needed by the UART. GPIO in the Linux
970 kernel sense are just some 1-bit line, and is a different use case.
972 How the registers are poked to attain the push or pull, and output low
973 configuration and the muxing of the "u0" or "gpio-mode" group onto these
974 pins is a question for the driver.
976 Some datasheets will be more helpful and refer to the "GPIO mode" as
977 "low power mode" rather than anything to do with GPIO. This often means
978 the same thing electrically speaking, but in this latter case the
979 software engineers will usually quickly identify that this is some
980 specific muxing or configuration rather than anything related to the GPIO
984 Board/machine configuration
985 ==================================
987 Boards and machines define how a certain complete running system is put
988 together, including how GPIOs and devices are muxed, how regulators are
989 constrained and how the clock tree looks. Of course pinmux settings are also
992 A pin controller configuration for a machine looks pretty much like a simple
993 regulator configuration, so for the example array above we want to enable i2c
994 and spi on the second function mapping:
996 #include <linux/pinctrl/machine.h>
998 static const struct pinctrl_map mapping[] __initconst = {
1000 .dev_name = "foo-spi.0",
1001 .name = PINCTRL_STATE_DEFAULT,
1002 .type = PIN_MAP_TYPE_MUX_GROUP,
1003 .ctrl_dev_name = "pinctrl-foo",
1004 .data.mux.function = "spi0",
1007 .dev_name = "foo-i2c.0",
1008 .name = PINCTRL_STATE_DEFAULT,
1009 .type = PIN_MAP_TYPE_MUX_GROUP,
1010 .ctrl_dev_name = "pinctrl-foo",
1011 .data.mux.function = "i2c0",
1014 .dev_name = "foo-mmc.0",
1015 .name = PINCTRL_STATE_DEFAULT,
1016 .type = PIN_MAP_TYPE_MUX_GROUP,
1017 .ctrl_dev_name = "pinctrl-foo",
1018 .data.mux.function = "mmc0",
1022 The dev_name here matches to the unique device name that can be used to look
1023 up the device struct (just like with clockdev or regulators). The function name
1024 must match a function provided by the pinmux driver handling this pin range.
1026 As you can see we may have several pin controllers on the system and thus
1027 we need to specify which one of them contains the functions we wish to map.
1029 You register this pinmux mapping to the pinmux subsystem by simply:
1031 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
1033 Since the above construct is pretty common there is a helper macro to make
1034 it even more compact which assumes you want to use pinctrl-foo and position
1035 0 for mapping, for example:
1037 static struct pinctrl_map mapping[] __initdata = {
1038 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1041 The mapping table may also contain pin configuration entries. It's common for
1042 each pin/group to have a number of configuration entries that affect it, so
1043 the table entries for configuration reference an array of config parameters
1044 and values. An example using the convenience macros is shown below:
1046 static unsigned long i2c_grp_configs[] = {
1051 static unsigned long i2c_pin_configs[] = {
1056 static struct pinctrl_map mapping[] __initdata = {
1057 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
1058 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1059 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1060 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1063 Finally, some devices expect the mapping table to contain certain specific
1064 named states. When running on hardware that doesn't need any pin controller
1065 configuration, the mapping table must still contain those named states, in
1066 order to explicitly indicate that the states were provided and intended to
1067 be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1068 a named state without causing any pin controller to be programmed:
1070 static struct pinctrl_map mapping[] __initdata = {
1071 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1078 As it is possible to map a function to different groups of pins an optional
1079 .group can be specified like this:
1083 .dev_name = "foo-spi.0",
1084 .name = "spi0-pos-A",
1085 .type = PIN_MAP_TYPE_MUX_GROUP,
1086 .ctrl_dev_name = "pinctrl-foo",
1088 .group = "spi0_0_grp",
1091 .dev_name = "foo-spi.0",
1092 .name = "spi0-pos-B",
1093 .type = PIN_MAP_TYPE_MUX_GROUP,
1094 .ctrl_dev_name = "pinctrl-foo",
1096 .group = "spi0_1_grp",
1100 This example mapping is used to switch between two positions for spi0 at
1101 runtime, as described further below under the heading "Runtime pinmuxing".
1103 Further it is possible for one named state to affect the muxing of several
1104 groups of pins, say for example in the mmc0 example above, where you can
1105 additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1106 three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1107 case), we define a mapping like this:
1111 .dev_name = "foo-mmc.0",
1113 .type = PIN_MAP_TYPE_MUX_GROUP,
1114 .ctrl_dev_name = "pinctrl-foo",
1116 .group = "mmc0_1_grp",
1119 .dev_name = "foo-mmc.0",
1121 .type = PIN_MAP_TYPE_MUX_GROUP,
1122 .ctrl_dev_name = "pinctrl-foo",
1124 .group = "mmc0_1_grp",
1127 .dev_name = "foo-mmc.0",
1129 .type = PIN_MAP_TYPE_MUX_GROUP,
1130 .ctrl_dev_name = "pinctrl-foo",
1132 .group = "mmc0_2_grp",
1135 .dev_name = "foo-mmc.0",
1137 .type = PIN_MAP_TYPE_MUX_GROUP,
1138 .ctrl_dev_name = "pinctrl-foo",
1140 .group = "mmc0_1_grp",
1143 .dev_name = "foo-mmc.0",
1145 .type = PIN_MAP_TYPE_MUX_GROUP,
1146 .ctrl_dev_name = "pinctrl-foo",
1148 .group = "mmc0_2_grp",
1151 .dev_name = "foo-mmc.0",
1153 .type = PIN_MAP_TYPE_MUX_GROUP,
1154 .ctrl_dev_name = "pinctrl-foo",
1156 .group = "mmc0_3_grp",
1160 The result of grabbing this mapping from the device with something like
1161 this (see next paragraph):
1163 p = devm_pinctrl_get(dev);
1164 s = pinctrl_lookup_state(p, "8bit");
1165 ret = pinctrl_select_state(p, s);
1169 p = devm_pinctrl_get_select(dev, "8bit");
1171 Will be that you activate all the three bottom records in the mapping at
1172 once. Since they share the same name, pin controller device, function and
1173 device, and since we allow multiple groups to match to a single device, they
1174 all get selected, and they all get enabled and disable simultaneously by the
1178 Pin control requests from drivers
1179 =================================
1181 When a device driver is about to probe the device core will automatically
1182 attempt to issue pinctrl_get_select_default() on these devices.
1183 This way driver writers do not need to add any of the boilerplate code
1184 of the type found below. However when doing fine-grained state selection
1185 and not using the "default" state, you may have to do some device driver
1186 handling of the pinctrl handles and states.
1188 So if you just want to put the pins for a certain device into the default
1189 state and be done with it, there is nothing you need to do besides
1190 providing the proper mapping table. The device core will take care of
1193 Generally it is discouraged to let individual drivers get and enable pin
1194 control. So if possible, handle the pin control in platform code or some other
1195 place where you have access to all the affected struct device * pointers. In
1196 some cases where a driver needs to e.g. switch between different mux mappings
1197 at runtime this is not possible.
1199 A typical case is if a driver needs to switch bias of pins from normal
1200 operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1201 PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1202 current in sleep mode.
1204 A driver may request a certain control state to be activated, usually just the
1205 default state like this:
1207 #include <linux/pinctrl/consumer.h>
1211 struct pinctrl_state *s;
1217 /* Allocate a state holder named "foo" etc */
1218 struct foo_state *foo = ...;
1220 foo->p = devm_pinctrl_get(&device);
1221 if (IS_ERR(foo->p)) {
1222 /* FIXME: clean up "foo" here */
1223 return PTR_ERR(foo->p);
1226 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1227 if (IS_ERR(foo->s)) {
1228 /* FIXME: clean up "foo" here */
1232 ret = pinctrl_select_state(foo->s);
1234 /* FIXME: clean up "foo" here */
1239 This get/lookup/select/put sequence can just as well be handled by bus drivers
1240 if you don't want each and every driver to handle it and you know the
1241 arrangement on your bus.
1243 The semantics of the pinctrl APIs are:
1245 - pinctrl_get() is called in process context to obtain a handle to all pinctrl
1246 information for a given client device. It will allocate a struct from the
1247 kernel memory to hold the pinmux state. All mapping table parsing or similar
1248 slow operations take place within this API.
1250 - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1251 to be called automatically on the retrieved pointer when the associated
1252 device is removed. It is recommended to use this function over plain
1255 - pinctrl_lookup_state() is called in process context to obtain a handle to a
1256 specific state for a client device. This operation may be slow, too.
1258 - pinctrl_select_state() programs pin controller hardware according to the
1259 definition of the state as given by the mapping table. In theory, this is a
1260 fast-path operation, since it only involved blasting some register settings
1261 into hardware. However, note that some pin controllers may have their
1262 registers on a slow/IRQ-based bus, so client devices should not assume they
1263 can call pinctrl_select_state() from non-blocking contexts.
1265 - pinctrl_put() frees all information associated with a pinctrl handle.
1267 - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1268 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1269 However, use of this function will be rare, due to the automatic cleanup
1270 that will occur even without calling it.
1272 pinctrl_get() must be paired with a plain pinctrl_put().
1273 pinctrl_get() may not be paired with devm_pinctrl_put().
1274 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1275 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1277 Usually the pin control core handled the get/put pair and call out to the
1278 device drivers bookkeeping operations, like checking available functions and
1279 the associated pins, whereas the enable/disable pass on to the pin controller
1280 driver which takes care of activating and/or deactivating the mux setting by
1281 quickly poking some registers.
1283 The pins are allocated for your device when you issue the devm_pinctrl_get()
1284 call, after this you should be able to see this in the debugfs listing of all
1287 NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1288 requested pinctrl handles, for example if the pinctrl driver has not yet
1289 registered. Thus make sure that the error path in your driver gracefully
1290 cleans up and is ready to retry the probing later in the startup process.
1293 Drivers needing both pin control and GPIOs
1294 ==========================================
1296 Again, it is discouraged to let drivers lookup and select pin control states
1297 themselves, but again sometimes this is unavoidable.
1299 So say that your driver is fetching its resources like this:
1301 #include <linux/pinctrl/consumer.h>
1302 #include <linux/gpio.h>
1304 struct pinctrl *pinctrl;
1307 pinctrl = devm_pinctrl_get_select_default(&dev);
1308 gpio = devm_gpio_request(&dev, 14, "foo");
1310 Here we first request a certain pin state and then request GPIO 14 to be
1311 used. If you're using the subsystems orthogonally like this, you should
1312 nominally always get your pinctrl handle and select the desired pinctrl
1313 state BEFORE requesting the GPIO. This is a semantic convention to avoid
1314 situations that can be electrically unpleasant, you will certainly want to
1315 mux in and bias pins in a certain way before the GPIO subsystems starts to
1318 The above can be hidden: using the device core, the pinctrl core may be
1319 setting up the config and muxing for the pins right before the device is
1320 probing, nevertheless orthogonal to the GPIO subsystem.
1322 But there are also situations where it makes sense for the GPIO subsystem
1323 to communicate directly with the pinctrl subsystem, using the latter as a
1324 back-end. This is when the GPIO driver may call out to the functions
1325 described in the section "Pin control interaction with the GPIO subsystem"
1326 above. This only involves per-pin multiplexing, and will be completely
1327 hidden behind the gpio_*() function namespace. In this case, the driver
1328 need not interact with the pin control subsystem at all.
1330 If a pin control driver and a GPIO driver is dealing with the same pins
1331 and the use cases involve multiplexing, you MUST implement the pin controller
1332 as a back-end for the GPIO driver like this, unless your hardware design
1333 is such that the GPIO controller can override the pin controller's
1334 multiplexing state through hardware without the need to interact with the
1338 System pin control hogging
1339 ==========================
1341 Pin control map entries can be hogged by the core when the pin controller
1342 is registered. This means that the core will attempt to call pinctrl_get(),
1343 lookup_state() and select_state() on it immediately after the pin control
1344 device has been registered.
1346 This occurs for mapping table entries where the client device name is equal
1347 to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1350 .dev_name = "pinctrl-foo",
1351 .name = PINCTRL_STATE_DEFAULT,
1352 .type = PIN_MAP_TYPE_MUX_GROUP,
1353 .ctrl_dev_name = "pinctrl-foo",
1354 .function = "power_func",
1357 Since it may be common to request the core to hog a few always-applicable
1358 mux settings on the primary pin controller, there is a convenience macro for
1361 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1363 This gives the exact same result as the above construction.
1369 It is possible to mux a certain function in and out at runtime, say to move
1370 an SPI port from one set of pins to another set of pins. Say for example for
1371 spi0 in the example above, we expose two different groups of pins for the same
1372 function, but with different named in the mapping as described under
1373 "Advanced mapping" above. So that for an SPI device, we have two states named
1374 "pos-A" and "pos-B".
1376 This snippet first muxes the function in the pins defined by group A, enables
1377 it, disables and releases it, and muxes it in on the pins defined by group B:
1379 #include <linux/pinctrl/consumer.h>
1382 struct pinctrl_state *s1, *s2;
1387 p = devm_pinctrl_get(&device);
1391 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1395 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1402 /* Enable on position A */
1403 ret = pinctrl_select_state(s1);
1409 /* Enable on position B */
1410 ret = pinctrl_select_state(s2);
1417 The above has to be done from process context. The reservation of the pins
1418 will be done when the state is activated, so in effect one specific pin
1419 can be used by different functions at different times on a running system.