sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
- /*
- * wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL,
- * LDELAY);
- */
/* Enable ivahd and sl2 clocks */
sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
- /* wait for ivahd to become accessible */
- /* wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); */
- /* wait for sl2 to become accessible */
- /* wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); */
-
/* Enable Tesla clocks */
sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
/* wait for tesla to become accessible */
- /* wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); */
-
- /* TODO: Some hack needed by MM: Clean this */
- #if 0 /* Doesn't work on some Zebu */
- *(volatile int *)0x4a306910 = 0x00000003;
- *(volatile int *)0x550809a0 = 0x00000001;
- *(volatile int *)0x55080a20 = 0x00000007;
- #endif
/* ABE clocks */
sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); */
sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); */
sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); */
sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); */
sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); */
/* Disable sleep transitions */
sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
/* MMC clocks */
sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
- /*wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
- /*wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL,
- * LDELAY); */
sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
/* Enable Camera clocks */
sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); */
sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); */
sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
/* Enable DSS clocks */
sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); */
sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); */
/* Check for DSS Clocks */
while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00)
/* Enable SGX clocks */
sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); */
/* Check for SGX FCLK and ICLK */
while (__raw_readl(0x4A009200) != 0x302)
;
- /* sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); */
/* Enable hsi/unipro/usb clocks */
sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
- /* wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); */
sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL,
- * LDELAY); */
/* enable the 32K, 48M optional clocks and enable the module */
sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
- /* wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); */
}
/******************************************************************************
__raw_writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
- /*
- * EMIF_PWR_MGMT_CTRL
- */
- //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL;
- //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100;
/*
* poll MR0 register (DAI bit)
* REG_CS[31] = 0 -- Mode register command to CS0
else
__raw_writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0);
- /* EMIF2 only at 0x90000000 */
- //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200;
-
__raw_writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2);
__raw_writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3);
*/
configure_core_dpll_no_lock();
- /* No IDLE: BUG in SDC */
- /* sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
- while(((*(volatile int *)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
- */
__raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
__raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
-
base_addr = EMIF1_BASE;
emif_config(base_addr);
/* Put the Core Subsystem PD to ON State */
- /* No IDLE: BUG in SDC */
- /* sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
- while(((*(volatile int *)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
- */
__raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
__raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
__raw_writel(0, 0x80000000);
__raw_writel(0, 0x80000000);
-
- /* *((volatile int *)0x90000000) = 0; */
}
/*****************************************
* Routine: board_init
MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \
MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */
-#define MUX_DEFAULT_OMAP4_ALL() \
- MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \
- MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \
- MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \
- MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \
- MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \
- MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \
- MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \
- MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \
- MV(CP(GPMC_AD8), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \
- MV(CP(GPMC_AD9), (M3_SAFE)) /* gpio_33 */ \
- MV(CP(GPMC_AD10), (M3_SAFE)) /* gpio_34 */ \
- MV(CP(GPMC_AD11), (M3_SAFE)) /* gpio_35 */ \
- MV(CP(GPMC_AD12), (M3_SAFE)) /* gpio_36 */ \
- MV(CP(GPMC_AD13), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \
- MV(CP(GPMC_AD14), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \
- MV(CP(GPMC_AD15), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
- MV(CP(GPMC_A16), (M3_SAFE)) /* gpio_40 */ \
- MV(CP(GPMC_A17), (M3_SAFE)) /* gpio_41 */ \
- MV(CP(GPMC_A18), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \
- MV(CP(GPMC_A19), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \
- MV(CP(GPMC_A20), (M3_SAFE)) /* gpio_44 */ \
- MV(CP(GPMC_A21), (M3_SAFE)) /* gpio_45 */ \
- MV(CP(GPMC_A22), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \
- MV(CP(GPMC_A23), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \
- MV(CP(GPMC_A24), (M3_SAFE)) /* gpio_48 */ \
- MV(CP(GPMC_A25), (M3_SAFE)) /* gpio_49 */ \
- MV(CP(GPMC_NCS0), (M0)) /* gpmc_ncs0 */ \
- MV(CP(GPMC_NCS1), (M3_SAFE)) /* gpio_51 */ \
- MV(CP(GPMC_NCS2), (M3_SAFE)) /* gpio_52 */ \
- MV(CP(GPMC_NCS3), (M3_SAFE)) /* gpio_53 */ \
- MV(CP(GPMC_NWP), (M0_SAFE)) /* gpmc_nwp */ \
- MV(CP(GPMC_CLK), (M3_SAFE)) /* gpio_55 */ \
- MV(CP(GPMC_NADV_ALE), (M0)) /* gpmc_nadv_ale */ \
- MV(CP(GPMC_NOE), (PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \
- MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \
- MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \
- MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \
- MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \
- MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
- MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \
- MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \
- MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \
- MV(CP(C2C_DATA14), (M1_SAFE)) /* dsi2_te0 */ \
- MV(CP(C2C_DATA15), (M3_SAFE)) /* gpio_104 */ \
- MV(CP(HDMI_HPD), (M0_SAFE)) /* hdmi_hpd */ \
- MV(CP(HDMI_CEC), (M0_SAFE)) /* hdmi_cec */ \
- MV(CP(HDMI_DDC_SCL), (M0_SAFE)) /* hdmi_ddc_scl */ \
- MV(CP(HDMI_DDC_SDA), (M0_SAFE)) /* hdmi_ddc_sda */ \
- MV(CP(CSI21_DX0), (M0_SAFE)) /* csi21_dx0 */ \
- MV(CP(CSI21_DY0), (M0_SAFE)) /* csi21_dy0 */ \
- MV(CP(CSI21_DX1), (M0_SAFE)) /* csi21_dx1 */ \
- MV(CP(CSI21_DY1), (M0_SAFE)) /* csi21_dy1 */ \
- MV(CP(CSI21_DX2), (M0_SAFE)) /* csi21_dx2 */ \
- MV(CP(CSI21_DY2), (M0_SAFE)) /* csi21_dy2 */ \
- MV(CP(CSI21_DX3), (M0_SAFE)) /* csi21_dx3 */ \
- MV(CP(CSI21_DY3), (M0_SAFE)) /* csi21_dy3 */ \
- MV(CP(CSI21_DX4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \
- MV(CP(CSI21_DY4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \
- MV(CP(CSI22_DX0), (M0_SAFE)) /* csi22_dx0 */ \
- MV(CP(CSI22_DY0), (M0_SAFE)) /* csi22_dy0 */ \
- MV(CP(CSI22_DX1), (M0_SAFE)) /* csi22_dx1 */ \
- MV(CP(CSI22_DY1), (M0_SAFE)) /* csi22_dy1 */ \
- MV(CP(CAM_SHUTTER), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \
- MV(CP(CAM_STROBE), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \
- MV(CP(CAM_GLOBALRESET), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \
- MV(CP(USBB1_ULPITLL_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \
- MV(CP(USBB1_ULPITLL_STP), (PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \
- MV(CP(USBB1_ULPITLL_DIR), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \
- MV(CP(USBB1_ULPITLL_NXT), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \
- MV(CP(USBB1_ULPITLL_DAT0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \
- MV(CP(USBB1_ULPITLL_DAT1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \
- MV(CP(USBB1_ULPITLL_DAT2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \
- MV(CP(USBB1_ULPITLL_DAT3), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \
- MV(CP(USBB1_ULPITLL_DAT4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \
- MV(CP(USBB1_ULPITLL_DAT5), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \
- MV(CP(USBB1_ULPITLL_DAT6), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \
- MV(CP(USBB1_ULPITLL_DAT7), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \
- MV(CP(USBB1_HSIC_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \
- MV(CP(USBB1_HSIC_STROBE), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \
- MV(CP(USBC1_ICUSB_DP), (M0_SAFE)) /* usbc1_icusb_dp */ \
- MV(CP(USBC1_ICUSB_DM), (M0_SAFE)) /* usbc1_icusb_dm */ \
- MV(CP(SDMMC1_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \
- MV(CP(SDMMC1_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \
- MV(CP(SDMMC1_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \
- MV(CP(SDMMC1_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \
- MV(CP(SDMMC1_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \
- MV(CP(SDMMC1_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \
- MV(CP(SDMMC1_DAT4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \
- MV(CP(SDMMC1_DAT5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \
- MV(CP(SDMMC1_DAT6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \
- MV(CP(SDMMC1_DAT7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \
- MV(CP(ABE_MCBSP2_CLKX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \
- MV(CP(ABE_MCBSP2_DR), (IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \
- MV(CP(ABE_MCBSP2_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \
- MV(CP(ABE_MCBSP2_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \
- MV(CP(ABE_MCBSP1_CLKX), (M1_SAFE)) /* abe_slimbus1_clock */ \
- MV(CP(ABE_MCBSP1_DR), (M1_SAFE)) /* abe_slimbus1_data */ \
- MV(CP(ABE_MCBSP1_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \
- MV(CP(ABE_MCBSP1_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \
- MV(CP(ABE_PDM_UL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \
- MV(CP(ABE_PDM_DL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \
- MV(CP(ABE_PDM_FRAME), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \
- MV(CP(ABE_PDM_LB_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \
- MV(CP(ABE_CLKS), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \
- MV(CP(ABE_DMIC_CLK1), (M0_SAFE)) /* abe_dmic_clk1 */ \
- MV(CP(ABE_DMIC_DIN1), (M0_SAFE)) /* abe_dmic_din1 */ \
- MV(CP(ABE_DMIC_DIN2), (M0_SAFE)) /* abe_dmic_din2 */ \
- MV(CP(ABE_DMIC_DIN3), (M0_SAFE)) /* abe_dmic_din3 */ \
- MV(CP(UART2_CTS), (PTU | IEN | M0)) /* uart2_cts */ \
- MV(CP(UART2_RTS), (M0)) /* uart2_rts */ \
- MV(CP(UART2_RX), (PTU | IEN | M0)) /* uart2_rx */ \
- MV(CP(UART2_TX), (M0)) /* uart2_tx */ \
- MV(CP(HDQ_SIO), (M3_SAFE)) /* gpio_127 */ \
- MV(CP(I2C1_SCL), (PTU | IEN | M0)) /* i2c1_scl */ \
- MV(CP(I2C1_SDA), (PTU | IEN | M0)) /* i2c1_sda */ \
- MV(CP(I2C2_SCL), (PTU | IEN | M0)) /* i2c2_scl */ \
- MV(CP(I2C2_SDA), (PTU | IEN | M0)) /* i2c2_sda */ \
- MV(CP(I2C3_SCL), (PTU | IEN | M0)) /* i2c3_scl */ \
- MV(CP(I2C3_SDA), (PTU | IEN | M0)) /* i2c3_sda */ \
- MV(CP(I2C4_SCL), (PTU | IEN | M0)) /* i2c4_scl */ \
- MV(CP(I2C4_SDA), (PTU | IEN | M0)) /* i2c4_sda */ \
- MV(CP(MCSPI1_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \
- MV(CP(MCSPI1_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \
- MV(CP(MCSPI1_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \
- MV(CP(MCSPI1_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \
- MV(CP(MCSPI1_CS1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \
- MV(CP(MCSPI1_CS2), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \
- MV(CP(MCSPI1_CS3), (M3_SAFE)) /* gpio_140 */ \
- MV(CP(UART3_CTS_RCTX), (PTU | IEN | M0)) /* uart3_tx */ \
- MV(CP(UART3_RTS_SD), (M0)) /* uart3_rts_sd */ \
- MV(CP(UART3_RX_IRRX), (IEN | M0)) /* uart3_rx */ \
- MV(CP(UART3_TX_IRTX), (M0)) /* uart3_tx */ \
- MV(CP(SDMMC5_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \
- MV(CP(SDMMC5_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \
- MV(CP(SDMMC5_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \
- MV(CP(SDMMC5_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \
- MV(CP(SDMMC5_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \
- MV(CP(SDMMC5_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \
- MV(CP(MCSPI4_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \
- MV(CP(MCSPI4_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \
- MV(CP(MCSPI4_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \
- MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
- MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \
- MV(CP(UART4_TX), (M0)) /* uart4_tx */ \
- MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \
- MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \
- MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \
- MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \
- MV(CP(USBB2_ULPITLL_DAT0), (M5)) /* dispc2_data20 */ \
- MV(CP(USBB2_ULPITLL_DAT1), (M5)) /* dispc2_data19 */ \
- MV(CP(USBB2_ULPITLL_DAT2), (M5)) /* dispc2_data18 */ \
- MV(CP(USBB2_ULPITLL_DAT3), (M5)) /* dispc2_data15 */ \
- MV(CP(USBB2_ULPITLL_DAT4), (M5)) /* dispc2_data14 */ \
- MV(CP(USBB2_ULPITLL_DAT5), (M5)) /* dispc2_data13 */ \
- MV(CP(USBB2_ULPITLL_DAT6), (M5)) /* dispc2_data12 */ \
- MV(CP(USBB2_ULPITLL_DAT7), (M5)) /* dispc2_data11 */ \
- MV(CP(USBB2_HSIC_DATA), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \
- MV(CP(USBB2_HSIC_STROBE), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \
- MV(CP(UNIPRO_TX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \
- MV(CP(UNIPRO_TY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \
- MV(CP(UNIPRO_TX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \
- MV(CP(UNIPRO_TY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \
- MV(CP(UNIPRO_TX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \
- MV(CP(UNIPRO_TY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \
- MV(CP(UNIPRO_RX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \
- MV(CP(UNIPRO_RY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \
- MV(CP(UNIPRO_RX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \
- MV(CP(UNIPRO_RY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \
- MV(CP(UNIPRO_RX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \
- MV(CP(UNIPRO_RY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \
- MV(CP(USBA0_OTG_CE), (PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \
- MV(CP(USBA0_OTG_DP), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \
- MV(CP(USBA0_OTG_DM), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \
- MV(CP(FREF_CLK1_OUT), (M0_SAFE)) /* fref_clk1_out */ \
- MV(CP(FREF_CLK2_OUT), (M0_SAFE)) /* fref_clk2_out */ \
- MV(CP(SYS_NIRQ1), (PTU | IEN | M0)) /* sys_nirq1 */ \
- MV(CP(SYS_NIRQ2), (PTU | IEN | M0)) /* sys_nirq2 */ \
- MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \
- MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \
- MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \
- MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \
- MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \
- MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \
- MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \
- MV(CP(DPM_EMU1), (M0_SAFE)) /* dpm_emu1 */ \
- MV(CP(DPM_EMU2), (M0_SAFE)) /* dpm_emu2 */ \
- MV(CP(DPM_EMU3), (M5)) /* dispc2_data10 */ \
- MV(CP(DPM_EMU4), (M5)) /* dispc2_data9 */ \
- MV(CP(DPM_EMU5), (M5)) /* dispc2_data16 */ \
- MV(CP(DPM_EMU6), (M5)) /* dispc2_data17 */ \
- MV(CP(DPM_EMU7), (M5)) /* dispc2_hsync */ \
- MV(CP(DPM_EMU8), (M5)) /* dispc2_pclk */ \
- MV(CP(DPM_EMU9), (M5)) /* dispc2_vsync */ \
- MV(CP(DPM_EMU10), (M5)) /* dispc2_de */ \
- MV(CP(DPM_EMU11), (M5)) /* dispc2_data8 */ \
- MV(CP(DPM_EMU12), (M5)) /* dispc2_data7 */ \
- MV(CP(DPM_EMU13), (M5)) /* dispc2_data6 */ \
- MV(CP(DPM_EMU14), (M5)) /* dispc2_data5 */ \
- MV(CP(DPM_EMU15), (M5)) /* dispc2_data4 */ \
- MV(CP(DPM_EMU16), (M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \
- MV(CP(DPM_EMU17), (M5)) /* dispc2_data2 */ \
- MV(CP(DPM_EMU18), (M5)) /* dispc2_data1 */ \
- MV(CP(DPM_EMU19), (M5)) /* dispc2_data0 */ \
- MV1(WK(PAD0_SIM_IO), (M0_SAFE)) /* sim_io */ \
- MV1(WK(PAD1_SIM_CLK), (M0_SAFE)) /* sim_clk */ \
- MV1(WK(PAD0_SIM_RESET), (M0_SAFE)) /* sim_reset */ \
- MV1(WK(PAD1_SIM_CD), (M0_SAFE)) /* sim_cd */ \
- MV1(WK(PAD0_SIM_PWRCTRL), (M0_SAFE)) /* sim_pwrctrl */ \
- MV1(WK(PAD1_SR_SCL), (PTU | IEN | M0)) /* sr_scl */ \
- MV1(WK(PAD0_SR_SDA), (PTU | IEN | M0)) /* sr_sda */ \
- MV1(WK(PAD1_FREF_XTAL_IN), (M0_SAFE)) /* # */ \
- MV1(WK(PAD0_FREF_SLICER_IN), (M0_SAFE)) /* fref_slicer_in */ \
- MV1(WK(PAD1_FREF_CLK_IOREQ), (M0_SAFE)) /* fref_clk_ioreq */ \
- MV1(WK(PAD0_FREF_CLK0_OUT), (M0)) /* sys_drm_msecure */ \
- MV1(WK(PAD1_FREF_CLK3_REQ), (M0)) /* # */ \
- MV1(WK(PAD0_FREF_CLK3_OUT), (M0_SAFE)) /* fref_clk3_out */ \
- MV1(WK(PAD1_FREF_CLK4_REQ), (M0_SAFE)) /* # */ \
- MV1(WK(PAD0_FREF_CLK4_OUT), (M0_SAFE)) /* # */ \
- MV1(WK(PAD1_SYS_32K), (IEN | M0_SAFE)) /* sys_32k */ \
- MV1(WK(PAD0_SYS_NRESPWRON), (IEN | M0_SAFE)) /* sys_nrespwron */ \
- MV1(WK(PAD1_SYS_NRESWARM), (IEN | M0_SAFE)) /* sys_nreswarm */ \
- MV1(WK(PAD0_SYS_PWR_REQ), (M0_SAFE)) /* sys_pwr_req */ \
- MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \
- MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \
- MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \
- MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \
- MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \
- MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \
- MV1(WK(PAD0_JTAG_TDI), (IEN | M0)) /* jtag_tdi */ \
- MV1(WK(PAD1_JTAG_TDO), (M0)) /* jtag_tdo */
-
/**********************************************************
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers
git.openpandora.org / pandora-x-loader.git / commitdiff