2 * (C) Copyright 2004-2009
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/cpu.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/mux.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/sys_info.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/mem.h>
33 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
34 #include <linux/mtd/nand_legacy.h>
37 /* EMIF and DMM registers */
38 #define EMIF1_BASE 0x4c000000
39 #define EMIF2_BASE 0x4d000000
40 #define DMM_BASE 0x4e000000
42 #define EMIF_MOD_ID_REV 0x0000
43 #define EMIF_STATUS 0x0004
44 #define EMIF_SDRAM_CONFIG 0x0008
45 #define EMIF_LPDDR2_NVM_CONFIG 0x000C
46 #define EMIF_SDRAM_REF_CTRL 0x0010
47 #define EMIF_SDRAM_REF_CTRL_SHDW 0x0014
48 #define EMIF_SDRAM_TIM_1 0x0018
49 #define EMIF_SDRAM_TIM_1_SHDW 0x001C
50 #define EMIF_SDRAM_TIM_2 0x0020
51 #define EMIF_SDRAM_TIM_2_SHDW 0x0024
52 #define EMIF_SDRAM_TIM_3 0x0028
53 #define EMIF_SDRAM_TIM_3_SHDW 0x002C
54 #define EMIF_LPDDR2_NVM_TIM 0x0030
55 #define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034
56 #define EMIF_PWR_MGMT_CTRL 0x0038
57 #define EMIF_PWR_MGMT_CTRL_SHDW 0x003C
58 #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
59 #define EMIF_LPDDR2_MODE_REG_CFG 0x0050
60 #define EMIF_L3_CONFIG 0x0054
61 #define EMIF_L3_CFG_VAL_1 0x0058
62 #define EMIF_L3_CFG_VAL_2 0x005C
63 #define IODFT_TLGC 0x0060
64 #define EMIF_PERF_CNT_1 0x0080
65 #define EMIF_PERF_CNT_2 0x0084
66 #define EMIF_PERF_CNT_CFG 0x0088
67 #define EMIF_PERF_CNT_SEL 0x008C
68 #define EMIF_PERF_CNT_TIM 0x0090
69 #define EMIF_READ_IDLE_CTRL 0x0098
70 #define EMIF_READ_IDLE_CTRL_SHDW 0x009c
71 #define EMIF_ZQ_CONFIG 0x00C8
72 #define EMIF_DDR_PHY_CTRL_1 0x00E4
73 #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8
74 #define EMIF_DDR_PHY_CTRL_2 0x00EC
76 #define DMM_LISA_MAP_0 0x0040
77 #define DMM_LISA_MAP_1 0x0044
78 #define DMM_LISA_MAP_2 0x0048
79 #define DMM_LISA_MAP_3 0x004C
87 #define REF_EN 0x40000000
106 #define MR1_VALUE ((MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \
109 /* defines for MR2 */
110 #define MR2_RL3_WL1 1
111 #define MR2_RL4_WL2 2
112 #define MR2_RL5_WL2 3
113 #define MR2_RL6_WL3 4
115 /* defines for MR10 */
116 #define MR10_ZQINIT 0xFF
117 #define MR10_ZQRESET 0xC3
118 #define MR10_ZQCL 0xAB
119 #define MR10_ZQCS 0x56
122 /* TODO: FREQ update method is not working so shadow registers programming
123 * is just for same of completeness. This would be safer if auto
124 * trasnitions are working
126 #define FREQ_UPDATE_EMIF
127 /* EMIF Needs to be configured@19.2 MHz and shadow registers
128 * should be programmed for new OPP.
131 #define SDRAM_CONFIG_INIT 0x80800EB1
132 #define DDR_PHY_CTRL_1_INIT 0x849FFFF5
133 #define READ_IDLE_CTRL 0x000501FF
134 #define PWR_MGMT_CTRL 0x4000000f
135 #define PWR_MGMT_CTRL_OPP100 0x4000000f
136 #define ZQ_CONFIG 0x500b3215
138 #define CS1_MR(mr) ((mr) | 0x80000000)
151 const struct ddr_regs ddr_regs_380_mhz = {
155 .phy_ctrl_1 = 0x849FF408,
156 .ref_ctrl = 0x000005ca,
157 .config_init = 0x80000eb1,
158 .config_final = 0x80001ab1,
159 .zq_config = 0x500b3215,
165 * Unused timings - but we may need them later
166 * Keep them commented
169 const struct ddr_regs ddr_regs_400_mhz = {
173 .phy_ctrl_1 = 0x849FF408,
174 .ref_ctrl = 0x00000618,
175 .config_init = 0x80000eb1,
176 .config_final = 0x80001ab1,
177 .zq_config = 0x500b3215,
182 const struct ddr_regs ddr_regs_200_mhz = {
186 .phy_ctrl_1 = 0x849FF405,
187 .ref_ctrl = 0x0000030c,
188 .config_init = 0x80000eb1,
189 .config_final = 0x80000eb1,
190 .zq_config = 0x500b3215,
196 const struct ddr_regs ddr_regs_200_mhz_2cs = {
200 .phy_ctrl_1 = 0x849FF405,
201 .ref_ctrl = 0x0000030c,
202 .config_init = 0x80000eb9,
203 .config_final = 0x80000eb9,
204 .zq_config = 0xD00b3215,
209 const struct ddr_regs ddr_regs_400_mhz_2cs = {
210 /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
214 .phy_ctrl_1 = 0x849FF408,
215 .ref_ctrl = 0x00000618,
216 .config_init = 0x80000eb9,
217 .config_final = 0x80001ab9,
218 .zq_config = 0xD00b3215,
223 /*******************************************************
225 * Description: spinning delay to use before udelay works
226 ******************************************************/
227 static inline void delay(unsigned long loops)
229 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
230 "bne 1b" : "=r" (loops) : "0"(loops));
234 void big_delay(unsigned int count)
237 for (i = 0; i < count; i++)
241 void reset_phy(unsigned int base)
243 __raw_writel(__raw_readl(base + IODFT_TLGC) | (1 << 10),
247 /* TODO: FREQ update method is not working so shadow registers programming
248 * is just for same of completeness. This would be safer if auto
249 * trasnitions are working
251 static int emif_config(unsigned int base)
253 unsigned int reg_value, rev;
254 const struct ddr_regs *ddr_regs = NULL;
255 rev = omap_revision();
257 if (rev == OMAP4430_ES1_0)
258 ddr_regs = &ddr_regs_380_mhz;
259 else if (rev == OMAP4430_ES2_0)
260 ddr_regs = &ddr_regs_200_mhz_2cs;
261 else if (rev >= OMAP4430_ES2_1)
262 ddr_regs = &ddr_regs_400_mhz_2cs;
265 * set SDRAM CONFIG register
266 * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
267 * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
268 * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
269 * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
270 * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
271 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column
272 * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
274 __raw_writel(__raw_readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xbfffffff,
275 base + EMIF_LPDDR2_NVM_CONFIG);
276 __raw_writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
278 /* PHY control values */
279 __raw_writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
280 __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
283 * EMIF_READ_IDLE_CTRL
285 __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
286 __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
291 __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
292 __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
297 __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
298 __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
303 __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
304 __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
306 __raw_writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
309 * poll MR0 register (DAI bit)
310 * REG_CS[31] = 0 -- Mode register command to CS0
311 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
312 * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
315 __raw_writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
318 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
319 } while (reg_value & 1);
321 __raw_writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
324 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
325 } while (reg_value & 1);
328 /* set MR10 register */
329 __raw_writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
330 __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
331 __raw_writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
332 __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
334 /* wait for tZQINIT=1us */
337 /* set MR1 register */
338 __raw_writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
339 __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
340 __raw_writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
341 __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
343 /* set MR2 register RL=6 for OPP100 */
344 __raw_writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
345 __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
346 __raw_writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
347 __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
349 /* Set SDRAM CONFIG register again here with final RL-WL value */
350 __raw_writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
351 __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
354 * EMIF_SDRAM_REF_CTRL
355 * refresh rate = DDR_CLK / reg_refresh_rate
356 * 3.9 uS = (400MHz) / reg_refresh_rate
358 __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
359 __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
361 /* set MR16 register */
362 __raw_writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
363 __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
364 __raw_writel(CS1_MR(MR16_ADDR | REF_EN),
365 base + EMIF_LPDDR2_MODE_REG_CFG);
366 __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
368 /* LPDDR2 init complete */
372 /*****************************************
374 * Description: Configure DDR
375 * EMIF1 -- CS0 -- DDR1 (256 MB)
376 * EMIF2 -- CS0 -- DDR2 (256 MB)
377 *****************************************/
378 static void ddr_init(void)
380 unsigned int base_addr, rev;
381 rev = omap_revision();
383 if (rev == OMAP4430_ES1_0) {
384 /* Configurte the Control Module DDRIO device */
385 __raw_writel(0x1c1c1c1c, 0x4A100638);
386 __raw_writel(0x1c1c1c1c, 0x4A10063c);
387 __raw_writel(0x1c1c1c1c, 0x4A100640);
388 __raw_writel(0x1c1c1c1c, 0x4A100648);
389 __raw_writel(0x1c1c1c1c, 0x4A10064c);
390 __raw_writel(0x1c1c1c1c, 0x4A100650);
391 /* LPDDR2IO set to NMOS PTV */
392 __raw_writel(0x00ffc000, 0x4A100704);
393 } else if (rev == OMAP4430_ES2_0) {
394 __raw_writel(0x9e9e9e9e, 0x4A100638);
395 __raw_writel(0x9e9e9e9e, 0x4A10063c);
396 __raw_writel(0x9e9e9e9e, 0x4A100640);
397 __raw_writel(0x9e9e9e9e, 0x4A100648);
398 __raw_writel(0x9e9e9e9e, 0x4A10064c);
399 __raw_writel(0x9e9e9e9e, 0x4A100650);
400 /* LPDDR2IO set to NMOS PTV */
401 __raw_writel(0x00ffc000, 0x4A100704);
408 /* Both EMIFs 128 byte interleaved*/
409 if (rev == OMAP4430_ES1_0)
410 __raw_writel(0x80540300, DMM_BASE + DMM_LISA_MAP_0);
412 __raw_writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0);
414 __raw_writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2);
415 __raw_writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3);
417 /* DDR needs to be initialised @ 19.2 MHz
418 * So put core DPLL in bypass mode
419 * Configure the Core DPLL but don't lock it
421 configure_core_dpll_no_lock();
423 __raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
424 __raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
426 base_addr = EMIF1_BASE;
427 emif_config(base_addr);
429 /* Configure EMIF24D */
430 base_addr = EMIF2_BASE;
431 emif_config(base_addr);
432 /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
433 lock_core_dpll_shadow();
434 /* TODO: SDC needs few hacks to get DDR freq update working */
436 /* Set DLL_OVERRIDE = 0 */
437 __raw_writel(0, CM_DLL_CTRL);
441 /* Check for DDR PHY ready for EMIF1 & EMIF2 */
442 while (!(__raw_readl(EMIF1_BASE + EMIF_STATUS) & 4) ||
443 !(__raw_readl(EMIF2_BASE + EMIF_STATUS) & 4))
446 /* Reprogram the DDR PYHY Control register */
447 /* PHY control values */
449 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
450 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
452 /* Put the Core Subsystem PD to ON State */
454 __raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
455 __raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
458 * In n a specific situation, the OCP interface between the DMM and
460 * 1. A TILER port is used to perform 2D burst writes of
461 * width 1 and height 8
462 * 2. ELLAn port is used to perform reads
463 * 3. All accesses are routed to the same EMIF controller
465 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
466 * be kept higher than default 0x7. As per recommondation 0x0A will
467 * be used for better performance with REG_LL_THRESH_MAX = 0x00
469 if (rev == OMAP4430_ES1_0) {
470 __raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG);
471 __raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG);
475 * DMM : DMM_LISA_MAP_0(Section_0)
476 * [31:24] SYS_ADDR 0x80
477 * [22:20] SYS_SIZE 0x7 - 2Gb
478 * [19:18] SDRC_INTLDMM 0x1 - 128 byte
479 * [17:16] SDRC_ADDRSPC 0x0
481 * [7:0] SDRC_ADDR 0X0
483 reset_phy(EMIF1_BASE);
484 reset_phy(EMIF2_BASE);
486 __raw_writel(0, 0x80000000);
487 __raw_writel(0, 0x80000000);
489 /*****************************************
490 * Routine: board_init
491 * Description: Early hardware init.
492 *****************************************/
498 /*************************************************************
499 * Routine: get_mem_type(void) - returns the kind of memory connected
500 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
501 *************************************************************/
502 u32 get_mem_type(void)
504 /* no nand, so return GPMC_NONE */
508 /*****************************************
509 * Routine: secure_unlock
510 * Description: Setup security registers for access
512 *****************************************/
513 void secure_unlock_mem(void)
515 /* Permission values for registers -Full fledged permissions to all */
516 #define UNLOCK_1 0xFFFFFFFF
517 #define UNLOCK_2 0x00000000
518 #define UNLOCK_3 0x0000FFFF
520 /* Protection Module Register Target APE (PM_RT)*/
521 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
522 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
523 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
524 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
526 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
527 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
528 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
530 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
531 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
532 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
533 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
536 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
537 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
538 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
540 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
543 /**********************************************************
544 * Routine: try_unlock_sram()
545 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
547 ***********************************************************/
548 void try_unlock_memory(void)
550 /* if GP device unlock device SRAM for general use */
551 /* secure code breaks for Secure/Emulation device - HS/E/T*/
555 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
556 static int scale_vcores(void)
558 unsigned int rev = omap_revision();
559 /* For VC bypass only VCOREx_CGF_FORCE is necessary and
560 * VCOREx_CFG_VOLTAGE changes can be discarded
562 /* PRM_VC_CFG_I2C_MODE */
563 __raw_writel(0, 0x4A307BA8);
565 /* PRM_VC_CFG_I2C_CLK */
566 __raw_writel(0x6026, 0x4A307BAC);
568 /* set VCORE1 force VSEL */
569 /* PRM_VC_VAL_BYPASS) */
570 if (rev == OMAP4430_ES1_0)
571 __raw_writel(0x3B5512, 0x4A307BA0);
573 __raw_writel(0x3A5512, 0x4A307BA0);
575 __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
576 while (__raw_readl(0x4A307BA0) & 0x1000000)
579 /* PRM_IRQSTATUS_MPU */
580 __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
582 /* FIXME: set VCORE2 force VSEL, Check the reset value */
583 /* PRM_VC_VAL_BYPASS) */
584 if (rev == OMAP4430_ES1_0)
585 __raw_writel(0x315B12, 0x4A307BA0);
587 __raw_writel(0x295B12, 0x4A307BA0);
589 __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
590 while (__raw_readl(0x4A307BA0) & 0x1000000)
593 /* PRM_IRQSTATUS_MPU */
594 __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
596 /*/set VCORE3 force VSEL */
597 /* PRM_VC_VAL_BYPASS */
600 __raw_writel(0x316112, 0x4A307BA0);
603 __raw_writel(0x296112, 0x4A307BA0);
606 __raw_writel(0x2A6112, 0x4A307BA0);
609 __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
610 while (__raw_readl(0x4A307BA0) & 0x1000000)
613 /* PRM_IRQSTATUS_MPU */
614 __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
620 /**********************************************************
622 * Description: Does early system init of muxing and clocks.
623 * - Called path is with SRAM stack.
624 **********************************************************/
628 unsigned int rev = omap_revision();
633 /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
634 /* Currently SMI in Kernel on ES2 devices seems to have an isse
635 * Once that is resolved, we can postpone this config to kernel
637 /* setup_auxcr(get_device_type(), external_boot); */
641 /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
642 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
647 if (rev != OMAP4430_ES1_0) {
648 if (__raw_readl(0x4805D138) & (1<<22)) {
649 /* enable software ioreq */
650 sr32(0x4A30a31C, 8, 1, 0x1);
651 /* set for sys_clk (38.4MHz) */
652 sr32(0x4A30a31C, 1, 2, 0x0);
653 /* set divisor to 2 */
654 sr32(0x4A30a31C, 16, 4, 0x1);
655 /* set the clock source to active */
656 sr32(0x4A30a110, 0, 1, 0x1);
658 sr32(0x4A30a110, 2, 2, 0x3);
660 /* enable software ioreq */
661 sr32(0x4A30a314, 8, 1, 0x1);
662 /* set for PER_DPLL */
663 sr32(0x4A30a314, 1, 2, 0x2);
664 /* set divisor to 16 */
665 sr32(0x4A30a314, 16, 4, 0xf);
666 /* set the clock source to active */
667 sr32(0x4A30a110, 0, 1, 0x1);
669 sr32(0x4A30a110, 2, 2, 0x3);
675 /*******************************************************
676 * Routine: misc_init_r
677 * Description: Init ethernet (done here so udelay works)
678 ********************************************************/
679 int misc_init_r(void)
684 /******************************************************
685 * Routine: wait_for_command_complete
686 * Description: Wait for posting to finish on watchdog
687 ******************************************************/
688 void wait_for_command_complete(unsigned int wd_base)
692 pending = __raw_readl(wd_base + WWPS);
696 /*******************************************************************
698 * Description: take the Ethernet controller out of reset and wait
699 * for the EEPROM load to complete.
700 ******************************************************************/
702 /**********************************************
704 * Description: sets uboots idea of sdram size
705 **********************************************/
711 #define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000
731 #define MV(OFFSET, VALUE)\
732 __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET));
733 #define MV1(OFFSET, VALUE)\
734 __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET));
736 #define CP(x) (CONTROL_PADCONF_##x)
737 #define WK(x) (CONTROL_WKUP_##x)
740 * IDIS - Input Disable
741 * PTD - Pull type Down
743 * DIS - Pull type selection is inactive
744 * EN - Pull type selection is active
746 * The commented string gives the final mux configuration for that pin
749 #define MUX_DEFAULT_OMAP4() \
750 MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \
751 MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \
752 MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \
753 MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \
754 MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \
755 MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \
756 MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \
757 MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \
758 MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \
759 MV(CP(GPMC_AD9) , ( PTU | IEN | M3)) /* gpio_33 */ \
760 MV(CP(GPMC_AD10) , ( PTU | IEN | M3)) /* gpio_34 */ \
761 MV(CP(GPMC_AD11) , ( PTU | IEN | M3)) /* gpio_35 */ \
762 MV(CP(GPMC_AD12) , ( PTU | IEN | M3)) /* gpio_36 */ \
763 MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \
764 MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \
765 MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
766 MV(CP(GPMC_A16) , ( M3)) /* gpio_40 */ \
767 MV(CP(GPMC_A17) , ( PTD | M3)) /* gpio_41 */ \
768 MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \
769 MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \
770 MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \
771 MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \
772 MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \
773 MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \
774 MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \
775 MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \
776 MV(CP(GPMC_NCS0) , ( M3)) /* gpio_50 */ \
777 MV(CP(GPMC_NCS1) , ( IEN | M3)) /* gpio_51 */ \
778 MV(CP(GPMC_NCS2) , ( IEN | M3)) /* gpio_52 */ \
779 MV(CP(GPMC_NCS3) , ( IEN | M3)) /* gpio_53 */ \
780 MV(CP(GPMC_NWP) , ( M3)) /* gpio_54 */ \
781 MV(CP(GPMC_CLK) , ( PTD | M3)) /* gpio_55 */ \
782 MV(CP(GPMC_NADV_ALE) , ( M3)) /* gpio_56 */ \
783 MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \
784 MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \
785 MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \
786 MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \
787 MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \
788 MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \
789 MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \
790 MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \
791 MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \
792 MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \
793 MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \
794 MV(CP(HDMI_HPD) , ( M0)) /* hdmi_hpd */ \
795 MV(CP(HDMI_CEC) , ( M0)) /* hdmi_cec */ \
796 MV(CP(HDMI_DDC_SCL) , ( PTU | M0)) /* hdmi_ddc_scl */ \
797 MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0)) /* hdmi_ddc_sda */ \
798 MV(CP(CSI21_DX0) , ( IEN | M0)) /* csi21_dx0 */ \
799 MV(CP(CSI21_DY0) , ( IEN | M0)) /* csi21_dy0 */ \
800 MV(CP(CSI21_DX1) , ( IEN | M0)) /* csi21_dx1 */ \
801 MV(CP(CSI21_DY1) , ( IEN | M0)) /* csi21_dy1 */ \
802 MV(CP(CSI21_DX2) , ( IEN | M0)) /* csi21_dx2 */ \
803 MV(CP(CSI21_DY2) , ( IEN | M0)) /* csi21_dy2 */ \
804 MV(CP(CSI21_DX3) , ( PTD | M7)) /* csi21_dx3 */ \
805 MV(CP(CSI21_DY3) , ( PTD | M7)) /* csi21_dy3 */ \
806 MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dx4 */ \
807 MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dy4 */ \
808 MV(CP(CSI22_DX0) , ( IEN | M0)) /* csi22_dx0 */ \
809 MV(CP(CSI22_DY0) , ( IEN | M0)) /* csi22_dy0 */ \
810 MV(CP(CSI22_DX1) , ( IEN | M0)) /* csi22_dx1 */ \
811 MV(CP(CSI22_DY1) , ( IEN | M0)) /* csi22_dy1 */ \
812 MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \
813 MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \
814 MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \
815 MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \
816 MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \
817 MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \
818 MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \
819 MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \
820 MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \
821 MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \
822 MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \
823 MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \
824 MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \
825 MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \
826 MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \
827 MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \
828 MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \
829 MV(CP(USBC1_ICUSB_DP) , ( IEN | M0)) /* usbc1_icusb_dp */ \
830 MV(CP(USBC1_ICUSB_DM) , ( IEN | M0)) /* usbc1_icusb_dm */ \
831 MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \
832 MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \
833 MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \
834 MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \
835 MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \
836 MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \
837 MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \
838 MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \
839 MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \
840 MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \
841 MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \
842 MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \
843 MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \
844 MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \
845 MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1)) /* abe_slimbus1_clock */ \
846 MV(CP(ABE_MCBSP1_DR) , ( IEN | M1)) /* abe_slimbus1_data */ \
847 MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \
848 MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \
849 MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_ul_data */ \
850 MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_dl_data */ \
851 MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_frame */ \
852 MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_lb_clk */ \
853 MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_clks */ \
854 MV(CP(ABE_DMIC_CLK1) , ( M0)) /* abe_dmic_clk1 */ \
855 MV(CP(ABE_DMIC_DIN1) , ( IEN | M0)) /* abe_dmic_din1 */ \
856 MV(CP(ABE_DMIC_DIN2) , ( IEN | M0)) /* abe_dmic_din2 */ \
857 MV(CP(ABE_DMIC_DIN3) , ( IEN | M0)) /* abe_dmic_din3 */ \
858 MV(CP(UART2_CTS) , ( PTU | IEN | M0)) /* uart2_cts */ \
859 MV(CP(UART2_RTS) , ( M0)) /* uart2_rts */ \
860 MV(CP(UART2_RX) , ( PTU | IEN | M0)) /* uart2_rx */ \
861 MV(CP(UART2_TX) , ( M0)) /* uart2_tx */ \
862 MV(CP(HDQ_SIO) , ( M3)) /* gpio_127 */ \
863 MV(CP(I2C1_SCL) , ( PTU | IEN | M0)) /* i2c1_scl */ \
864 MV(CP(I2C1_SDA) , ( PTU | IEN | M0)) /* i2c1_sda */ \
865 MV(CP(I2C2_SCL) , ( PTU | IEN | M0)) /* i2c2_scl */ \
866 MV(CP(I2C2_SDA) , ( PTU | IEN | M0)) /* i2c2_sda */ \
867 MV(CP(I2C3_SCL) , ( PTU | IEN | M0)) /* i2c3_scl */ \
868 MV(CP(I2C3_SDA) , ( PTU | IEN | M0)) /* i2c3_sda */ \
869 MV(CP(I2C4_SCL) , ( PTU | IEN | M0)) /* i2c4_scl */ \
870 MV(CP(I2C4_SDA) , ( PTU | IEN | M0)) /* i2c4_sda */ \
871 MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \
872 MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \
873 MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \
874 MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \
875 MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* mcspi1_cs1 */ \
876 MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \
877 MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3)) /* gpio_140 */ \
878 MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0)) /* uart3_tx */ \
879 MV(CP(UART3_RTS_SD) , ( M0)) /* uart3_rts_sd */ \
880 MV(CP(UART3_RX_IRRX) , ( IEN | M0)) /* uart3_rx */ \
881 MV(CP(UART3_TX_IRTX) , ( M0)) /* uart3_tx */ \
882 MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \
883 MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \
884 MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \
885 MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \
886 MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \
887 MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \
888 MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \
889 MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \
890 MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \
891 MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
892 MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \
893 MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \
894 MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \
895 MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \
896 MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \
897 MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \
898 MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5)) /* dispc2_data20 */ \
899 MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5)) /* dispc2_data19 */ \
900 MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5)) /* dispc2_data18 */ \
901 MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5)) /* dispc2_data15 */ \
902 MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5)) /* dispc2_data14 */ \
903 MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5)) /* dispc2_data13 */ \
904 MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5)) /* dispc2_data12 */ \
905 MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \
906 MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \
907 MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \
908 MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \
909 MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \
910 MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \
911 MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \
912 MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \
913 MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \
914 MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \
915 MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \
916 MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \
917 MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \
918 MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \
919 MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \
920 MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \
921 MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \
922 MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \
923 MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \
924 MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \
925 MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \
926 MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \
927 MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
928 MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \
929 MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \
930 MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \
931 MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \
932 MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \
933 MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \
934 MV(CP(DPM_EMU1) , ( IEN | M0)) /* dpm_emu1 */ \
935 MV(CP(DPM_EMU2) , ( IEN | M0)) /* dpm_emu2 */ \
936 MV(CP(DPM_EMU3) , ( IEN | M5)) /* dispc2_data10 */ \
937 MV(CP(DPM_EMU4) , ( IEN | M5)) /* dispc2_data9 */ \
938 MV(CP(DPM_EMU5) , ( IEN | M5)) /* dispc2_data16 */ \
939 MV(CP(DPM_EMU6) , ( IEN | M5)) /* dispc2_data17 */ \
940 MV(CP(DPM_EMU7) , ( IEN | M5)) /* dispc2_hsync */ \
941 MV(CP(DPM_EMU8) , ( IEN | M5)) /* dispc2_pclk */ \
942 MV(CP(DPM_EMU9) , ( IEN | M5)) /* dispc2_vsync */ \
943 MV(CP(DPM_EMU10) , ( IEN | M5)) /* dispc2_de */ \
944 MV(CP(DPM_EMU11) , ( IEN | M5)) /* dispc2_data8 */ \
945 MV(CP(DPM_EMU12) , ( IEN | M5)) /* dispc2_data7 */ \
946 MV(CP(DPM_EMU13) , ( IEN | M5)) /* dispc2_data6 */ \
947 MV(CP(DPM_EMU14) , ( IEN | M5)) /* dispc2_data5 */ \
948 MV(CP(DPM_EMU15) , ( IEN | M5)) /* dispc2_data4 */ \
949 MV(CP(DPM_EMU16) , ( M3)) /* gpio_27 */ \
950 MV(CP(DPM_EMU17) , ( IEN | M5)) /* dispc2_data2 */ \
951 MV(CP(DPM_EMU18) , ( IEN | M5)) /* dispc2_data1 */ \
952 MV(CP(DPM_EMU19) , ( IEN | M5)) /* dispc2_data0 */ \
953 MV1(WK(PAD0_SIM_IO) , ( IEN | M0)) /* sim_io */ \
954 MV1(WK(PAD1_SIM_CLK) , ( M0)) /* sim_clk */ \
955 MV1(WK(PAD0_SIM_RESET) , ( M0)) /* sim_reset */ \
956 MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0)) /* sim_cd */ \
957 MV1(WK(PAD0_SIM_PWRCTRL) , ( M0)) /* sim_pwrctrl */ \
958 MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0)) /* sr_scl */ \
959 MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0)) /* sr_sda */ \
960 MV1(WK(PAD1_FREF_XTAL_IN) , ( M0)) /* # */ \
961 MV1(WK(PAD0_FREF_SLICER_IN) , ( M0)) /* fref_slicer_in */ \
962 MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0)) /* fref_clk_ioreq */ \
963 MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2)) /* sys_drm_msecure */ \
964 MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0)) /* # */ \
965 MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0)) /* fref_clk3_out */ \
966 MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0)) /* # */ \
967 MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0)) /* # */ \
968 MV1(WK(PAD1_SYS_32K) , ( IEN | M0)) /* sys_32k */ \
969 MV1(WK(PAD0_SYS_NRESPWRON) , ( M0)) /* sys_nrespwron */ \
970 MV1(WK(PAD1_SYS_NRESWARM) , ( M0)) /* sys_nreswarm */ \
971 MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0)) /* sys_pwr_req */ \
972 MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \
973 MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \
974 MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \
975 MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \
976 MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \
977 MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */
979 /**********************************************************
980 * Routine: set_muxconf_regs
981 * Description: Setting up the configuration Mux registers
982 * specific to the hardware. Many pins need
983 * to be moved from protect to primary mode.
984 *********************************************************/
985 void set_muxconf_regs(void)
990 /******************************************************************************
991 * Routine: update_mux()
992 * Description:Update balls which are different between boards. All should be
993 * updated to match functionality. However, I'm only updating ones
994 * which I'll be using for now. When power comes into play they
996 *****************************************************************************/
997 void update_mux(u32 btype, u32 mtype)
1002 /* optionally do something like blinking LED */
1003 void board_hang(void)