omap4430panda: enable clock gating for M6_DPLL_CORE

omap4430panda: enable clock gating for M6_DPLL_CORE

The M6 clock from the core DPLL supplies a clock to the debug domain.
After the core DPLL is locked, the M6 clock appears to stop if clock
gating has been *disabled* for that output (reason unknown).  This
breaks JTAG debugging.

This patch enables clock gating on M6_DPLL_CORE before locking the
core DPLL, so the debugger continues to work.

Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>