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(parent: b988b8c) | patch
TQM885D: Exchanged SDRAM timing by a more relaxed timing.
authorJens Gehrlein <jens.gehrlein@tqs.de>
Wed, 26 Sep 2007 15:55:54 +0000 (17:55 +0200)
committerWolfgang Denk <wd@denx.de>
Thu, 27 Dec 2007 00:59:50 +0000 (01:59 +0100)
commit22d1a56cbfb0bff34f477b4db6a55d076d829b83
treeb8206a0016a00d0d13564b2ff22c080cadf9f762tree | snapshot
parentb988b8cd443989be65161888eea0127ad03f846fcommit | diff
TQM885D: Exchanged SDRAM timing by a more relaxed timing.

CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.

Signed-off-by: Martin Krause <martin.krause@tqs.de>
board/tqm8xx/tqm8xx.c diff | blob | history
cpu/mpc8xx/speed.c diff | blob | history
include/configs/TQM885D.h diff | blob | history
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