ARM: davinci: Explicitly set channel controllers' default queues
authorIdo Yariv <ido@wizery.com>
Sun, 10 Jul 2011 13:14:35 +0000 (16:14 +0300)
committerSekhar Nori <nsekhar@ti.com>
Sat, 17 Sep 2011 10:24:08 +0000 (15:54 +0530)
Davinci platforms may define a default queue for each channel
controller. If one is not defined, the default queue is set to EVENTQ_1.
However, there's no way to distinguish between an unset default queue to
one that is set to EVENTQ_0, as EVENTQ_0 = 0.

Explicitly specify the default queue for all channel controllers on all
Davinci platforms to EVENTQ_1, and don't overwrite it in the EDMA probe
function.

One exception is the DA850 board, for which EVENTQ_1 is not a valid
option for its second channel controller. Use EVENTQ_0 instead for that
channel controller.

Signed-off-by: Ido Yariv <ido@wizery.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arch/arm/mach-davinci/devices-da8xx.c
arch/arm/mach-davinci/devices-tnetv107x.c
arch/arm/mach-davinci/dm355.c
arch/arm/mach-davinci/dm644x.c
arch/arm/mach-davinci/dm646x.c
arch/arm/mach-davinci/dma.c

index 2f7e719..68def71 100644 (file)
@@ -136,6 +136,7 @@ static struct edma_soc_info da830_edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = da8xx_queue_tc_mapping,
        .queue_priority_mapping = da8xx_queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
@@ -151,6 +152,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da8xx_queue_tc_mapping,
                .queue_priority_mapping = da8xx_queue_priority_mapping,
+               .default_queue          = EVENTQ_1,
        },
        {
                .n_channel              = 32,
@@ -160,6 +162,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da850_queue_tc_mapping,
                .queue_priority_mapping = da850_queue_priority_mapping,
+               .default_queue          = EVENTQ_0,
        },
 };
 
index 6162cae..29b17f7 100644 (file)
@@ -80,6 +80,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = edma_tc_mapping,
        .queue_priority_mapping = edma_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
index a3a94e9..68fb181 100644 (file)
@@ -591,6 +591,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
index 4c82c27..555ff5b 100644 (file)
@@ -514,6 +514,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
index 1802e71..b0c350a 100644 (file)
@@ -555,6 +555,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = dm646x_queue_tc_mapping,
        .queue_priority_mapping = dm646x_queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
index 6b96698..6ba4191 100644 (file)
@@ -1450,8 +1450,6 @@ static int __init edma_probe(struct platform_device *pdev)
                                                        EDMA_MAX_CC);
 
                edma_cc[j]->default_queue = info[j]->default_queue;
-               if (!edma_cc[j]->default_queue)
-                       edma_cc[j]->default_queue = EVENTQ_1;
 
                dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
                        edmacc_regs_base[j]);