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ARM: Improve the L2 cache performance when PL310 is used
authorCatalin Marinas <catalin.marinas@arm.com>
Tue, 31 Aug 2010 12:05:22 +0000 (13:05 +0100)
committerSantosh Shilimkar <santosh.shilimkar@ti.com>
Tue, 26 Oct 2010 06:09:54 +0000 (11:39 +0530)
With this L2 cache controller, the cache maintenance by PA and sync
operations are atomic and do not require a "wait" loop. This patch
conditionally defines the cache_wait() function.

Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
automatically enables CACHE_PL310 when only CPU_V7 is defined.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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