Merge commit 'origin/master' into next
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 17 Jun 2009 00:24:53 +0000 (10:24 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 17 Jun 2009 00:24:53 +0000 (10:24 +1000)
67 files changed:
arch/powerpc/Kconfig.debug
arch/powerpc/boot/cuboot-85xx.c
arch/powerpc/boot/dts/asp834x-redboot.dts
arch/powerpc/boot/dts/gef_sbc610.dts
arch/powerpc/boot/dts/kmeter1.dts [new file with mode: 0644]
arch/powerpc/boot/dts/mpc8272ads.dts
arch/powerpc/boot/dts/mpc8315erdb.dts
arch/powerpc/boot/dts/mpc8349emitx.dts
arch/powerpc/boot/dts/mpc834x_mds.dts
arch/powerpc/boot/dts/mpc8377_mds.dts
arch/powerpc/boot/dts/mpc8377_rdb.dts
arch/powerpc/boot/dts/mpc8378_mds.dts
arch/powerpc/boot/dts/mpc8378_rdb.dts
arch/powerpc/boot/dts/mpc8379_mds.dts
arch/powerpc/boot/dts/mpc8379_rdb.dts
arch/powerpc/boot/dts/mpc8569mds.dts
arch/powerpc/boot/dts/sbc8349.dts
arch/powerpc/boot/dts/xcalibur1501.dts [new file with mode: 0644]
arch/powerpc/boot/dts/xpedite5200.dts [new file with mode: 0644]
arch/powerpc/boot/dts/xpedite5200_xmon.dts [new file with mode: 0644]
arch/powerpc/boot/dts/xpedite5301.dts [new file with mode: 0644]
arch/powerpc/boot/dts/xpedite5330.dts [new file with mode: 0644]
arch/powerpc/boot/dts/xpedite5370.dts [new file with mode: 0644]
arch/powerpc/boot/wrapper
arch/powerpc/configs/83xx/kmeter1_defconfig [new file with mode: 0644]
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig [new file with mode: 0644]
arch/powerpc/include/asm/delay.h
arch/powerpc/include/asm/fsl_lbc.h
arch/powerpc/include/asm/reg.h
arch/powerpc/include/asm/reg_booke.h
arch/powerpc/kernel/Makefile
arch/powerpc/kernel/cpu_setup_6xx.S
arch/powerpc/kernel/cpu_setup_fsl_booke.S
arch/powerpc/kvm/Makefile
arch/powerpc/lib/Makefile
arch/powerpc/mm/Makefile
arch/powerpc/oprofile/Makefile
arch/powerpc/platforms/44x/warp.c
arch/powerpc/platforms/83xx/Kconfig
arch/powerpc/platforms/83xx/Makefile
arch/powerpc/platforms/83xx/kmeter1.c [new file with mode: 0644]
arch/powerpc/platforms/83xx/mpc83xx.h
arch/powerpc/platforms/83xx/usb.c
arch/powerpc/platforms/85xx/Kconfig
arch/powerpc/platforms/85xx/Makefile
arch/powerpc/platforms/85xx/mpc8536_ds.c
arch/powerpc/platforms/85xx/mpc85xx_ds.c
arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/powerpc/platforms/85xx/xes_mpc85xx.c [new file with mode: 0644]
arch/powerpc/platforms/86xx/Kconfig
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
arch/powerpc/platforms/Kconfig.cputype
arch/powerpc/platforms/Makefile
arch/powerpc/sysdev/Makefile
arch/powerpc/xmon/Makefile
drivers/char/hvc_iseries.c
drivers/char/hvc_vio.c
drivers/char/hvcs.c
drivers/net/ps3_gelic_net.c
drivers/net/ps3_gelic_wireless.c
drivers/rapidio/rio-scan.c
drivers/rapidio/rio-sysfs.c
drivers/scsi/ps3rom.c
drivers/serial/of_serial.c
drivers/serial/ucc_uart.c
drivers/usb/host/ehci-ps3.c
drivers/usb/host/ohci-ps3.c

index d79a902..3b10051 100644 (file)
@@ -2,6 +2,23 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
+config PPC_DISABLE_WERROR
+       bool "Don't build arch/powerpc code with -Werror"
+       default n
+       help
+         This option tells the compiler NOT to build the code under
+         arch/powerpc with the -Werror flag (which means warnings
+         are treated as errors).
+
+         Only enable this if you are hitting a build failure in the
+         arch/powerpc code caused by a warning, and you don't feel
+         inclined to fix it.
+
+config PPC_WERROR
+       bool
+       depends on !PPC_DISABLE_WERROR
+       default y
+
 config PRINT_STACK_DEPTH
        int "Stack depth to print" if DEBUG_KERNEL
        default 64
index 6776a1a..277ba4a 100644 (file)
@@ -15,6 +15,7 @@
 #include "cuboot.h"
 
 #define TARGET_85xx
+#define TARGET_HAS_ETH3
 #include "ppcboot.h"
 
 static bd_t bd;
@@ -27,6 +28,7 @@ static void platform_fixups(void)
        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
        dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
+       dt_fixup_mac_address_by_alias("ethernet3", bd.bi_enet3addr);
        dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
 
        /* Unfortunately, the specific model number is encoded in the
index 7da84fd..261d10c 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                usb@23000 {
index 217f8aa..35a6318 100644 (file)
                        interrupt-parent = <&mpic>;
                        dfsrr;
 
+                       hwmon@48 {
+                               compatible = "national,lm92";
+                               reg = <0x48>;
+                       };
+
+                       hwmon@4c {
+                               compatible = "adi,adt7461";
+                               reg = <0x4c>;
+                       };
+
                        rtc@51 {
                                compatible = "epson,rx8581";
                                reg = <0x00000051>;
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
new file mode 100644 (file)
index 0000000..167044f
--- /dev/null
@@ -0,0 +1,520 @@
+/*
+ * Keymile KMETER1 Device Tree Source
+ *
+ * 2008 DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+       model = "KMETER1";
+       compatible = "keymile,KMETER1";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       aliases {
+               ethernet0 = &enet_piggy2;
+               ethernet1 = &enet_estar1;
+               ethernet2 = &enet_estar2;
+               ethernet3 = &enet_eth1;
+               ethernet4 = &enet_eth2;
+               ethernet5 = &enet_eth3;
+               ethernet6 = &enet_eth4;
+               serial0 = &serial0;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8360@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <32768>;         // L1, 32K
+                       i-cache-size = <32768>;         // L1, 32K
+                       timebase-frequency = <0>;       /* Filled in by U-Boot */
+                       bus-frequency = <0>;    /* Filled in by U-Boot */
+                       clock-frequency = <0>;  /* Filled in by U-Boot */
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0>;    /* Filled in by U-Boot */
+       };
+
+       soc8360@e0000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,mpc8360-immr", "simple-bus";
+               ranges = <0x0 0xe0000000 0x00200000>;
+               reg = <0xe0000000 0x00000200>;
+               bus-frequency = <0>;    /* Filled in by U-Boot */
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <14 0x8>;
+                       interrupt-parent = <&ipic>;
+                       dfsrr;
+               };
+
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <264000000>;
+                       interrupts = <9 0x8>;
+                       interrupt-parent = <&ipic>;
+               };
+
+               dma@82a8 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
+                       reg = <0x82a8 4>;
+                       ranges = <0 0x8100 0x1a8>;
+                       interrupt-parent = <&ipic>;
+                       interrupts = <71 8>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+                               reg = <0 0x80>;
+                               interrupt-parent = <&ipic>;
+                               interrupts = <71 8>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+                               reg = <0x80 0x80>;
+                               interrupt-parent = <&ipic>;
+                               interrupts = <71 8>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+                               reg = <0x100 0x80>;
+                               interrupt-parent = <&ipic>;
+                               interrupts = <71 8>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+                               reg = <0x180 0x28>;
+                               interrupt-parent = <&ipic>;
+                               interrupts = <71 8>;
+                       };
+               };
+
+               ipic: pic@700 {
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       compatible = "fsl,pq2pro-pic", "fsl,ipic";
+                       interrupt-controller;
+                       reg = <0x700 0x100>;
+               };
+
+               par_io@1400 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x1400 0x100>;
+                       compatible = "fsl,mpc8360-par_io";
+                       num-ports = <7>;
+
+                       pio_ucc1: ucc_pin@0 {
+                               reg = <0>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO   */
+                                       0   2  1  0  1  0       /* MDC    */
+
+                                       0   3  1  0  1  0       /* TxD0   */
+                                       0   4  1  0  1  0       /* TxD1   */
+                                       0   5  1  0  1  0       /* TxD2   */
+                                       0   6  1  0  1  0       /* TxD3   */
+                                       0   9  2  0  1  0       /* RxD0   */
+                                       0  10  2  0  1  0       /* RxD1   */
+                                       0  11  2  0  1  0       /* RxD2   */
+                                       0  12  2  0  1  0       /* RxD3   */
+                                       0   7  1  0  1  0       /* TX_EN  */
+                                       0   8  1  0  1  0       /* TX_ER  */
+                                       0  15  2  0  1  0       /* RX_DV  */
+                                       0  16  2  0  1  0       /* RX_ER  */
+                                       0   0  2  0  1  0       /* RX_CLK */
+                                       2   9  1  0  3  0       /* GTX_CLK - CLK10 */
+                                       2   8  2  0  1  0       /* GTX125  - CLK9  */
+                               >;
+                       };
+
+                       pio_ucc2: ucc_pin@1 {
+                               reg = <1>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO   */
+                                       0   2  1  0  1  0       /* MDC    */
+
+                                       0  17  1  0  1  0       /* TxD0   */
+                                       0  18  1  0  1  0       /* TxD1   */
+                                       0  19  1  0  1  0       /* TxD2   */
+                                       0  20  1  0  1  0       /* TxD3   */
+                                       0  23  2  0  1  0       /* RxD0   */
+                                       0  24  2  0  1  0       /* RxD1   */
+                                       0  25  2  0  1  0       /* RxD2   */
+                                       0  26  2  0  1  0       /* RxD3   */
+                                       0  21  1  0  1  0       /* TX_EN  */
+                                       0  22  1  0  1  0       /* TX_ER  */
+                                       0  29  2  0  1  0       /* RX_DV  */
+                                       0  30  2  0  1  0       /* RX_ER  */
+                                       0  31  2  0  1  0       /* RX_CLK */
+                                       2  2   1  0  2  0       /* GTX_CLK - CLK3  */
+                                       2  3   2  0  1  0       /* GTX125  - CLK4  */
+                               >;
+                       };
+
+                       pio_ucc4: ucc_pin@3 {
+                               reg = <3>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO */
+                                       0   2  1  0  1  0       /* MDC  */
+
+                                       1  14  1  0  1  0       /* TxD0   (PB14, out, f1) */
+                                       1  15  1  0  1  0       /* TxD1   (PB15, out, f1) */
+                                       1  20  2  0  1  0       /* RxD0   (PB20, in,  f1) */
+                                       1  21  2  0  1  0       /* RxD1   (PB21, in,  f1) */
+                                       1  18  1  0  1  0       /* TX_EN  (PB18, out, f1) */
+                                       1  26  2  0  1  0       /* RX_DV  (PB26, in,  f1) */
+                                       1  27  2  0  1  0       /* RX_ER  (PB27, in,  f1) */
+
+                                       2  16  2  0  1  0       /* UCC4_RMII_CLK (CLK17) */
+                               >;
+                       };
+
+                       pio_ucc5: ucc_pin@4 {
+                               reg = <4>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO */
+                                       0   2  1  0  1  0       /* MDC  */
+
+                                       3   0  1  0  1  0       /* TxD0  (PD0,  out, f1) */
+                                       3   1  1  0  1  0       /* TxD1  (PD1,  out, f1) */
+                                       3   6  2  0  1  0       /* RxD0  (PD6,   in, f1) */
+                                       3   7  2  0  1  0       /* RxD1  (PD7,   in, f1) */
+                                       3   4  1  0  1  0       /* TX_EN (PD4,  out, f1) */
+                                       3  12  2  0  1  0       /* RX_DV (PD12,  in, f1) */
+                                       3  13  2  0  1  0       /* RX_ER (PD13,  in, f1) */
+                               >;
+                       };
+
+                       pio_ucc6: ucc_pin@5 {
+                               reg = <5>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO */
+                                       0   2  1  0  1  0       /* MDC  */
+
+                                       3  14  1  0  1  0       /* TxD0   (PD14, out, f1) */
+                                       3  15  1  0  1  0       /* TxD1   (PD15, out, f1) */
+                                       3  20  2  0  1  0       /* RxD0   (PD20, in,  f1) */
+                                       3  21  2  0  1  0       /* RxD1   (PD21, in,  f1) */
+                                       3  18  1  0  1  0       /* TX_EN  (PD18, out, f1) */
+                                       3  26  2  0  1  0       /* RX_DV  (PD26, in,  f1) */
+                                       3  27  2  0  1  0       /* RX_ER  (PD27, in,  f1) */
+                               >;
+                       };
+
+                       pio_ucc7: ucc_pin@6 {
+                               reg = <6>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO */
+                                       0   2  1  0  1  0       /* MDC  */
+
+                                       4   0  1  0  1  0       /* TxD0   (PE0,  out, f1) */
+                                       4   1  1  0  1  0       /* TxD1   (PE1,  out, f1) */
+                                       4   6  2  0  1  0       /* RxD0   (PE6,   in, f1) */
+                                       4   7  2  0  1  0       /* RxD1   (PE7,   in, f1) */
+                                       4   4  1  0  1  0       /* TX_EN  (PE4,  out, f1) */
+                                       4  12  2  0  1  0       /* RX_DV  (PE12,  in, f1) */
+                                       4  13  2  0  1  0       /* RX_ER  (PE13,  in, f1) */
+                               >;
+                       };
+
+                       pio_ucc8: ucc_pin@7 {
+                               reg = <7>;
+
+                               pio-map = <
+                                       /* port pin dir open_drain assignment has_irq */
+                                       0   1  3  0  2  0       /* MDIO */
+                                       0   2  1  0  1  0       /* MDC  */
+
+                                       4  14  1  0  2  0       /* TxD0   (PE14, out, f2) */
+                                       4  15  1  0  1  0       /* TxD1   (PE15, out, f1) */
+                                       4  20  2  0  1  0       /* RxD0   (PE20, in,  f1) */
+                                       4  21  2  0  1  0       /* RxD1   (PE21, in,  f1) */
+                                       4  18  1  0  1  0       /* TX_EN  (PE18, out, f1) */
+                                       4  26  2  0  1  0       /* RX_DV  (PE26, in,  f1) */
+                                       4  27  2  0  1  0       /* RX_ER  (PE27, in,  f1) */
+
+                                       2  15  2  0  1  0       /* UCCx_RMII_CLK (CLK16) */
+                               >;
+                       };
+
+               };
+
+               qe@100000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,qe";
+                       ranges = <0x0 0x100000 0x100000>;
+                       reg = <0x100000 0x480>;
+                       clock-frequency = <0>;  /* Filled in by U-Boot */
+                       brg-frequency = <0>;    /* Filled in by U-Boot */
+                       bus-frequency = <0>;    /* Filled in by U-Boot */
+
+                       muram@10000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "fsl,qe-muram", "fsl,cpm-muram";
+                               ranges = <0x0 0x00010000 0x0000c000>;
+
+                               data-only@0 {
+                                       compatible = "fsl,qe-muram-data",
+                                                    "fsl,cpm-muram-data";
+                                       reg = <0x0 0xc000>;
+                               };
+                       };
+
+                       /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+                       enet_estar1: ucc@2000 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <1>;
+                               reg = <0x2000 0x200>;
+                               interrupts = <32>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk9";
+                               phy-handle = <&phy_estar1>;
+                               phy-connection-type = "rgmii-id";
+                               pio-handle = <&pio_ucc1>;
+                       };
+
+                       /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+                       enet_estar2: ucc@3000 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <2>;
+                               reg = <0x3000 0x200>;
+                               interrupts = <33>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk4";
+                               phy-handle = <&phy_estar2>;
+                               phy-connection-type = "rgmii-id";
+                               pio-handle = <&pio_ucc2>;
+                       };
+
+                       /* Piggy2 (UCC4, MDIO 0x00, RMII) */
+                       enet_piggy2: ucc@3200 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <4>;
+                               reg = <0x3200 0x200>;
+                               interrupts = <35>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk17";
+                               phy-handle = <&phy_piggy2>;
+                               phy-connection-type = "rmii";
+                               pio-handle = <&pio_ucc4>;
+                       };
+
+                       /* Eth-1 (UCC5, MDIO 0x08, RMII) */
+                       enet_eth1: ucc@2400 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <5>;
+                               reg = <0x2400 0x200>;
+                               interrupts = <40>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk16";
+                               phy-handle = <&phy_eth1>;
+                               phy-connection-type = "rmii";
+                               pio-handle = <&pio_ucc5>;
+                       };
+
+                       /* Eth-2 (UCC6, MDIO 0x09, RMII) */
+                       enet_eth2: ucc@3400 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <6>;
+                               reg = <0x3400 0x200>;
+                               interrupts = <41>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk16";
+                               phy-handle = <&phy_eth2>;
+                               phy-connection-type = "rmii";
+                               pio-handle = <&pio_ucc6>;
+                       };
+
+                       /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+                       enet_eth3: ucc@2600 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <7>;
+                               reg = <0x2600 0x200>;
+                               interrupts = <42>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk16";
+                               phy-handle = <&phy_eth3>;
+                               phy-connection-type = "rmii";
+                               pio-handle = <&pio_ucc7>;
+                       };
+
+                       /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+                       enet_eth4: ucc@3600 {
+                               device_type = "network";
+                               compatible = "ucc_geth";
+                               cell-index = <8>;
+                               reg = <0x3600 0x200>;
+                               interrupts = <43>;
+                               interrupt-parent = <&qeic>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               rx-clock-name = "none";
+                               tx-clock-name = "clk16";
+                               phy-handle = <&phy_eth4>;
+                               phy-connection-type = "rmii";
+                               pio-handle = <&pio_ucc8>;
+                       };
+
+                       mdio@3320 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x3320 0x18>;
+                               compatible = "fsl,ucc-mdio";
+
+                               /* Piggy2 (UCC4, MDIO 0x00, RMII) */
+                               phy_piggy2: ethernet-phy@00 {
+                                       reg = <0x0>;
+                               };
+
+                               /* Eth-1 (UCC5, MDIO 0x08, RMII) */
+                               phy_eth1: ethernet-phy@08 {
+                                       reg = <0x08>;
+                               };
+
+                               /* Eth-2 (UCC6, MDIO 0x09, RMII) */
+                               phy_eth2: ethernet-phy@09 {
+                                       reg = <0x09>;
+                               };
+
+                               /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+                               phy_eth3: ethernet-phy@0a {
+                                       reg = <0x0a>;
+                               };
+
+                               /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+                               phy_eth4: ethernet-phy@0b {
+                                       reg = <0x0b>;
+                               };
+
+                               /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+                               phy_estar1: ethernet-phy@10 {
+                                       interrupt-parent = <&ipic>;
+                                       interrupts = <17 0x8>;
+                                       reg = <0x10>;
+                               };
+
+                               /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+                               phy_estar2: ethernet-phy@11 {
+                                       interrupt-parent = <&ipic>;
+                                       interrupts = <18 0x8>;
+                                       reg = <0x11>;
+                               };
+                       };
+
+                       qeic: interrupt-controller@80 {
+                               interrupt-controller;
+                               compatible = "fsl,qe-ic";
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               reg = <0x80 0x80>;
+                               interrupts = <32 8 33 8>;
+                               interrupt-parent = <&ipic>;
+                       };
+               };
+       };
+
+       localbus@e0005000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
+                            "simple-bus";
+               reg = <0xe0005000 0xd8>;
+               ranges = <0 0 0xf0000000 0x04000000>;   /* Filled in by U-Boot */
+
+               flash@f0000000,0 {
+                       compatible = "cfi-flash";
+                       /*
+                        * The Intel P30 chip has 2 non-identical chips on
+                        * one die, so we need to define 2 seperate regions
+                        * that are scanned by physmap_of independantly.
+                        */
+                       reg = <0 0x00000000 0x02000000
+                              0 0x02000000 0x02000000>;        /* Filled in by U-Boot */
+                       bank-width = <2>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "u-boot";
+                               reg = <0 0x40000>;
+                       };
+                       partition@40000 {
+                               label = "env";
+                               reg = <0x40000 0x40000>;
+                       };
+                       partition@80000 {
+                               label = "dtb";
+                               reg = <0x80000 0x20000>;
+                       };
+                       partition@a0000 {
+                               label = "kernel";
+                               reg = <0xa0000 0x300000>;
+                       };
+                       partition@3a0000 {
+                               label = "ramdisk";
+                               reg = <0x3a0000 0x800000>;
+                       };
+                       partition@ba0000 {
+                               label = "user";
+                               reg = <0xba0000 0x3460000>;
+                       };
+               };
+       };
+};
index 2a1929a..60f3327 100644 (file)
        #address-cells = <1>;
        #size-cells = <1>;
 
+       aliases {
+               ethernet0 = &eth0;
+               ethernet1 = &eth1;
+               serial0 = &scc1;
+               serial1 = &scc4;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                #size-cells = <1>;
                reg = <0xf0010100 0x40>;
 
-               ranges = <0x0 0x0 0xfe000000 0x2000000
+               ranges = <0x0 0x0 0xff800000 0x00800000
                          0x1 0x0 0xf4500000 0x8000
                          0x3 0x0 0xf8200000 0x8000>;
 
                flash@0,0 {
                        compatible = "jedec-flash";
-                       reg = <0x0 0x0 0x2000000>;
+                       reg = <0x0 0x0 0x00800000>;
                        bank-width = <4>;
                        device-width = <1>;
                };
                                reg = <0x119f0 0x10 0x115f0 0x10>;
                        };
 
-                       serial@11a00 {
+                       scc1: serial@11a00 {
                                device_type = "serial";
                                compatible = "fsl,mpc8272-scc-uart",
                                             "fsl,cpm2-scc-uart";
                                fsl,cpm-command = <0x800000>;
                        };
 
-                       serial@11a60 {
+                       scc4: serial@11a60 {
                                device_type = "serial";
                                compatible = "fsl,mpc8272-scc-uart",
                                             "fsl,cpm2-scc-uart";
                                };
                        };
 
-                       ethernet@11300 {
+                       eth0: ethernet@11300 {
                                device_type = "network";
                                compatible = "fsl,mpc8272-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
                                fsl,cpm-command = <0x12000300>;
                        };
 
-                       ethernet@11320 {
+                       eth1: ethernet@11320 {
                                device_type = "network";
                                compatible = "fsl,mpc8272-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
index 3f4c5fb..32e10f5 100644 (file)
                        reg = <0x700 0x100>;
                        device_type = "ipic";
                };
+
+               ipic-msi@7c0 {
+                       compatible = "fsl,ipic-msi";
+                       reg = <0x7c0 0x40>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <0x43 0x8
+                                     0x4  0x8
+                                     0x51 0x8
+                                     0x52 0x8
+                                     0x56 0x8
+                                     0x57 0x8
+                                     0x58 0x8
+                                     0x59 0x8>;
+                       interrupt-parent = < &ipic >;
+               };
        };
 
        pci0: pci@e0008500 {
index e3eeaed..feeeb7f 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
 
                usb@23000 {
index a2553a6..230febb 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                usb@23000 {
index 67bb372..f32c281 100644 (file)
                        };
 
                        sdhci@2e000 {
-                               compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
+                               compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
                                reg = <0x2e000 0x1000>;
                                interrupts = <42 0x8>;
                                interrupt-parent = <&ipic>;
index 0533393..224b4f0 100644 (file)
                        };
 
                        sdhci@2e000 {
-                               compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
+                               compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
                                reg = <0x2e000 0x1000>;
                                interrupts = <42 0x8>;
                                interrupt-parent = <&ipic>;
index a955a57..f720ab9 100644 (file)
                        };
 
                        sdhci@2e000 {
-                               compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
+                               compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
                                reg = <0x2e000 0x1000>;
                                interrupts = <42 0x8>;
                                interrupt-parent = <&ipic>;
index 5d90e85..474ea2f 100644 (file)
                        };
 
                        sdhci@2e000 {
-                               compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
+                               compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
                                reg = <0x2e000 0x1000>;
                                interrupts = <42 0x8>;
                                interrupt-parent = <&ipic>;
index d266ddb..4fa221f 100644 (file)
                        };
 
                        sdhci@2e000 {
-                               compatible = "fsl,mpc8379-esdhc";
+                               compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
                                reg = <0x2e000 0x1000>;
                                interrupts = <42 0x8>;
                                interrupt-parent = <&ipic>;
index 98ae95b..d4838af 100644 (file)
                        };
 
                        sdhci@2e000 {
-                               compatible = "fsl,mpc8379-esdhc";
+                               compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
                                reg = <0x2e000 0x1000>;
                                interrupts = <42 0x8>;
                                interrupt-parent = <&ipic>;
index 39c2927..a8dcb01 100644 (file)
@@ -24,6 +24,8 @@
                ethernet1 = &enet1;
                ethernet2 = &enet2;
                ethernet3 = &enet3;
+               ethernet5 = &enet5;
+               ethernet7 = &enet7;
                pci1 = &pci1;
                rapidio0 = &rio0;
        };
                        #size-cells = <1>;
                        compatible = "cfi-flash";
                        reg = <0x0 0x0 0x02000000>;
-                       bank-width = <2>;
+                       bank-width = <1>;
                        device-width = <1>;
+                       partition@0 {
+                               label = "ramdisk";
+                               reg = <0x00000000 0x01c00000>;
+                       };
+                       partition@1c00000 {
+                               label = "kernel";
+                               reg = <0x01c00000 0x002e0000>;
+                       };
+                       partiton@1ee0000 {
+                               label = "dtb";
+                               reg = <0x01ee0000 0x00020000>;
+                       };
+                       partition@1f00000 {
+                               label = "firmware";
+                               reg = <0x01f00000 0x00080000>;
+                               read-only;
+                       };
+                       partition@1f80000 {
+                               label = "u-boot";
+                               reg = <0x01f80000 0x00080000>;
+                               read-only;
+                       };
                };
 
                bcsr@1,0 {
                                reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
+                       qe_phy5: ethernet-phy@04 {
+                               interrupt-parent = <&mpic>;
+                               reg = <0x04>;
+                               device_type = "ethernet-phy";
+                       };
+                       qe_phy7: ethernet-phy@06 {
+                               interrupt-parent = <&mpic>;
+                               reg = <0x6>;
+                               device_type = "ethernet-phy";
+                       };
+               };
+               mdio@3520 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3520 0x18>;
+                       compatible = "fsl,ucc-mdio";
+
+                       tbi0: tbi-phy@15 {
+                       reg = <0x15>;
+                       device_type = "tbi-phy";
+                       };
+               };
+               mdio@3720 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3720 0x38>;
+                       compatible = "fsl,ucc-mdio";
+                       tbi1: tbi-phy@17 {
+                               reg = <0x17>;
+                               device_type = "tbi-phy";
+                       };
                };
 
                enet2: ucc@2200 {
                        phy-connection-type = "rgmii-id";
                };
 
+               enet5: ucc@3400 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       cell-index = <6>;
+                       reg = <0x3400 0x200>;
+                       interrupts = <41>;
+                       interrupt-parent = <&qeic>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       rx-clock-name = "none";
+                       tx-clock-name = "none";
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&qe_phy5>;
+                       phy-connection-type = "sgmii";
+               };
+
+               enet7: ucc@3600 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       cell-index = <8>;
+                       reg = <0x3600 0x200>;
+                       interrupts = <43>;
+                       interrupt-parent = <&qeic>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       rx-clock-name = "none";
+                       tx-clock-name = "none";
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&qe_phy7>;
+                       phy-connection-type = "sgmii";
+               };
+
                muram@10000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
index 5fb6f66..2d9fa68 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                usb@23000 {
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
new file mode 100644 (file)
index 0000000..ac0a617
--- /dev/null
@@ -0,0 +1,696 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+       model = "xes,xcalibur1501";
+       compatible = "xes,xcalibur1501", "xes,MPC8572";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               ethernet3 = &enet3;
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci2 = &pci2;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8572@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+
+               PowerPC,8572@1 {
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x0>;        // Filled in by U-Boot
+       };
+
+       localbus@ef005000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+               reg = <0 0xef005000 0 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+               /* Local bus region mappings */
+               ranges = <0 0 0 0xf8000000 0x8000000  /* CS0: Flash 1 */
+                         1 0 0 0xf0000000 0x8000000  /* CS1: Flash 2 */
+                         2 0 0 0xef800000 0x40000    /* CS2: NAND CE1 */
+                         3 0 0 0xef840000 0x40000    /* CS3: NAND CE2 */
+                         4 0 0 0xe9000000 0x100000>; /* CS4: USB */
+
+               nor-boot@0,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       reg = <0 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Primary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Primary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Primary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Primary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Primary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nor-alternate@1,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       //reg = <0xf0000000 0x08000000>; /* 128MB */
+                       reg = <1 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Secondary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Secondary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Secondary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Secondary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Secondary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       /*
+                        * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+                        * Micron MT29F8G08DAA (2x 512 MB), or Micron
+                        * MT29F16G08FAA (2x 1 GB), depending on the build
+                        * configuration
+                        */
+                       compatible = "fsl,mpc8572-fcm-nand",
+                                    "fsl,elbc-fcm-nand";
+                       reg = <2 0 0x40000>;
+                       /* U-Boot should fix this up if chip size > 1 GB */
+                       partition@0 {
+                               label = "NAND Filesystem";
+                               reg = <0 0x40000000>;
+                       };
+               };
+
+               usb@4,0 {
+                       compatible = "nxp,usb-isp1761";
+                       reg = <4 0 0x100000>;
+                       bus-width = <32>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <10 1>;
+               };
+       };
+
+       soc8572@ef000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,mpc8572-immr", "simple-bus";
+               ranges = <0x0 0 0xef000000 0x100000>;
+               bus-frequency = <0>;            // Filled out by uboot.
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               memory-controller@6000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x6000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8572-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x100000>; // L2, 1M
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       temp-sensor@48 {
+                               compatible = "dallas,ds1631", "dallas,ds1621";
+                               reg = <0x48>;
+                       };
+
+                       temp-sensor@4c {
+                               compatible = "adi,adt7461";
+                               reg = <0x4c>;
+                       };
+
+                       cpu-supervisor@51 {
+                               compatible = "dallas,ds4510";
+                               reg = <0x51>;
+                       };
+
+                       eeprom@54 {
+                               compatible = "atmel,at24c128b";
+                               reg = <0x54>;
+                       };
+
+                       rtc@68 {
+                               compatible = "stm,m41t00",
+                                            "dallas,ds1338";
+                               reg = <0x68>;
+                       };
+
+                       pcie-switch@6a {
+                               compatible = "plx,pex8648";
+                               reg = <0x6a>;
+                       };
+
+                       /* On-board signals for VID, flash, serial */
+                       gpio1: gpio@18 {
+                               compatible = "nxp,pca9557";
+                               reg = <0x18>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       /* PMC0/XMC0 signals */
+                       gpio2: gpio@1c {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1c>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       /* PMC1/XMC1 signals */
+                       gpio3: gpio@1d {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1d>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       /* CompactPCI signals (sysen, GA[4:0]) */
+                       gpio4: gpio@1e {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1e>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       /* CompactPCI J5 GPIO and FAL/DEG/PRST */
+                       gpio5: gpio@1f {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1f>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@c300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0xc300 0x4>;
+                       ranges = <0x0 0xc100 0x200>;
+                       cell-index = <1>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <76 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <77 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <78 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <79 2>;
+                       };
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               /* eTSEC 1 front panel 0 */
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <4 1>;
+                                       reg = <0x1>;
+                               };
+                               phy1: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <4 1>;
+                                       reg = <0x2>;
+                               };
+                               phy2: ethernet-phy@3 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <5 1>;
+                                       reg = <0x3>;
+                               };
+                               phy3: ethernet-phy@4 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <5 1>;
+                                       reg = <0x4>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC 2 front panel 1 */
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC 3 PICMG2.16 backplane port 0 */
+               enet2: ethernet@26000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <2>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x26000 0x1000>;
+                       ranges = <0x0 0x26000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <31 2 32 2 33 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi2>;
+                       phy-handle = <&phy2>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi2: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC 4 PICMG2.16 backplane port 1 */
+               enet3: ethernet@27000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <3>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x27000 0x1000>;
+                       ranges = <0x0 0x27000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <37 2 38 2 39 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi3>;
+                       phy-handle = <&phy3>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi3: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* UART0 */
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               /* UART1 */
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        //global utilities block
+                       compatible = "fsl,mpc8572-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               msi@41600 {
+                       compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               crypto@30000 {
+                       compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                    "fsl,sec2.1", "fsl,sec2.0";
+                       reg = <0x30000 0x10000>;
+                       interrupts = <45 2 58 2>;
+                       interrupt-parent = <&mpic>;
+                       fsl,num-channels = <4>;
+                       fsl,channel-fifo-len = <24>;
+                       fsl,exec-units-mask = <0x9fe>;
+                       fsl,descriptor-types-mask = <0x3ab0ebf>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               gpio0: gpio@f000 {
+                       compatible = "fsl,mpc8572-gpio";
+                       reg = <0xf000 0x1000>;
+                       interrupts = <47 2>;
+                       interrupt-parent = <&mpic>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+               };
+
+               gpio-leds {
+                       compatible = "gpio-leds";
+
+                       heartbeat {
+                               label = "Heartbeat";
+                               gpios = <&gpio0 4 1>;
+                               linux,default-trigger = "heartbeat";
+                       };
+
+                       yellow {
+                               label = "Yellow";
+                               gpios = <&gpio0 5 1>;
+                       };
+
+                       red {
+                               label = "Red";
+                               gpios = <&gpio0 6 1>;
+                       };
+
+                       green {
+                               label = "Green";
+                               gpios = <&gpio0 7 1>;
+                       };
+               };
+
+               /* PME (pattern-matcher) */
+               pme@10000 {
+                       compatible = "fsl,mpc8572-pme", "pme8572";
+                       reg = <0x10000 0x5000>;
+                       interrupts = <57 2 64 2 65 2 66 2 67 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@2f000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x2f000 0x1000>;
+                       interupts = <61 2 >;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@15000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x15000 0x1000>;
+                       interupts = <75 2>;
+                       interrupt-parent = <&mpic>;
+               };
+       };
+
+       /*
+        * PCI Express controller 3 @ ef008000 is not used.
+        * This would have been pci0 on other mpc85xx platforms.
+        *
+        * PCI Express controller 2 @ ef009000 is not used.
+        * This would have been pci1 on other mpc85xx platforms.
+        */
+
+       /* PCI Express controller 1, wired to PEX8648 PCIe switch */
+       pci2: pcie@ef00a000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef00a000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+                         0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x40000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
new file mode 100644 (file)
index 0000000..a0cf53f
--- /dev/null
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
+ * Based on TQM8548 device tree
+ *
+ * XPedite5200 PrPMC/XMC module based on MPC8548E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/ {
+       model = "xes,xpedite5200";
+       compatible = "xes,xpedite5200", "xes,MPC8548";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               ethernet3 = &enet3;
+
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci0 = &pci0;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8548@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;        // L1, 32K
+                       i-cache-size = <0x8000>;        // L1, 32K
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0>;        // Filled in by U-Boot
+       };
+
+       soc@ef000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               ranges = <0x0 0xef000000 0x100000>;
+               bus-frequency = <0>;
+               compatible = "fsl,mpc8548-immr", "simple-bus";
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8548-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8548-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512K
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               /* On-card I2C */
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       /*
+                        * Board GPIO:
+                        *      0: BRD_CFG0 (1: P14 IO present)
+                        *      1: BRD_CFG1 (1: FP ethernet present)
+                        *      2: BRD_CFG2 (1: XMC IO present)
+                        *      3: XMC root complex indicator
+                        *      4: Flash boot device indicator
+                        *      5: Flash write protect enable
+                        *      6: PMC monarch indicator
+                        *      7: PMC EREADY
+                        */
+                       gpio1: gpio@18 {
+                               compatible = "nxp,pca9556";
+                               reg = <0x18>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       /* P14 GPIO */
+                       gpio2: gpio@19 {
+                               compatible = "nxp,pca9556";
+                               reg = <0x19>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       eeprom@50 {
+                               compatible = "atmel,at24c16";
+                               reg = <0x50>;
+                       };
+
+                       rtc@68 {
+                               compatible = "stm,m41t00",
+                                            "dallas,ds1338";
+                               reg = <0x68>;
+                       };
+
+                       dtt@48 {
+                               compatible = "maxim,max1237";
+                               reg = <0x34>;
+                       };
+               };
+
+               /* Off-card I2C */
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               /* eTSEC1: Front panel port 0 */
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x1>;
+                               };
+                               phy1: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x2>;
+                               };
+                               phy2: ethernet-phy@3 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x3>;
+                               };
+                               phy3: ethernet-phy@4 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x4>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC2: Front panel port 1 */
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC3: Rear panel port 2 */
+               enet2: ethernet@26000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <2>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x26000 0x1000>;
+                       ranges = <0x0 0x26000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <31 2 32 2 33 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi2>;
+                       phy-handle = <&phy2>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi2: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC4: Rear panel port 3 */
+               enet3: ethernet@27000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <3>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x27000 0x1000>;
+                       ranges = <0x0 0x27000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <37 2 38 2 39 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi3>;
+                       phy-handle = <&phy3>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi3: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       current-speed = <115200>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       current-speed = <115200>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        // global utilities reg
+                       compatible = "fsl,mpc8548-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+       };
+
+       localbus@ef005000 {
+               compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
+                            "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <1>;
+               reg = <0xef005000 0x100>;       // BRx, ORx, etc.
+
+               ranges = <
+                       0 0x0 0xfc000000 0x04000000     // NOR boot flash
+                       1 0x0 0xf8000000 0x04000000     // NOR expansion flash
+                       2 0x0 0xef800000 0x00010000     // NAND CE1
+                       3 0x0 0xef840000 0x00010000     // NAND CE2
+               >;
+
+               nor-boot@0,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "cfi-flash";
+                       reg = <0 0x0 0x4000000>;
+                       bank-width = <2>;
+
+                       partition@0 {
+                               label = "Primary OS";
+                               reg = <0x00000000 0x180000>;
+                       };
+                       partition@180000 {
+                               label = "Secondary OS";
+                               reg = <0x00180000 0x180000>;
+                       };
+                       partition@300000 {
+                               label = "User";
+                               reg = <0x00300000 0x3c80000>;
+                       };
+                       partition@3f80000 {
+                               label = "Boot firmware";
+                               reg = <0x03f80000 0x80000>;
+                       };
+               };
+
+               nor-alternate@1,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "cfi-flash";
+                       reg = <1 0x0 0x4000000>;
+                       bank-width = <2>;
+
+                       partition@0 {
+                               label = "Filesystem";
+                               reg = <0x00000000 0x3f80000>;
+                       };
+                       partition@3f80000 {
+                               label = "Alternate boot firmware";
+                               reg = <0x03f80000 0x80000>;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "xes,address-ctl-nand";
+                       reg = <2 0x0 0x10000>;
+                       cle-line = <0x8>;       /* CLE tied to A3 */
+                       ale-line = <0x10>;      /* ALE tied to A4 */
+
+                       /* U-Boot should fix this up */
+                       partition@0 {
+                               label = "NAND Filesystem";
+                               reg = <0 0x40000000>;
+                       };
+               };
+       };
+
+       /* PMC interface */
+       pci0: pci@ef008000 {
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+               device_type = "pci";
+               reg = <0xef008000 0x1000>;
+               clock-frequency = <33333333>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                               /* IDSEL */
+                                0xe000 0 0 1 &mpic 2 1
+                                0xe000 0 0 2 &mpic 3 1>;
+
+               interrupt-parent = <&mpic>;
+               interrupts = <24 2>;
+               bus-range = <0 0>;
+               ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
+                         0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
+       };
+
+       /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
+};
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
new file mode 100644 (file)
index 0000000..c5b2975
--- /dev/null
@@ -0,0 +1,506 @@
+/*
+ * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
+ * Based on TQM8548 device tree
+ *
+ * XPedite5200 PrPMC/XMC module based on MPC8548E.  This dts is for the
+ * xMon boot loader memory map which differs from U-Boot's.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/ {
+       model = "xes,xpedite5200";
+       compatible = "xes,xpedite5200", "xes,MPC8548";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       form-factor = "PMC/XMC";
+       boot-bank = <0x0>;
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               ethernet3 = &enet3;
+
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci0 = &pci0;
+               pci1 = &pci1;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8548@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;        // L1, 32K
+                       i-cache-size = <0x8000>;        // L1, 32K
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0>;        // Filled in by boot loader
+       };
+
+       soc@ef000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               ranges = <0x0 0xef000000 0x100000>;
+               bus-frequency = <0>;
+               compatible = "fsl,mpc8548-immr", "simple-bus";
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8548-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8548-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512K
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               /* On-card I2C */
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       /*
+                        * Board GPIO:
+                        *      0: BRD_CFG0 (1: P14 IO present)
+                        *      1: BRD_CFG1 (1: FP ethernet present)
+                        *      2: BRD_CFG2 (1: XMC IO present)
+                        *      3: XMC root complex indicator
+                        *      4: Flash boot device indicator
+                        *      5: Flash write protect enable
+                        *      6: PMC monarch indicator
+                        *      7: PMC EREADY
+                        */
+                       gpio1: gpio@18 {
+                               compatible = "nxp,pca9556";
+                               reg = <0x18>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       /* P14 GPIO */
+                       gpio2: gpio@19 {
+                               compatible = "nxp,pca9556";
+                               reg = <0x19>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       eeprom@50 {
+                               compatible = "atmel,at24c16";
+                               reg = <0x50>;
+                       };
+
+                       rtc@68 {
+                               compatible = "stm,m41t00",
+                                            "dallas,ds1338";
+                               reg = <0x68>;
+                       };
+
+                       dtt@48 {
+                               compatible = "maxim,max1237";
+                               reg = <0x34>;
+                       };
+               };
+
+               /* Off-card I2C */
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8548-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               /* eTSEC1: Front panel port 0 */
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x1>;
+                               };
+                               phy1: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x2>;
+                               };
+                               phy2: ethernet-phy@3 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x3>;
+                               };
+                               phy3: ethernet-phy@4 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x4>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC2: Front panel port 1 */
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC3: Rear panel port 2 */
+               enet2: ethernet@26000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <2>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x26000 0x1000>;
+                       ranges = <0x0 0x26000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <31 2 32 2 33 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi2>;
+                       phy-handle = <&phy2>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi2: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC4: Rear panel port 3 */
+               enet3: ethernet@27000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <3>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x27000 0x1000>;
+                       ranges = <0x0 0x27000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <37 2 38 2 39 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi3>;
+                       phy-handle = <&phy3>;
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi3: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       current-speed = <9600>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       current-speed = <9600>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        // global utilities reg
+                       compatible = "fsl,mpc8548-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+       };
+
+       localbus@ef005000 {
+               compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
+                            "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <1>;
+               reg = <0xef005000 0x100>;       // BRx, ORx, etc.
+
+               ranges = <
+                       0 0x0 0xf8000000 0x08000000     // NOR boot flash
+                       1 0x0 0xf0000000 0x08000000     // NOR expansion flash
+                       2 0x0 0xe8000000 0x00010000     // NAND CE1
+                       3 0x0 0xe8010000 0x00010000     // NAND CE2
+               >;
+
+               nor-boot@0,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "cfi-flash";
+                       reg = <0 0x0 0x4000000>;
+                       bank-width = <2>;
+
+                       partition@0 {
+                               label = "Primary OS";
+                               reg = <0x00000000 0x180000>;
+                       };
+                       partition@180000 {
+                               label = "Secondary OS";
+                               reg = <0x00180000 0x180000>;
+                       };
+                       partition@300000 {
+                               label = "User";
+                               reg = <0x00300000 0x3c80000>;
+                       };
+                       partition@3f80000 {
+                               label = "Boot firmware";
+                               reg = <0x03f80000 0x80000>;
+                       };
+               };
+
+               nor-alternate@1,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "cfi-flash";
+                       reg = <1 0x0 0x4000000>;
+                       bank-width = <2>;
+
+                       partition@0 {
+                               label = "Filesystem";
+                               reg = <0x00000000 0x3f80000>;
+                       };
+                       partition@3f80000 {
+                               label = "Alternate boot firmware";
+                               reg = <0x03f80000 0x80000>;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "xes,address-ctl-nand";
+                       reg = <2 0x0 0x10000>;
+                       cle-line = <0x8>;       /* CLE tied to A3 */
+                       ale-line = <0x10>;      /* ALE tied to A4 */
+
+                       partition@0 {
+                               label = "NAND Filesystem";
+                               reg = <0 0x40000000>;
+                       };
+               };
+       };
+
+       /* PMC interface */
+       pci0: pci@ef008000 {
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+               device_type = "pci";
+               reg = <0xef008000 0x1000>;
+               clock-frequency = <33333333>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                               /* IDSEL */
+                                0xe000 0 0 1 &mpic 2 1
+                                0xe000 0 0 2 &mpic 3 1>;
+
+               interrupt-parent = <&mpic>;
+               interrupts = <24 2>;
+               bus-range = <0 0>;
+               ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
+                         0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
+       };
+
+       /* XMC PCIe */
+       pci1: pcie@ef00a000 {
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x00000 0 0 1 &mpic 0 1
+                       0x00000 0 0 2 &mpic 1 1
+                       0x00000 0 0 3 &mpic 2 1
+                       0x00000 0 0 4 &mpic 3 1>;
+
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               bus-range = <0 0xff>;
+               ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
+                         0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
+               clock-frequency = <33333333>;
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0xef00a000 0x1000>;
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               pcie@0 {
+                       reg = <0 0 0 0 0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x02000000 0 0xc0000000 0x02000000 0
+                                 0xc0000000 0 0x20000000
+                                 0x01000000 0 0x00000000 0x01000000 0
+                                 0x00000000 0 0x08000000>;
+               };
+       };
+
+       /* Needed for dtbImage boot wrapper compatibility */
+       chosen {
+               linux,stdout-path = &serial0;
+       };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
new file mode 100644 (file)
index 0000000..db7faf5
--- /dev/null
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XPedite5301 PMC/XMC module based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+       model = "xes,xpedite5301";
+       compatible = "xes,xpedite5301", "xes,MPC8572";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       form-factor = "PMC/XMC";
+       boot-bank = <0x0>;      /* 0: Primary flash, 1: Secondary flash */
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci1 = &pci1;
+               pci2 = &pci2;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8572@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+
+               PowerPC,8572@1 {
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x0>;        // Filled in by U-Boot
+       };
+
+       localbus@ef005000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+               reg = <0 0xef005000 0 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+               /* Local bus region mappings */
+               ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
+                         1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
+                         2 0 0 0xef800000 0x40000   /* CS2: NAND CE1 */
+                         3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
+
+               nor-boot@0,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       reg = <0 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Primary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Primary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Primary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Primary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Primary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nor-alternate@1,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       //reg = <0xf0000000 0x08000000>; /* 128MB */
+                       reg = <1 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Secondary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Secondary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Secondary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Secondary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Secondary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       /*
+                        * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+                        * Micron MT29F8G08DAA (2x 512 MB), or Micron
+                        * MT29F16G08FAA (2x 1 GB), depending on the build
+                        * configuration
+                        */
+                       compatible = "fsl,mpc8572-fcm-nand",
+                                    "fsl,elbc-fcm-nand";
+                       reg = <2 0 0x40000>;
+                       /* U-Boot should fix this up if chip size > 1 GB */
+                       partition@0 {
+                               label = "NAND Filesystem";
+                               reg = <0 0x40000000>;
+                       };
+               };
+
+       };
+
+       soc8572@ef000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,mpc8572-immr", "simple-bus";
+               ranges = <0x0 0 0xef000000 0x100000>;
+               bus-frequency = <0>;            // Filled out by uboot.
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               memory-controller@6000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x6000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8572-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x100000>; // L2, 1M
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       temp-sensor@48 {
+                               compatible = "dallas,ds1631", "dallas,ds1621";
+                               reg = <0x48>;
+                       };
+
+                       temp-sensor@4c {
+                               compatible = "adi,adt7461";
+                               reg = <0x4c>;
+                       };
+
+                       cpu-supervisor@51 {
+                               compatible = "dallas,ds4510";
+                               reg = <0x51>;
+                       };
+
+                       eeprom@54 {
+                               compatible = "atmel,at24c128b";
+                               reg = <0x54>;
+                       };
+
+                       rtc@68 {
+                               compatible = "stm,m41t00",
+                                            "dallas,ds1338";
+                               reg = <0x68>;
+                       };
+
+                       pcie-switch@70 {
+                               compatible = "plx,pex8518";
+                               reg = <0x70>;
+                       };
+
+                       gpio1: gpio@18 {
+                               compatible = "nxp,pca9557";
+                               reg = <0x18>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio2: gpio@1c {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1c>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio3: gpio@1e {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1e>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio4: gpio@1f {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1f>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@c300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0xc300 0x4>;
+                       ranges = <0x0 0xc100 0x200>;
+                       cell-index = <1>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <76 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <77 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <78 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <79 2>;
+                       };
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               /* eTSEC 1 */
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x1>;
+                               };
+                               phy1: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x2>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC 2 */
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* UART0 */
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               /* UART1 */
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        //global utilities block
+                       compatible = "fsl,mpc8572-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               msi@41600 {
+                       compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               crypto@30000 {
+                       compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                    "fsl,sec2.1", "fsl,sec2.0";
+                       reg = <0x30000 0x10000>;
+                       interrupts = <45 2 58 2>;
+                       interrupt-parent = <&mpic>;
+                       fsl,num-channels = <4>;
+                       fsl,channel-fifo-len = <24>;
+                       fsl,exec-units-mask = <0x9fe>;
+                       fsl,descriptor-types-mask = <0x3ab0ebf>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               gpio0: gpio@f000 {
+                       compatible = "fsl,mpc8572-gpio";
+                       reg = <0xf000 0x1000>;
+                       interrupts = <47 2>;
+                       interrupt-parent = <&mpic>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+               };
+
+               gpio-leds {
+                       compatible = "gpio-leds";
+
+                       heartbeat {
+                               label = "Heartbeat";
+                               gpios = <&gpio0 4 1>;
+                               linux,default-trigger = "heartbeat";
+                       };
+
+                       yellow {
+                               label = "Yellow";
+                               gpios = <&gpio0 5 1>;
+                       };
+
+                       red {
+                               label = "Red";
+                               gpios = <&gpio0 6 1>;
+                       };
+
+                       green {
+                               label = "Green";
+                               gpios = <&gpio0 7 1>;
+                       };
+               };
+
+               /* PME (pattern-matcher) */
+               pme@10000 {
+                       compatible = "fsl,mpc8572-pme", "pme8572";
+                       reg = <0x10000 0x5000>;
+                       interrupts = <57 2 64 2 65 2 66 2 67 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@2f000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x2f000 0x1000>;
+                       interupts = <61 2 >;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@15000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x15000 0x1000>;
+                       interupts = <75 2>;
+                       interrupt-parent = <&mpic>;
+               };
+       };
+
+       /*
+        * PCI Express controller 3 @ ef008000 is not used.
+        * This would have been pci0 on other mpc85xx platforms.
+        */
+
+       /* PCI Express controller 2, wired to XMC P15 connector */
+       pci1: pcie@ef009000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef009000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
+                         0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <25 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x5 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x6 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x7 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0xc0000000
+                                 0x2000000 0x0 0xc0000000
+                                 0x0 0x10000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+
+       /* PCI Express controller 1, wired to PEX8112 for PMC interface */
+       pci2: pcie@ef00a000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef00a000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+                         0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x40000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
new file mode 100644 (file)
index 0000000..c364ca6
--- /dev/null
@@ -0,0 +1,707 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XPedite5330 3U CompactPCI module based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+       model = "xes,xpedite5330";
+       compatible = "xes,xpedite5330", "xes,MPC8572";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       form-factor = "3U CompactPCI";
+       boot-bank = <0x0>;      /* 0: Primary flash, 1: Secondary flash */
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci0 = &pci0;
+               pci1 = &pci1;
+               pci2 = &pci2;
+       };
+
+       pmcslots {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               pmcslot@0 {
+                       cell-index = <0>;
+                       /*
+                        * boolean properties (true if defined):
+                        *     monarch;
+                        *     module-present;
+                        */
+               };
+       };
+
+       xmcslots {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               xmcslot@0 {
+                       cell-index = <0>;
+                       /*
+                        * boolean properties (true if defined):
+                        *     module-present;
+                        */
+               };
+       };
+
+       cpci {
+               /*
+                * boolean properties (true if defined):
+                *     system-controller;
+                */
+               system-controller;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8572@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+
+               PowerPC,8572@1 {
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x0>;        // Filled in by U-Boot
+       };
+
+       localbus@ef005000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+               reg = <0 0xef005000 0 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+               /* Local bus region mappings */
+               ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
+                         1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
+                         2 0 0 0xef800000 0x40000   /* CS2: NAND CE1 */
+                         3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
+
+               nor-boot@0,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       reg = <0 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Primary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Primary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Primary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Primary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Primary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nor-alternate@1,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       //reg = <0xf0000000 0x08000000>; /* 128MB */
+                       reg = <1 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Secondary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Secondary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Secondary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Secondary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Secondary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       /*
+                        * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+                        * Micron MT29F8G08DAA (2x 512 MB), or Micron
+                        * MT29F16G08FAA (2x 1 GB), depending on the build
+                        * configuration
+                        */
+                       compatible = "fsl,mpc8572-fcm-nand",
+                                    "fsl,elbc-fcm-nand";
+                       reg = <2 0 0x40000>;
+                       /* U-Boot should fix this up if chip size > 1 GB */
+                       partition@0 {
+                               label = "NAND Filesystem";
+                               reg = <0 0x40000000>;
+                       };
+               };
+
+       };
+
+       soc8572@ef000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,mpc8572-immr", "simple-bus";
+               ranges = <0x0 0 0xef000000 0x100000>;
+               bus-frequency = <0>;            // Filled out by uboot.
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               memory-controller@6000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x6000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8572-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x100000>; // L2, 1M
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       temp-sensor@48 {
+                               compatible = "dallas,ds1631", "dallas,ds1621";
+                               reg = <0x48>;
+                       };
+
+                       temp-sensor@4c {
+                               compatible = "adi,adt7461";
+                               reg = <0x4c>;
+                       };
+
+                       cpu-supervisor@51 {
+                               compatible = "dallas,ds4510";
+                               reg = <0x51>;
+                       };
+
+                       eeprom@54 {
+                               compatible = "atmel,at24c128b";
+                               reg = <0x54>;
+                       };
+
+                       rtc@68 {
+                               compatible = "stm,m41t00",
+                                            "dallas,ds1338";
+                               reg = <0x68>;
+                       };
+
+                       pcie-switch@70 {
+                               compatible = "plx,pex8518";
+                               reg = <0x70>;
+                       };
+
+                       gpio1: gpio@18 {
+                               compatible = "nxp,pca9557";
+                               reg = <0x18>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio2: gpio@1c {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1c>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio3: gpio@1e {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1e>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio4: gpio@1f {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1f>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@c300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0xc300 0x4>;
+                       ranges = <0x0 0xc100 0x200>;
+                       cell-index = <1>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <76 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <77 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <78 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <79 2>;
+                       };
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               /* eTSEC 1 */
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x1>;
+                               };
+                               phy1: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x2>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC 2 */
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* UART0 */
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               /* UART1 */
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        //global utilities block
+                       compatible = "fsl,mpc8572-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               msi@41600 {
+                       compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               crypto@30000 {
+                       compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                    "fsl,sec2.1", "fsl,sec2.0";
+                       reg = <0x30000 0x10000>;
+                       interrupts = <45 2 58 2>;
+                       interrupt-parent = <&mpic>;
+                       fsl,num-channels = <4>;
+                       fsl,channel-fifo-len = <24>;
+                       fsl,exec-units-mask = <0x9fe>;
+                       fsl,descriptor-types-mask = <0x3ab0ebf>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               gpio0: gpio@f000 {
+                       compatible = "fsl,mpc8572-gpio";
+                       reg = <0xf000 0x1000>;
+                       interrupts = <47 2>;
+                       interrupt-parent = <&mpic>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+               };
+
+               gpio-leds {
+                       compatible = "gpio-leds";
+
+                       heartbeat {
+                               label = "Heartbeat";
+                               gpios = <&gpio0 4 1>;
+                               linux,default-trigger = "heartbeat";
+                       };
+
+                       yellow {
+                               label = "Yellow";
+                               gpios = <&gpio0 5 1>;
+                       };
+
+                       red {
+                               label = "Red";
+                               gpios = <&gpio0 6 1>;
+                       };
+
+                       green {
+                               label = "Green";
+                               gpios = <&gpio0 7 1>;
+                       };
+               };
+
+               /* PME (pattern-matcher) */
+               pme@10000 {
+                       compatible = "fsl,mpc8572-pme", "pme8572";
+                       reg = <0x10000 0x5000>;
+                       interrupts = <57 2 64 2 65 2 66 2 67 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@2f000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x2f000 0x1000>;
+                       interupts = <61 2 >;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@15000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x15000 0x1000>;
+                       interupts = <75 2>;
+                       interrupt-parent = <&mpic>;
+               };
+       };
+
+       /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
+       pci0: pcie@ef008000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef008000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
+                         0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <24 2>;
+               interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+               interrupt-map = <
+                       0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x02000000 0x0 0xe0000000
+                                 0x02000000 0x0 0xe0000000
+                                 0x0 0x10000000
+
+                                 0x01000000 0x0 0x0
+                                 0x01000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+
+       /* PCI Express controller 2, PMC module via PEX8112 bridge */
+       pci1: pcie@ef009000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef009000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
+                         0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <25 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x5 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x6 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x7 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0xc0000000
+                                 0x2000000 0x0 0xc0000000
+                                 0x0 0x10000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+
+       /* PCI Express controller 1, XMC P15 */
+       pci2: pcie@ef00a000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef00a000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+                         0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x40000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
new file mode 100644 (file)
index 0000000..7a8a4af
--- /dev/null
@@ -0,0 +1,638 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XPedite5370 3U VPX single-board computer based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+       model = "xes,xpedite5370";
+       compatible = "xes,xpedite5370", "xes,MPC8572";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci1 = &pci1;
+               pci2 = &pci2;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8572@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+
+               PowerPC,8572@1 {
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x0>;        // Filled in by U-Boot
+       };
+
+       localbus@ef005000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+               reg = <0 0xef005000 0 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+               /* Local bus region mappings */
+               ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
+                         1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
+                         2 0 0 0xef800000 0x40000   /* CS2: NAND CE1 */
+                         3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
+
+               nor-boot@0,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       reg = <0 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Primary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Primary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Primary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Primary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Primary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nor-alternate@1,0 {
+                       compatible = "amd,s29gl01gp", "cfi-flash";
+                       bank-width = <2>;
+                       //reg = <0xf0000000 0x08000000>; /* 128MB */
+                       reg = <1 0 0x8000000>; /* 128MB */
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "Secondary user space";
+                               reg = <0x00000000 0x6f00000>; /* 111 MB */
+                       };
+                       partition@6f00000 {
+                               label = "Secondary kernel";
+                               reg = <0x6f00000 0x1000000>; /* 16 MB */
+                       };
+                       partition@7f00000 {
+                               label = "Secondary DTB";
+                               reg = <0x7f00000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f40000 {
+                               label = "Secondary U-Boot environment";
+                               reg = <0x7f40000 0x40000>; /* 256 KB */
+                       };
+                       partition@7f80000 {
+                               label = "Secondary U-Boot";
+                               reg = <0x7f80000 0x80000>; /* 512 KB */
+                               read-only;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       /*
+                        * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+                        * Micron MT29F8G08DAA (2x 512 MB), or Micron
+                        * MT29F16G08FAA (2x 1 GB), depending on the build
+                        * configuration
+                        */
+                       compatible = "fsl,mpc8572-fcm-nand",
+                                    "fsl,elbc-fcm-nand";
+                       reg = <2 0 0x40000>;
+                       /* U-Boot should fix this up if chip size > 1 GB */
+                       partition@0 {
+                               label = "NAND Filesystem";
+                               reg = <0 0x40000000>;
+                       };
+               };
+
+       };
+
+       soc8572@ef000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,mpc8572-immr", "simple-bus";
+               ranges = <0x0 0 0xef000000 0x100000>;
+               bus-frequency = <0>;            // Filled out by uboot.
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               memory-controller@6000 {
+                       compatible = "fsl,mpc8572-memory-controller";
+                       reg = <0x6000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8572-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x100000>; // L2, 1M
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       temp-sensor@48 {
+                               compatible = "dallas,ds1631", "dallas,ds1621";
+                               reg = <0x48>;
+                       };
+
+                       temp-sensor@4c {
+                               compatible = "adi,adt7461";
+                               reg = <0x4c>;
+                       };
+
+                       cpu-supervisor@51 {
+                               compatible = "dallas,ds4510";
+                               reg = <0x51>;
+                       };
+
+                       eeprom@54 {
+                               compatible = "atmel,at24c128b";
+                               reg = <0x54>;
+                       };
+
+                       rtc@68 {
+                               compatible = "stm,m41t00",
+                                            "dallas,ds1338";
+                               reg = <0x68>;
+                       };
+
+                       pcie-switch@70 {
+                               compatible = "plx,pex8518";
+                               reg = <0x70>;
+                       };
+
+                       gpio1: gpio@18 {
+                               compatible = "nxp,pca9557";
+                               reg = <0x18>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio2: gpio@1c {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1c>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio3: gpio@1e {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1e>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+
+                       gpio4: gpio@1f {
+                               compatible = "nxp,pca9557";
+                               reg = <0x1f>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               polarity = <0x00>;
+                       };
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@c300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0xc300 0x4>;
+                       ranges = <0x0 0xc100 0x200>;
+                       cell-index = <1>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <76 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <77 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <78 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <79 2>;
+                       };
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8572-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               /* eTSEC 1 */
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x1>;
+                               };
+                               phy1: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <8 1>;
+                                       reg = <0x2>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* eTSEC 2 */
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+                       phy-connection-type = "sgmii";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               /* UART0 */
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               /* UART1 */
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        //global utilities block
+                       compatible = "fsl,mpc8572-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               msi@41600 {
+                       compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               crypto@30000 {
+                       compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                    "fsl,sec2.1", "fsl,sec2.0";
+                       reg = <0x30000 0x10000>;
+                       interrupts = <45 2 58 2>;
+                       interrupt-parent = <&mpic>;
+                       fsl,num-channels = <4>;
+                       fsl,channel-fifo-len = <24>;
+                       fsl,exec-units-mask = <0x9fe>;
+                       fsl,descriptor-types-mask = <0x3ab0ebf>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               gpio0: gpio@f000 {
+                       compatible = "fsl,mpc8572-gpio";
+                       reg = <0xf000 0x1000>;
+                       interrupts = <47 2>;
+                       interrupt-parent = <&mpic>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+               };
+
+               gpio-leds {
+                       compatible = "gpio-leds";
+
+                       heartbeat {
+                               label = "Heartbeat";
+                               gpios = <&gpio0 4 1>;
+                               linux,default-trigger = "heartbeat";
+                       };
+
+                       yellow {
+                               label = "Yellow";
+                               gpios = <&gpio0 5 1>;
+                       };
+
+                       red {
+                               label = "Red";
+                               gpios = <&gpio0 6 1>;
+                       };
+
+                       green {
+                               label = "Green";
+                               gpios = <&gpio0 7 1>;
+                       };
+               };
+
+               /* PME (pattern-matcher) */
+               pme@10000 {
+                       compatible = "fsl,mpc8572-pme", "pme8572";
+                       reg = <0x10000 0x5000>;
+                       interrupts = <57 2 64 2 65 2 66 2 67 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@2f000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x2f000 0x1000>;
+                       interupts = <61 2 >;
+                       interrupt-parent = <&mpic>;
+               };
+
+               tlu@15000 {
+                       compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+                       reg = <0x15000 0x1000>;
+                       interupts = <75 2>;
+                       interrupt-parent = <&mpic>;
+               };
+       };
+
+       /*
+        * PCI Express controller 3 @ ef008000 is not used.
+        * This would have been pci0 on other mpc85xx platforms.
+        */
+
+       /* PCI Express controller 2, wired to VPX P1,P2 backplane */
+       pci1: pcie@ef009000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef009000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
+                         0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <25 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x5 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x6 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x7 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0xc0000000
+                                 0x2000000 0x0 0xc0000000
+                                 0x0 0x10000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+
+       /* PCI Express controller 1, wired to PEX8518 PCIe switch */
+       pci2: pcie@ef00a000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xef00a000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+                         0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x40000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
+               };
+       };
+};
index 3ac75ae..4db487d 100755 (executable)
@@ -225,6 +225,10 @@ asp834x-redboot)
     platformo="$object/fixed-head.o $object/redboot-83xx.o"
     binary=y
     ;;
+xpedite52*)
+    link_address='0x1400000'
+    platformo=$object/cuboot-85xx.o
+    ;;
 esac
 
 vmz="$tmpdir/`basename \"$kernel\"`.$ext"
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig
new file mode 100644 (file)
index 0000000..bf0853f
--- /dev/null
@@ -0,0 +1,908 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28
+# Fri Apr  3 10:34:33 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+# CONFIG_FSL_EMB_PERFMON is not set
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_CHRP is not set
+# CONFIG_MPC5121_ADS is not set
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_PPC_83xx=y
+# CONFIG_MPC831x_RDB is not set
+# CONFIG_MPC832x_MDS is not set
+# CONFIG_MPC832x_RDB is not set
+# CONFIG_MPC834x_MDS is not set
+# CONFIG_MPC834x_ITX is not set
+# CONFIG_MPC836x_MDS is not set
+# CONFIG_MPC836x_RDK is not set
+# CONFIG_MPC837x_MDS is not set
+# CONFIG_MPC837x_RDB is not set
+# CONFIG_SBC834x is not set
+# CONFIG_ASP834x is not set
+CONFIG_KMETER1=y
+# CONFIG_PPC_86xx is not set
+# CONFIG_EMBEDDED6xx is not set
+CONFIG_IPIC=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+CONFIG_QUICC_ENGINE=y
+# CONFIG_QE_GPIO is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_KEXEC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_FSL_SOC=y
+CONFIG_PPC_PCI_CHOICE=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_PHRAM=y
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+CONFIG_MTD_UBI_DEBUG=y
+# CONFIG_MTD_UBI_DEBUG_MSG is not set
+# CONFIG_MTD_UBI_DEBUG_PARANOID is not set
+# CONFIG_MTD_UBI_DEBUG_DISABLE_BGT is not set
+# CONFIG_MTD_UBI_DEBUG_USERSPACE_IO is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES is not set
+
+#
+# Additional UBI debugging messages
+#
+# CONFIG_MTD_UBI_DEBUG_MSG_BLD is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_EBA is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_WL is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_IO is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_GIANFAR is not set
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_MAGIC_PACKET is not set
+# CONFIG_UGETH_FILTERING is not set
+# CONFIG_UGETH_TX_ON_DEMAND is not set
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_WAN=y
+CONFIG_HDLC=y
+# CONFIG_HDLC_RAW is not set
+# CONFIG_HDLC_RAW_ETH is not set
+# CONFIG_HDLC_CISCO is not set
+# CONFIG_HDLC_FR is not set
+# CONFIG_HDLC_PPP is not set
+
+#
+# X.25/LAPB support is disabled
+#
+CONFIG_HDLC_KM=y
+CONFIG_FS_UCC_HDLC=y
+# CONFIG_DLCI is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPPOE=y
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_QE is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_BOOTCOUNT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_MCU_MPC8349EMITX is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+CONFIG_UIO=y
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+CONFIG_UCC_FAST=y
+CONFIG_UCC=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
new file mode 100644 (file)
index 0000000..2552cbe
--- /dev/null
@@ -0,0 +1,1821 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc6
+# Thu Jun 11 11:25:17 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_E500=y
+# CONFIG_PPC_E500MC is not set
+CONFIG_BOOKE=y
+CONFIG_FSL_BOOKE=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_PHYS_64BIT is not set
+CONFIG_SPE=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_BOOK3E_MMU=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set