Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 3 Jul 2008 01:58:56 +0000 (18:58 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 3 Jul 2008 01:58:56 +0000 (18:58 -0700)
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: fix NODES_SHIFT Kconfig range

277 files changed:
.gitignore
Documentation/DocBook/kgdb.tmpl
Documentation/cpusets.txt
Documentation/feature-removal-schedule.txt
Documentation/hwmon/sysfs-interface
Documentation/networking/ip-sysctl.txt
Documentation/networking/s2io.txt
Documentation/video4linux/CARDLIST.au0828
MAINTAINERS
Makefile
arch/alpha/Makefile
arch/alpha/kernel/core_t2.c
arch/alpha/kernel/pci.c
arch/alpha/kernel/traps.c
arch/blackfin/kernel/cplb-nompu/cplbinit.c
arch/blackfin/kernel/irqchip.c
arch/ia64/kernel/iosapic.c
arch/ia64/kernel/setup.c
arch/ia64/sn/kernel/sn2/sn2_smp.c
arch/powerpc/boot/Makefile
arch/powerpc/kernel/legacy_serial.c
arch/powerpc/kernel/vdso.c
arch/powerpc/platforms/52xx/lite5200_pm.c
arch/x86/Kconfig
arch/x86/kernel/Makefile
arch/x86/kernel/kvmclock.c
arch/x86/kernel/pvclock.c [new file with mode: 0644]
arch/x86/kvm/i8254.c
arch/x86/kvm/lapic.c
arch/x86/kvm/mmu.c
arch/x86/kvm/vmx.c
arch/x86/kvm/x86.c
arch/x86/xen/Kconfig
arch/x86/xen/time.c
drivers/acpi/ac.c
drivers/acpi/bay.c
drivers/acpi/dock.c
drivers/acpi/glue.c
drivers/acpi/video.c
drivers/ata/Kconfig
drivers/ata/ahci.c
drivers/ata/ata_piix.c
drivers/ata/libata-core.c
drivers/ata/libata-scsi.c
drivers/ata/libata.h
drivers/ata/pata_pcmcia.c
drivers/ata/sata_mv.c
drivers/char/agp/intel-agp.c
drivers/char/drm/ati_pcigart.c
drivers/char/drm/drm.h
drivers/char/drm/drm_drv.c
drivers/char/drm/drm_pciids.h
drivers/char/drm/i915_drv.c
drivers/char/drm/i915_drv.h
drivers/char/drm/i915_irq.c
drivers/char/drm/r300_cmdbuf.c
drivers/char/drm/r300_reg.h
drivers/char/drm/radeon_cp.c
drivers/char/drm/radeon_drm.h
drivers/char/drm/radeon_drv.h
drivers/char/drm/radeon_irq.c
drivers/char/drm/radeon_microcode.h [new file with mode: 0644]
drivers/char/drm/radeon_state.c
drivers/char/tty_ioctl.c
drivers/connector/connector.c
drivers/firewire/Kconfig
drivers/firewire/fw-cdev.c
drivers/firewire/fw-ohci.c
drivers/firewire/fw-sbp2.c
drivers/firewire/fw-transaction.c
drivers/hwmon/abituguru3.c
drivers/hwmon/adt7473.c
drivers/hwmon/lm75.c
drivers/hwmon/lm85.c
drivers/ide/Kconfig
drivers/ide/arm/Makefile
drivers/ide/arm/bast-ide.c [deleted file]
drivers/ide/arm/palm_bk3710.c
drivers/ide/ide-taskfile.c
drivers/ide/legacy/ide-cs.c
drivers/ieee1394/Kconfig
drivers/infiniband/hw/mthca/mthca_memfree.c
drivers/input/ff-core.c
drivers/md/dm-crypt.c
drivers/md/md.c
drivers/md/raid10.c
drivers/md/raid5.c
drivers/media/common/ir-keymaps.c
drivers/media/common/tuners/tda18271-common.c
drivers/media/common/tuners/tda18271-fe.c
drivers/media/common/tuners/xc5000.c
drivers/media/common/tuners/xc5000_priv.h
drivers/media/dvb/dvb-usb/gl861.c
drivers/media/dvb/dvb-usb/umt-010.c
drivers/media/dvb/frontends/au8522.c
drivers/media/dvb/frontends/stv0299.c
drivers/media/dvb/frontends/tda10023.c
drivers/media/dvb/frontends/tda1004x.c
drivers/media/dvb/ttpci/Kconfig
drivers/media/dvb/ttpci/av7110_hw.c
drivers/media/video/au0828/au0828-cards.c
drivers/media/video/cx18/Kconfig
drivers/media/video/cx18/cx18-av-core.c
drivers/media/video/cx18/cx18-av-core.h
drivers/media/video/cx18/cx18-cards.c
drivers/media/video/cx18/cx18-cards.h
drivers/media/video/cx18/cx18-dvb.c
drivers/media/video/cx18/cx18-gpio.c
drivers/media/video/cx18/cx18-gpio.h
drivers/media/video/cx18/cx18-i2c.c
drivers/media/video/cx25840/cx25840-core.c
drivers/media/video/cx88/cx88-alsa.c
drivers/media/video/em28xx/em28xx-audio.c
drivers/media/video/em28xx/em28xx-cards.c
drivers/media/video/em28xx/em28xx-dvb.c
drivers/media/video/em28xx/em28xx-reg.h
drivers/media/video/em28xx/em28xx-video.c
drivers/media/video/pxa_camera.c
drivers/media/video/saa7134/saa7134-alsa.c
drivers/media/video/saa7134/saa7134-cards.c
drivers/media/video/saa7134/saa7134-dvb.c
drivers/media/video/saa7134/saa7134-empress.c
drivers/media/video/saa7134/saa7134-input.c
drivers/media/video/soc_camera.c
drivers/media/video/videodev.c
drivers/media/video/vivi.c
drivers/net/3c59x.c
drivers/net/e100.c
drivers/net/e1000/e1000_ethtool.c
drivers/net/e1000e/netdev.c
drivers/net/hamradio/dmascc.c
drivers/net/igb/igb_main.c
drivers/net/ipg.c
drivers/net/ixgbe/ixgbe_main.c
drivers/net/netxen/netxen_nic_main.c
drivers/net/pcmcia/axnet_cs.c
drivers/net/pcmcia/pcnet_cs.c
drivers/net/pppoe.c
drivers/net/qla3xxx.c
drivers/net/r6040.c
drivers/net/s2io.c
drivers/net/s2io.h
drivers/net/tc35815.c
drivers/net/wan/x25_asy.c
drivers/net/wireless/b43/leds.c
drivers/net/wireless/b43/main.c
drivers/net/wireless/b43legacy/dma.c
drivers/net/wireless/b43legacy/main.c
drivers/net/wireless/hostap/hostap_80211_rx.c
drivers/net/wireless/hostap/hostap_ap.c
drivers/net/wireless/hostap/hostap_cs.c
drivers/net/wireless/hostap/hostap_hw.c
drivers/net/wireless/hostap/hostap_main.c
drivers/net/wireless/iwlwifi/iwl3945-base.c
drivers/net/wireless/iwlwifi/iwl4965-base.c
drivers/net/wireless/prism54/islpci_eth.c
drivers/net/wireless/rt2x00/rt2500usb.c
drivers/net/wireless/rt2x00/rt2x00.h
drivers/net/wireless/rt2x00/rt2x00dev.c
drivers/net/wireless/rt2x00/rt2x00mac.c
drivers/net/wireless/rt2x00/rt73usb.c
drivers/scsi/esp_scsi.c
drivers/scsi/ses.c
drivers/serial/bfin_5xx.c
drivers/thermal/Kconfig
drivers/thermal/thermal_sys.c
drivers/watchdog/Makefile
drivers/watchdog/hpwdt.c
fs/block_dev.c
fs/dcache.c
fs/ext4/resize.c
fs/gfs2/bmap.c
fs/gfs2/rgrp.c
fs/locks.c
fs/namei.c
fs/nfs/mount_clnt.c
fs/nfs/super.c
fs/nfs/write.c
fs/pipe.c
fs/select.c
fs/udf/super.c
fs/utimes.c
include/asm-alpha/core_mcpcia.h
include/asm-alpha/core_t2.h
include/asm-alpha/io.h
include/asm-alpha/mmu_context.h
include/asm-alpha/percpu.h
include/asm-alpha/system.h
include/asm-alpha/vga.h
include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
include/asm-generic/Kbuild.asm
include/asm-powerpc/Kbuild
include/asm-x86/kvm_host.h
include/asm-x86/kvm_para.h
include/asm-x86/pvclock-abi.h [new file with mode: 0644]
include/asm-x86/pvclock.h [new file with mode: 0644]
include/linux/Kbuild
include/linux/audit.h
include/linux/bootmem.h
include/linux/dcache.h
include/linux/fs.h
include/linux/inet_lro.h
include/linux/input.h
include/linux/kvm_host.h
include/linux/netdevice.h
include/linux/thermal.h
include/linux/tty_driver.h
include/media/cx25840.h
include/media/ir-common.h
include/media/v4l2-dev.h
include/net/ipv6.h
include/net/mac80211.h
include/net/net_namespace.h
include/net/sch_generic.h
include/xen/interface/xen.h
kernel/audit.c
kernel/auditfilter.c
kernel/cpuset.c
kernel/futex.c
kernel/kgdb.c
kernel/rcupreempt.c
kernel/sched.c
kernel/sched_rt.c
kernel/sched_stats.h
kernel/softlockup.c
lib/debugobjects.c
lib/ts_bm.c
mm/bootmem.c
mm/memory.c
mm/migrate.c
mm/slab.c
net/core/dev.c
net/core/fib_rules.c
net/core/filter.c
net/core/net_namespace.c
net/core/skbuff.c
net/ipv4/inet_fragment.c
net/ipv4/inet_lro.c
net/ipv4/ip_fragment.c
net/ipv4/tcp.c
net/ipv4/tcp_ipv4.c
net/ipv6/ip6_input.c
net/ipv6/ipv6_sockglue.c
net/ipv6/netfilter/ip6table_mangle.c
net/ipv6/netfilter/nf_conntrack_reasm.c
net/ipv6/reassembly.c
net/ipv6/route.c
net/ipv6/tcp_ipv6.c
net/mac80211/key.c
net/mac80211/tx.c
net/mac80211/wext.c
net/mac80211/wme.c
net/netfilter/nf_conntrack_proto_tcp.c
net/netlabel/netlabel_unlabeled.c
net/netlink/af_netlink.c
net/netlink/attr.c
net/sched/Kconfig
net/sched/sch_api.c
net/sched/sch_atm.c
net/sched/sch_cbq.c
net/sched/sch_dsmark.c
net/sched/sch_generic.c
net/sched/sch_hfsc.c
net/sched/sch_htb.c
net/sched/sch_ingress.c
net/sched/sch_prio.c
net/sched/sch_sfq.c
net/sctp/socket.c
net/unix/af_unix.c
net/wireless/reg.c
sound/isa/sb/sb_mixer.c
sound/pci/aw2/aw2-alsa.c
virt/kvm/ioapic.c

index 9bb1cb6..869e1a3 100644 (file)
@@ -3,6 +3,10 @@
 # subdirectories here. Add them in the ".gitignore" file
 # in that subdirectory instead.
 #
+# NOTE! Please use 'git-ls-files -i --exclude-standard'
+# command after changing this file, to see if there are
+# any tracked files which get ignored after the change.
+#
 # Normal rules
 #
 .*
 *.lst
 *.symtypes
 *.order
+*.elf
+*.bin
+*.gz
 
 #
 # Top-level generic files
 #
 tags
 TAGS
-vmlinux*
-!vmlinux.lds.S
-!vmlinux.lds.h
+vmlinux
 System.map
 Module.markers
 Module.symvers
 !.gitignore
+!.mailmap
 
 #
 # Generated include files
index 028a844..e8acd1f 100644 (file)
     runs an instance of gdb against the vmlinux file which contains
     the symbols (not boot image such as bzImage, zImage, uImage...).
     In gdb the developer specifies the connection parameters and
-    connects to kgdb.  Depending on which kgdb I/O modules exist in
-    the kernel for a given architecture, it may be possible to debug
-    the test machine's kernel with the development machine using a
-    rs232 or ethernet connection.
+    connects to kgdb.  The type of connection a developer makes with
+    gdb depends on the availability of kgdb I/O modules compiled as
+    builtin's or kernel modules in the test machine's kernel.
     </para>
   </chapter>
   <chapter id="CompilingAKernel">
   </para>
   <para>
   IMPORTANT NOTE: Using this option with kgdb over the console
-  (kgdboc) or kgdb over ethernet (kgdboe) is not supported.
+  (kgdboc) is not supported.
   </para>
   </sect1>
   </chapter>
     (gdb) target remote /dev/ttyS0
     </programlisting>
     <para>
-    Example (kgdb to a terminal server):
+    Example (kgdb to a terminal server on tcp port 2012):
     </para>
     <programlisting>
     % gdb ./vmlinux
-    (gdb) target remote udp:192.168.2.2:6443
-    </programlisting>
-    <para>
-    Example (kgdb over ethernet):
-    </para>
-    <programlisting>
-    % gdb ./vmlinux
-    (gdb) target remote udp:192.168.2.2:6443
+    (gdb) target remote 192.168.2.2:2012
     </programlisting>
     <para>
     Once connected, you can debug a kernel the way you would debug an
index d803c5c..353504d 100644 (file)
@@ -542,7 +542,7 @@ otherwise initial value -1 that indicates the cpuset has no request.
    2  : search cores in a package.
    3  : search cpus in a node [= system wide on non-NUMA system]
  ( 4  : search nodes in a chunk of node [on NUMA system] )
- ( 5~ : search system wide [on NUMA system])
+ ( 5  : search system wide [on NUMA system] )
 
 This file is per-cpuset and affect the sched domain where the cpuset
 belongs to.  Therefore if the flag 'sched_load_balance' of a cpuset
index 5b3f31f..46ece3f 100644 (file)
@@ -312,3 +312,12 @@ When:      2.6.26
 Why:   Implementation became generic; users should now include
        linux/semaphore.h instead.
 Who:   Matthew Wilcox <willy@linux.intel.com>
+
+---------------------------
+
+What:  CONFIG_THERMAL_HWMON
+When:  January 2009
+Why:   This option was introduced just to allow older lm-sensors userspace
+       to keep working over the upgrade to 2.6.26. At the scheduled time of
+       removal fixed lm-sensors (2.x or 3.x) should be readily available.
+Who:   Rene Herman <rene.herman@gmail.com>
index f4a8ebc..2d84573 100644 (file)
@@ -2,17 +2,12 @@ Naming and data format standards for sysfs files
 ------------------------------------------------
 
 The libsensors library offers an interface to the raw sensors data
-through the sysfs interface. See libsensors documentation and source for
-further information. As of writing this document, libsensors
-(from lm_sensors 2.8.3) is heavily chip-dependent. Adding or updating
-support for any given chip requires modifying the library's code.
-This is because libsensors was written for the procfs interface
-older kernel modules were using, which wasn't standardized enough.
-Recent versions of libsensors (from lm_sensors 2.8.2 and later) have
-support for the sysfs interface, though.
-
-The new sysfs interface was designed to be as chip-independent as
-possible.
+through the sysfs interface. Since lm-sensors 3.0.0, libsensors is
+completely chip-independent. It assumes that all the kernel drivers
+implement the standard sysfs interface described in this document.
+This makes adding or updating support for any given chip very easy, as
+libsensors, and applications using it, do not need to be modified.
+This is a major improvement compared to lm-sensors 2.
 
 Note that motherboards vary widely in the connections to sensor chips.
 There is no standard that ensures, for example, that the second
@@ -35,19 +30,17 @@ access this data in a simple and consistent way. That said, such programs
 will have to implement conversion, labeling and hiding of inputs. For
 this reason, it is still not recommended to bypass the library.
 
-If you are developing a userspace application please send us feedback on
-this standard.
-
-Note that this standard isn't completely established yet, so it is subject
-to changes. If you are writing a new hardware monitoring driver those
-features can't seem to fit in this interface, please contact us with your
-extension proposal. Keep in mind that backward compatibility must be
-preserved.
-
 Each chip gets its own directory in the sysfs /sys/devices tree.  To
 find all sensor chips, it is easier to follow the device symlinks from
 /sys/class/hwmon/hwmon*.
 
+Up to lm-sensors 3.0.0, libsensors looks for hardware monitoring attributes
+in the "physical" device directory. Since lm-sensors 3.0.1, attributes found
+in the hwmon "class" device directory are also supported. Complex drivers
+(e.g. drivers for multifunction chips) may want to use this possibility to
+avoid namespace pollution. The only drawback will be that older versions of
+libsensors won't support the driver in question.
+
 All sysfs values are fixed point numbers.
 
 There is only one value per file, unlike the older /proc specification.
index 17a6e46..17f1f91 100644 (file)
@@ -81,23 +81,23 @@ inet_peer_minttl - INTEGER
        Minimum time-to-live of entries.  Should be enough to cover fragment
        time-to-live on the reassembling side.  This minimum time-to-live  is
        guaranteed if the pool size is less than inet_peer_threshold.
-       Measured in jiffies(1).
+       Measured in seconds.
 
 inet_peer_maxttl - INTEGER
        Maximum time-to-live of entries.  Unused entries will expire after
        this period of time if there is no memory pressure on the pool (i.e.
        when the number of entries in the pool is very small).
-       Measured in jiffies(1).
+       Measured in seconds.
 
 inet_peer_gc_mintime - INTEGER
        Minimum interval between garbage collection passes.  This interval is
        in effect under high memory pressure on the pool.
-       Measured in jiffies(1).
+       Measured in seconds.
 
 inet_peer_gc_maxtime - INTEGER
        Minimum interval between garbage collection passes.  This interval is
        in effect under low (or absent) memory pressure on the pool.
-       Measured in jiffies(1).
+       Measured in seconds.
 
 TCP variables: 
 
@@ -794,10 +794,6 @@ tag - INTEGER
        Allows you to write a number, which can be used as required.
        Default value is 0.
 
-(1) Jiffie: internal timeunit for the kernel. On the i386 1/100s, on the
-Alpha 1/1024s. See the HZ define in /usr/include/asm/param.h for the exact
-value on your system. 
-
 Alexey Kuznetsov.
 kuznet@ms2.inr.ac.ru
 
index 4bde53e..1e28e2d 100644 (file)
@@ -83,9 +83,9 @@ Valid range: Limited by memory on system
 Default: 30 
 
 e. intr_type
-Specifies interrupt type. Possible values 1(INTA), 2(MSI), 3(MSI-X)
-Valid range: 1-3
-Default: 
+Specifies interrupt type. Possible values 0(INTA), 2(MSI-X)
+Valid values: 0, 2
+Default: 2
 
 5.  Performance suggestions
 General:
index aaae360..86d1c8e 100644 (file)
@@ -1,4 +1,4 @@
   0 -> Unknown board                            (au0828)
-  1 -> Hauppauge HVR950Q                        (au0828)        [2040:7200]
+  1 -> Hauppauge HVR950Q                        (au0828)        [2040:7200,2040:7210,2040:7217,2040:721b,2040:721f,2040:7280,0fd9:0008]
   2 -> Hauppauge HVR850                         (au0828)        [2040:7240]
   3 -> DViCO FusionHDTV USB                     (au0828)        [0fe9:d620]
index cd587ee..8f0ec46 100644 (file)
@@ -4431,10 +4431,10 @@ M:      johnpol@2ka.mipt.ru
 S:     Maintained
 
 W83791D HARDWARE MONITORING DRIVER
-P:     Charles Spirakis
-M:     bezaur@gmail.com
+P:     Marc Hulsman
+M:     m.hulsman@tudelft.nl
 L:     lm-sensors@lm-sensors.org
-S:     Odd Fixes
+S:     Maintained
 
 W83793 HARDWARE MONITORING DRIVER
 P:     Rudolf Marek
index 6923d66..6aff5f4 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 26
-EXTRAVERSION = -rc6
+EXTRAVERSION = -rc8
 NAME = Rotary Wombat
 
 # *DOCUMENTATION*
index 4e1a8e2..4759fe7 100644 (file)
@@ -13,6 +13,7 @@ NM := $(NM) -B
 LDFLAGS_vmlinux        := -static -N #-relax
 CHECKFLAGS     += -D__alpha__ -m64
 cflags-y       := -pipe -mno-fp-regs -ffixed-8 -msmall-data
+cflags-y       += $(call cc-option, -fno-jump-tables)
 
 cpuflags-$(CONFIG_ALPHA_EV4)           := -mcpu=ev4
 cpuflags-$(CONFIG_ALPHA_EV5)           := -mcpu=ev5
index c075029..d9980d4 100644 (file)
@@ -74,6 +74,8 @@
 # define DBG(args)
 #endif
 
+DEFINE_SPINLOCK(t2_hae_lock);
+
 static volatile unsigned int t2_mcheck_any_expected;
 static volatile unsigned int t2_mcheck_last_taken;
 
index 36ab22a..5cf45fc 100644 (file)
@@ -71,6 +71,23 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_i
 static void __init
 quirk_cypress(struct pci_dev *dev)
 {
+       /* The Notorious Cy82C693 chip.  */
+
+       /* The generic legacy mode IDE fixup in drivers/pci/probe.c
+          doesn't work correctly with the Cypress IDE controller as
+          it has non-standard register layout.  Fix that.  */
+       if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
+               dev->resource[2].start = dev->resource[3].start = 0;
+               dev->resource[2].end = dev->resource[3].end = 0;
+               dev->resource[2].flags = dev->resource[3].flags = 0;
+               if (PCI_FUNC(dev->devfn) == 2) {
+                       dev->resource[0].start = 0x170;
+                       dev->resource[0].end = 0x177;
+                       dev->resource[1].start = 0x376;
+                       dev->resource[1].end = 0x376;
+               }
+       }
+
        /* The Cypress bridge responds on the PCI bus in the address range
           0xffff0000-0xffffffff (conventional x86 BIOS ROM).  There is no
           way to turn this off.  The bridge also supports several extended
index dc57790..c778779 100644 (file)
@@ -447,7 +447,7 @@ struct unaligned_stat {
 
 
 /* Macro for exception fixup code to access integer registers.  */
-#define una_reg(r)  (regs->regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)])
+#define una_reg(r)  (_regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)])
 
 
 asmlinkage void
@@ -456,6 +456,7 @@ do_entUna(void * va, unsigned long opcode, unsigned long reg,
 {
        long error, tmp1, tmp2, tmp3, tmp4;
        unsigned long pc = regs->pc - 4;
+       unsigned long *_regs = regs->regs;
        const struct exception_table_entry *fixup;
 
        unaligned[0].count++;
index 917325b..6be0c50 100644 (file)
@@ -254,7 +254,8 @@ close_cplbtab(struct cplb_tab *table)
 }
 
 /* helper function */
-static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
+static void __init
+__fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 {
        if (cplb_data[i].psize) {
                fill_cplbtab(t,
@@ -291,7 +292,8 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_en
        }
 }
 
-static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
+static void __init
+__fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 {
        if (cplb_data[i].psize) {
                fill_cplbtab(t,
index 73647c1..07402f5 100644 (file)
@@ -60,9 +60,14 @@ static struct irq_chip bad_chip = {
 };
 
 static struct irq_desc bad_irq_desc = {
+       .status = IRQ_DISABLED,
        .chip = &bad_chip,
        .handle_irq = handle_bad_irq,
        .depth = 1,
+       .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock),
+#ifdef CONFIG_SMP
+       .affinity = CPU_MASK_ALL
+#endif
 };
 
 int show_interrupts(struct seq_file *p, void *v)
index 082c31d..39752cd 100644 (file)
@@ -558,8 +558,6 @@ static struct iosapic_rte_info * __init_refok iosapic_alloc_rte (void)
        if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
                rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
                                    NR_PREALLOCATE_RTE_ENTRIES);
-               if (!rte)
-                       return NULL;
                for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
                        list_add(&rte->rte_list, &free_rte_list);
        }
index f48a809..4ae15c8 100644 (file)
@@ -578,8 +578,6 @@ setup_arch (char **cmdline_p)
        cpu_init();     /* initialize the bootstrap CPU */
        mmu_context_init();     /* initialize context_id bitmap */
 
-       check_sal_cache_flush();
-
 #ifdef CONFIG_ACPI
        acpi_boot_init();
 #endif
@@ -607,6 +605,7 @@ setup_arch (char **cmdline_p)
                ia64_mca_init();
 
        platform_setup(cmdline_p);
+       check_sal_cache_flush();
        paging_init();
 }
 
index 49d3120..e585f9a 100644 (file)
@@ -512,6 +512,8 @@ static ssize_t sn2_ptc_proc_write(struct file *file, const char __user *user, si
        int cpu;
        char optstr[64];
 
+       if (count == 0 || count > sizeof(optstr))
+               return -EINVAL;
        if (copy_from_user(optstr, user, count))
                return -EFAULT;
        optstr[count - 1] = '\0';
index 1cee2f9..095e04d 100644 (file)
@@ -273,7 +273,8 @@ endif
 initrd-  := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-))
 initrd-y := $(patsubst zImage%, zImage.initrd%, \
                $(patsubst dtbImage%, dtbImage.initrd%, \
-               $(patsubst treeImage%, treeImage.initrd%, $(image-y))))
+               $(patsubst simpleImage%, simpleImage.initrd%, \
+               $(patsubst treeImage%, treeImage.initrd%, $(image-y)))))
 initrd-y := $(filter-out $(image-y), $(initrd-y))
 targets        += $(image-y) $(initrd-y)
 
index 61dd174..cf37f5c 100644 (file)
@@ -136,6 +136,11 @@ static int __init add_legacy_soc_port(struct device_node *np,
        if (of_get_property(np, "clock-frequency", NULL) == NULL)
                return -1;
 
+       /* if reg-shift or offset, don't try to use it */
+       if ((of_get_property(np, "reg-shift", NULL) != NULL) ||
+               (of_get_property(np, "reg-offset", NULL) != NULL))
+               return -1;
+
        /* if rtas uses this device, don't try to use it as well */
        if (of_get_property(np, "used-by-rtas", NULL) != NULL)
                return -1;
index c21a626..ce245a8 100644 (file)
@@ -142,7 +142,7 @@ static void dump_one_vdso_page(struct page *pg, struct page *upg)
        printk("kpg: %p (c:%d,f:%08lx)", __va(page_to_pfn(pg) << PAGE_SHIFT),
               page_count(pg),
               pg->flags);
-       if (upg/* && pg != upg*/) {
+       if (upg && !IS_ERR(upg) /* && pg != upg*/) {
                printk(" upg: %p (c:%d,f:%08lx)", __va(page_to_pfn(upg)
                                                       << PAGE_SHIFT),
                       page_count(upg),
index 41c7fd9..fe92e65 100644 (file)
@@ -14,6 +14,7 @@ static struct mpc52xx_sdma __iomem *bes;
 static struct mpc52xx_xlb __iomem *xlb;
 static struct mpc52xx_gpio __iomem *gps;
 static struct mpc52xx_gpio_wkup __iomem *gpw;
+static void __iomem *pci;
 static void __iomem *sram;
 static const int sram_size = 0x4000;   /* 16 kBytes */
 static void __iomem *mbar;
@@ -50,6 +51,8 @@ static int lite5200_pm_prepare(void)
                { .type = "builtin", .compatible = "mpc5200", }, /* efika */
                {}
        };
+       u64 regaddr64 = 0;
+       const u32 *regaddr_p;
 
        /* deep sleep? let mpc52xx code handle that */
        if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
@@ -60,8 +63,12 @@ static int lite5200_pm_prepare(void)
 
        /* map registers */
        np = of_find_matching_node(NULL, immr_ids);
-       mbar = of_iomap(np, 0);
+       regaddr_p = of_get_address(np, 0, NULL, NULL);
+       if (regaddr_p)
+               regaddr64 = of_translate_address(np, regaddr_p);
        of_node_put(np);
+
+       mbar = ioremap((u32) regaddr64, 0xC000);
        if (!mbar) {
                printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
                return -ENOSYS;
@@ -71,6 +78,7 @@ static int lite5200_pm_prepare(void)
        pic = mbar + 0x500;
        gps = mbar + 0xb00;
        gpw = mbar + 0xc00;
+       pci = mbar + 0xd00;
        bes = mbar + 0x1200;
        xlb = mbar + 0x1f00;
        sram = mbar + 0x8000;
@@ -85,6 +93,7 @@ static struct mpc52xx_sdma sbes;
 static struct mpc52xx_xlb sxlb;
 static struct mpc52xx_gpio sgps;
 static struct mpc52xx_gpio_wkup sgpw;
+static char spci[0x200];
 
 static void lite5200_save_regs(void)
 {
@@ -94,6 +103,7 @@ static void lite5200_save_regs(void)
        _memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
        _memcpy_fromio(&sgps, gps, sizeof(*gps));
        _memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
+       _memcpy_fromio(spci, pci, 0x200);
 
        _memcpy_fromio(saved_sram, sram, sram_size);
 }
@@ -103,6 +113,8 @@ static void lite5200_restore_regs(void)
        int i;
        _memcpy_toio(sram, saved_sram, sram_size);
 
+       /* PCI Configuration */
+       _memcpy_toio(pci, spci, 0x200);
 
        /*
         * GPIOs. Interrupt Master Enable has higher address then other
index 8a07f41..bf07b6f 100644 (file)
@@ -383,6 +383,7 @@ config VMI
 config KVM_CLOCK
        bool "KVM paravirtualized clock"
        select PARAVIRT
+       select PARAVIRT_CLOCK
        depends on !(X86_VISWS || X86_VOYAGER)
        help
          Turning on this option will allow you to run a paravirtualized clock
@@ -410,6 +411,10 @@ config PARAVIRT
          over full virtualization.  However, when run without a hypervisor
          the kernel is theoretically slower and slightly larger.
 
+config PARAVIRT_CLOCK
+       bool
+       default n
+
 endif
 
 config MEMTEST_BOOTPARAM
index 5e618c3..77807d4 100644 (file)
@@ -82,6 +82,7 @@ obj-$(CONFIG_VMI)             += vmi_32.o vmiclock_32.o
 obj-$(CONFIG_KVM_GUEST)                += kvm.o
 obj-$(CONFIG_KVM_CLOCK)                += kvmclock.o
 obj-$(CONFIG_PARAVIRT)         += paravirt.o paravirt_patch_$(BITS).o
+obj-$(CONFIG_PARAVIRT_CLOCK)   += pvclock.o
 
 obj-$(CONFIG_PCSPKR_PLATFORM)  += pcspeaker.o
 
index 08a3098..87edf1c 100644 (file)
@@ -18,6 +18,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/kvm_para.h>
+#include <asm/pvclock.h>
 #include <asm/arch_hooks.h>
 #include <asm/msr.h>
 #include <asm/apic.h>
@@ -36,18 +37,9 @@ static int parse_no_kvmclock(char *arg)
 early_param("no-kvmclock", parse_no_kvmclock);
 
 /* The hypervisor will put information about time periodically here */
-static DEFINE_PER_CPU_SHARED_ALIGNED(struct kvm_vcpu_time_info, hv_clock);
-#define get_clock(cpu, field) per_cpu(hv_clock, cpu).field
+static DEFINE_PER_CPU_SHARED_ALIGNED(struct pvclock_vcpu_time_info, hv_clock);
+static struct pvclock_wall_clock wall_clock;
 
-static inline u64 kvm_get_delta(u64 last_tsc)
-{
-       int cpu = smp_processor_id();
-       u64 delta = native_read_tsc() - last_tsc;
-       return (delta * get_clock(cpu, tsc_to_system_mul)) >> KVM_SCALE;
-}
-
-static struct kvm_wall_clock wall_clock;
-static cycle_t kvm_clock_read(void);
 /*
  * The wallclock is the time of day when we booted. Since then, some time may
  * have elapsed since the hypervisor wrote the data. So we try to account for
@@ -55,64 +47,37 @@ static cycle_t kvm_clock_read(void);
  */
 static unsigned long kvm_get_wallclock(void)
 {
-       u32 wc_sec, wc_nsec;
-       u64 delta;
+       struct pvclock_vcpu_time_info *vcpu_time;
        struct timespec ts;
-       int version, nsec;
        int low, high;
 
        low = (int)__pa(&wall_clock);
        high = ((u64)__pa(&wall_clock) >> 32);
+       native_write_msr(MSR_KVM_WALL_CLOCK, low, high);
 
-       delta = kvm_clock_read();
+       vcpu_time = &get_cpu_var(hv_clock);
+       pvclock_read_wallclock(&wall_clock, vcpu_time, &ts);
+       put_cpu_var(hv_clock);
 
-       native_write_msr(MSR_KVM_WALL_CLOCK, low, high);
-       do {
-               version = wall_clock.wc_version;
-               rmb();
-               wc_sec = wall_clock.wc_sec;
-               wc_nsec = wall_clock.wc_nsec;
-               rmb();
-       } while ((wall_clock.wc_version != version) || (version & 1));
-
-       delta = kvm_clock_read() - delta;
-       delta += wc_nsec;
-       nsec = do_div(delta, NSEC_PER_SEC);
-       set_normalized_timespec(&ts, wc_sec + delta, nsec);
-       /*
-        * Of all mechanisms of time adjustment I've tested, this one
-        * was the champion!
-        */
-       return ts.tv_sec + 1;
+       return ts.tv_sec;
 }
 
 static int kvm_set_wallclock(unsigned long now)
 {
-       return 0;
+       return -1;
 }
 
-/*
- * This is our read_clock function. The host puts an tsc timestamp each time
- * it updates a new time. Without the tsc adjustment, we can have a situation
- * in which a vcpu starts to run earlier (smaller system_time), but probes
- * time later (compared to another vcpu), leading to backwards time
- */
 static cycle_t kvm_clock_read(void)
 {
-       u64 last_tsc, now;
-       int cpu;
+       struct pvclock_vcpu_time_info *src;
+       cycle_t ret;
 
-       preempt_disable();
-       cpu = smp_processor_id();
-
-       last_tsc = get_clock(cpu, tsc_timestamp);
-       now = get_clock(cpu, system_time);
-
-       now += kvm_get_delta(last_tsc);
-       preempt_enable();
-
-       return now;
+       src = &get_cpu_var(hv_clock);
+       ret = pvclock_clocksource_read(src);
+       put_cpu_var(hv_clock);
+       return ret;
 }
+
 static struct clocksource kvm_clock = {
        .name = "kvm-clock",
        .read = kvm_clock_read,
@@ -123,13 +88,14 @@ static struct clocksource kvm_clock = {
        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static int kvm_register_clock(void)
+static int kvm_register_clock(char *txt)
 {
        int cpu = smp_processor_id();
        int low, high;
        low = (int)__pa(&per_cpu(hv_clock, cpu)) | 1;
        high = ((u64)__pa(&per_cpu(hv_clock, cpu)) >> 32);
-
+       printk(KERN_INFO "kvm-clock: cpu %d, msr %x:%x, %s\n",
+              cpu, high, low, txt);
        return native_write_msr_safe(MSR_KVM_SYSTEM_TIME, low, high);
 }
 
@@ -140,12 +106,20 @@ static void kvm_setup_secondary_clock(void)
         * Now that the first cpu already had this clocksource initialized,
         * we shouldn't fail.
         */
-       WARN_ON(kvm_register_clock());
+       WARN_ON(kvm_register_clock("secondary cpu clock"));
        /* ok, done with our trickery, call native */
        setup_secondary_APIC_clock();
 }
 #endif
 
+#ifdef CONFIG_SMP
+void __init kvm_smp_prepare_boot_cpu(void)
+{
+       WARN_ON(kvm_register_clock("primary cpu clock"));
+       native_smp_prepare_boot_cpu();
+}
+#endif
+
 /*
  * After the clock is registered, the host will keep writing to the
  * registered memory location. If the guest happens to shutdown, this memory
@@ -174,13 +148,16 @@ void __init kvmclock_init(void)
                return;
 
        if (kvmclock && kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE)) {
-               if (kvm_register_clock())
+               if (kvm_register_clock("boot clock"))
                        return;
                pv_time_ops.get_wallclock = kvm_get_wallclock;
                pv_time_ops.set_wallclock = kvm_set_wallclock;
                pv_time_ops.sched_clock = kvm_clock_read;
 #ifdef CONFIG_X86_LOCAL_APIC
                pv_apic_ops.setup_secondary_clock = kvm_setup_secondary_clock;
+#endif
+#ifdef CONFIG_SMP
+               smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu;
 #endif
                machine_ops.shutdown  = kvm_shutdown;
 #ifdef CONFIG_KEXEC
diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c
new file mode 100644 (file)
index 0000000..05fbe9a
--- /dev/null
@@ -0,0 +1,141 @@
+/*  paravirtual clock -- common code used by kvm/xen
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <linux/kernel.h>
+#include <linux/percpu.h>
+#include <asm/pvclock.h>
+
+/*
+ * These are perodically updated
+ *    xen: magic shared_info page
+ *    kvm: gpa registered via msr
+ * and then copied here.
+ */
+struct pvclock_shadow_time {
+       u64 tsc_timestamp;     /* TSC at last update of time vals.  */
+       u64 system_timestamp;  /* Time, in nanosecs, since boot.    */
+       u32 tsc_to_nsec_mul;
+       int tsc_shift;
+       u32 version;
+};
+
+/*
+ * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
+ * yielding a 64-bit result.
+ */
+static inline u64 scale_delta(u64 delta, u32 mul_frac, int shift)
+{
+       u64 product;
+#ifdef __i386__
+       u32 tmp1, tmp2;
+#endif
+
+       if (shift < 0)
+               delta >>= -shift;
+       else
+               delta <<= shift;
+
+#ifdef __i386__
+       __asm__ (
+               "mul  %5       ; "
+               "mov  %4,%%eax ; "
+               "mov  %%edx,%4 ; "
+               "mul  %5       ; "
+               "xor  %5,%5    ; "
+               "add  %4,%%eax ; "
+               "adc  %5,%%edx ; "
+               : "=A" (product), "=r" (tmp1), "=r" (tmp2)
+               : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
+#elif __x86_64__
+       __asm__ (
+               "mul %%rdx ; shrd $32,%%rdx,%%rax"
+               : "=a" (product) : "0" (delta), "d" ((u64)mul_frac) );
+#else
+#error implement me!
+#endif
+
+       return product;
+}
+
+static u64 pvclock_get_nsec_offset(struct pvclock_shadow_time *shadow)
+{
+       u64 delta = native_read_tsc() - shadow->tsc_timestamp;
+       return scale_delta(delta, shadow->tsc_to_nsec_mul, shadow->tsc_shift);
+}
+
+/*
+ * Reads a consistent set of time-base values from hypervisor,
+ * into a shadow data area.
+ */
+static unsigned pvclock_get_time_values(struct pvclock_shadow_time *dst,
+                                       struct pvclock_vcpu_time_info *src)
+{
+       do {
+               dst->version = src->version;
+               rmb();          /* fetch version before data */
+               dst->tsc_timestamp     = src->tsc_timestamp;
+               dst->system_timestamp  = src->system_time;
+               dst->tsc_to_nsec_mul   = src->tsc_to_system_mul;
+               dst->tsc_shift         = src->tsc_shift;
+               rmb();          /* test version after fetching data */
+       } while ((src->version & 1) || (dst->version != src->version));
+
+       return dst->version;
+}
+
+cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src)
+{
+       struct pvclock_shadow_time shadow;
+       unsigned version;
+       cycle_t ret, offset;
+
+       do {
+               version = pvclock_get_time_values(&shadow, src);
+               barrier();
+               offset = pvclock_get_nsec_offset(&shadow);
+               ret = shadow.system_timestamp + offset;
+               barrier();
+       } while (version != src->version);
+
+       return ret;
+}
+
+void pvclock_read_wallclock(struct pvclock_wall_clock *wall_clock,
+                           struct pvclock_vcpu_time_info *vcpu_time,
+                           struct timespec *ts)
+{
+       u32 version;
+       u64 delta;
+       struct timespec now;
+
+       /* get wallclock at system boot */
+       do {
+               version = wall_clock->version;
+               rmb();          /* fetch version before time */
+               now.tv_sec  = wall_clock->sec;
+               now.tv_nsec = wall_clock->nsec;
+               rmb();          /* fetch time before checking version */
+       } while ((wall_clock->version & 1) || (version != wall_clock->version));
+
+       delta = pvclock_clocksource_read(vcpu_time);    /* time since system boot */
+       delta += now.tv_sec * (u64)NSEC_PER_SEC + now.tv_nsec;
+
+       now.tv_nsec = do_div(delta, NSEC_PER_SEC);
+       now.tv_sec = delta;
+
+       set_normalized_timespec(ts, now.tv_sec, now.tv_nsec);
+}
index f2f5d26..3829aa7 100644 (file)
@@ -200,9 +200,12 @@ int __pit_timer_fn(struct kvm_kpit_state *ps)
 
        atomic_inc(&pt->pending);
        smp_mb__after_atomic_inc();
-       if (vcpu0 && waitqueue_active(&vcpu0->wq)) {
-               vcpu0->arch.mp_state = KVM_MP_STATE_RUNNABLE;
-               wake_up_interruptible(&vcpu0->wq);
+       if (vcpu0) {
+               set_bit(KVM_REQ_PENDING_TIMER, &vcpu0->requests);
+               if (waitqueue_active(&vcpu0->wq)) {
+                       vcpu0->arch.mp_state = KVM_MP_STATE_RUNNABLE;
+                       wake_up_interruptible(&vcpu0->wq);
+               }
        }
 
        pt->timer.expires = ktime_add_ns(pt->timer.expires, pt->period);
index c297c50..ebc03f5 100644 (file)
@@ -940,6 +940,7 @@ static int __apic_timer_fn(struct kvm_lapic *apic)
        wait_queue_head_t *q = &apic->vcpu->wq;
 
        atomic_inc(&apic->timer.pending);
+       set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
        if (waitqueue_active(q)) {
                apic->vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
                wake_up_interruptible(q);
index ee3f530..7e7c396 100644 (file)
@@ -640,6 +640,7 @@ static void rmap_write_protect(struct kvm *kvm, u64 gfn)
                        rmap_remove(kvm, spte);
                        --kvm->stat.lpages;
                        set_shadow_pte(spte, shadow_trap_nonpresent_pte);
+                       spte = NULL;
                        write_protected = 1;
                }
                spte = rmap_next(kvm, rmapp, spte);
@@ -1082,10 +1083,6 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
                struct kvm_mmu_page *shadow;
 
                spte |= PT_WRITABLE_MASK;
-               if (user_fault) {
-                       mmu_unshadow(vcpu->kvm, gfn);
-                       goto unshadowed;
-               }
 
                shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
                if (shadow ||
@@ -1102,8 +1099,6 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
                }
        }
 
-unshadowed:
-
        if (pte_access & ACC_WRITE_MASK)
                mark_page_dirty(vcpu->kvm, gfn);
 
@@ -1580,11 +1575,13 @@ static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
                                  u64 *spte,
                                  const void *new)
 {
-       if ((sp->role.level != PT_PAGE_TABLE_LEVEL)
-           && !vcpu->arch.update_pte.largepage) {
-               ++vcpu->kvm->stat.mmu_pde_zapped;
-               return;
-       }
+       if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
+               if (!vcpu->arch.update_pte.largepage ||
+                   sp->role.glevels == PT32_ROOT_LEVEL) {
+                       ++vcpu->kvm->stat.mmu_pde_zapped;
+                       return;
+               }
+        }
 
        ++vcpu->kvm->stat.mmu_pte_updated;
        if (sp->role.glevels == PT32_ROOT_LEVEL)
index 02efbe7..540e951 100644 (file)
@@ -566,7 +566,7 @@ static void vmx_save_host_state(struct kvm_vcpu *vcpu)
        load_transition_efer(vmx);
 }
 
-static void vmx_load_host_state(struct vcpu_vmx *vmx)
+static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 {
        unsigned long flags;
 
@@ -596,6 +596,13 @@ static void vmx_load_host_state(struct vcpu_vmx *vmx)
        reload_host_efer(vmx);
 }
 
+static void vmx_load_host_state(struct vcpu_vmx *vmx)
+{
+       preempt_disable();
+       __vmx_load_host_state(vmx);
+       preempt_enable();
+}
+
 /*
  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
  * vcpu mutex is already taken.
@@ -654,7 +661,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 
 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 {
-       vmx_load_host_state(to_vmx(vcpu));
+       __vmx_load_host_state(to_vmx(vcpu));
 }
 
 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
@@ -884,11 +891,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
        switch (msr_index) {
 #ifdef CONFIG_X86_64
        case MSR_EFER:
+               vmx_load_host_state(vmx);
                ret = kvm_set_msr_common(vcpu, msr_index, data);
-               if (vmx->host_state.loaded) {
-                       reload_host_efer(vmx);
-                       load_transition_efer(vmx);
-               }
                break;
        case MSR_FS_BASE:
                vmcs_writel(GUEST_FS_BASE, data);
@@ -910,11 +914,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
                guest_write_tsc(data);
                break;
        default:
+               vmx_load_host_state(vmx);
                msr = find_msr_entry(vmx, msr_index);
                if (msr) {
                        msr->data = data;
-                       if (vmx->host_state.loaded)
-                               load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
                        break;
                }
                ret = kvm_set_msr_common(vcpu, msr_index, data);
index 00acf13..63a77ca 100644 (file)
@@ -492,8 +492,8 @@ static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
 {
        static int version;
-       struct kvm_wall_clock wc;
-       struct timespec wc_ts;
+       struct pvclock_wall_clock wc;
+       struct timespec now, sys, boot;
 
        if (!wall_clock)
                return;
@@ -502,10 +502,19 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
 
        kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
 
-       wc_ts = current_kernel_time();
-       wc.wc_sec = wc_ts.tv_sec;
-       wc.wc_nsec = wc_ts.tv_nsec;
-       wc.wc_version = version;
+       /*
+        * The guest calculates current wall clock time by adding
+        * system time (updated by kvm_write_guest_time below) to the
+        * wall clock specified here.  guest system time equals host
+        * system time for us, thus we must fill in host boot time here.
+        */
+       now = current_kernel_time();
+       ktime_get_ts(&sys);
+       boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
+
+       wc.sec = boot.tv_sec;
+       wc.nsec = boot.tv_nsec;
+       wc.version = version;
 
        kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
 
@@ -513,6 +522,45 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
        kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
 }
 
+static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
+{
+       uint32_t quotient, remainder;
+
+       /* Don't try to replace with do_div(), this one calculates
+        * "(dividend << 32) / divisor" */
+       __asm__ ( "divl %4"
+                 : "=a" (quotient), "=d" (remainder)
+                 : "0" (0), "1" (dividend), "r" (divisor) );
+       return quotient;
+}
+
+static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
+{
+       uint64_t nsecs = 1000000000LL;
+       int32_t  shift = 0;
+       uint64_t tps64;
+       uint32_t tps32;
+
+       tps64 = tsc_khz * 1000LL;
+       while (tps64 > nsecs*2) {
+               tps64 >>= 1;
+               shift--;
+       }
+
+       tps32 = (uint32_t)tps64;
+       while (tps32 <= (uint32_t)nsecs) {
+               tps32 <<= 1;
+               shift++;
+       }
+
+       hv_clock->tsc_shift = shift;
+       hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
+
+       pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
+                __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
+                hv_clock->tsc_to_system_mul);
+}
+
 static void kvm_write_guest_time(struct kvm_vcpu *v)
 {
        struct timespec ts;
@@ -523,6 +571,11 @@ static void kvm_write_guest_time(struct kvm_vcpu *v)
        if ((!vcpu->time_page))
                return;
 
+       if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
+               kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
+               vcpu->hv_clock_tsc_khz = tsc_khz;
+       }
+
        /* Keep irq disabled to prevent changes to the clock */
        local_irq_save(flags);
        kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
@@ -537,14 +590,14 @@ static void kvm_write_guest_time(struct kvm_vcpu *v)
        /*
         * The interface expects us to write an even number signaling that the
         * update is finished. Since the guest won't see the intermediate
-        * state, we just write "2" at the end
+        * state, we just increase by 2 at the end.
         */
-       vcpu->hv_clock.version = 2;
+       vcpu->hv_clock.version += 2;
 
        shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
 
        memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
-               sizeof(vcpu->hv_clock));
+              sizeof(vcpu->hv_clock));
 
        kunmap_atomic(shared_kaddr, KM_USER0);
 
@@ -599,10 +652,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                /* ...but clean it before doing the actual write */
                vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
 
-               vcpu->arch.hv_clock.tsc_to_system_mul =
-                                       clocksource_khz2mult(tsc_khz, 22);
-               vcpu->arch.hv_clock.tsc_shift = 22;
-
                down_read(&current->mm->mmap_sem);
                vcpu->arch.time_page =
                                gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
@@ -2759,6 +2808,8 @@ again:
        if (vcpu->requests) {
                if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
                        __kvm_migrate_timers(vcpu);
+               if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
+                       kvm_x86_ops->tlb_flush(vcpu);
                if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
                                       &vcpu->requests)) {
                        kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
@@ -2772,6 +2823,7 @@ again:
                }
        }
 
+       clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
        kvm_inject_pending_timer_irqs(vcpu);
 
        preempt_disable();
@@ -2781,21 +2833,13 @@ again:
 
        local_irq_disable();
 
-       if (need_resched()) {
+       if (vcpu->requests || need_resched()) {
                local_irq_enable();
                preempt_enable();
                r = 1;
                goto out;
        }
 
-       if (vcpu->requests)
-               if (test_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) {
-                       local_irq_enable();
-                       preempt_enable();
-                       r = 1;
-                       goto out;
-               }
-
        if (signal_pending(current)) {
                local_irq_enable();
                preempt_enable();
@@ -2825,9 +2869,6 @@ again:
 
        kvm_guest_enter();
 
-       if (vcpu->requests)
-               if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
-                       kvm_x86_ops->tlb_flush(vcpu);
 
        KVMTRACE_0D(VMENTRY, vcpu, entryexit);
        kvm_x86_ops->run(vcpu, kvm_run);
index 525b108..6c388e5 100644 (file)
@@ -5,6 +5,7 @@
 config XEN
        bool "Xen guest support"
        select PARAVIRT
+       select PARAVIRT_CLOCK
        depends on X86_32
        depends on X86_CMPXCHG && X86_TSC && X86_PAE && !(X86_VISWS || X86_VOYAGER)
        help
index 52b2e38..41e2175 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/math64.h>
 
+#include <asm/pvclock.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 
 
 static cycle_t xen_clocksource_read(void);
 
-/* These are perodically updated in shared_info, and then copied here. */
-struct shadow_time_info {
-       u64 tsc_timestamp;     /* TSC at last update of time vals.  */
-       u64 system_timestamp;  /* Time, in nanosecs, since boot.    */
-       u32 tsc_to_nsec_mul;
-       int tsc_shift;
-       u32 version;
-};
-
-static DEFINE_PER_CPU(struct shadow_time_info, shadow_time);
-
 /* runstate info updated by Xen */
 static DEFINE_PER_CPU(struct vcpu_runstate_info, runstate);
 
@@ -211,7 +201,7 @@ unsigned long long xen_sched_clock(void)
 unsigned long xen_cpu_khz(void)
 {
        u64 xen_khz = 1000000ULL << 32;
-       const struct vcpu_time_info *info =
+       const struct pvclock_vcpu_time_info *info =
                &HYPERVISOR_shared_info->vcpu_info[0].time;
 
        do_div(xen_khz, info->tsc_to_system_mul);
@@ -223,121 +213,26 @@ unsigned long xen_cpu_khz(void)
        return xen_khz;
 }
 
-/*
- * Reads a consistent set of time-base values from Xen, into a shadow data
- * area.
- */
-static unsigned get_time_values_from_xen(void)
-{
-       struct vcpu_time_info   *src;
-       struct shadow_time_info *dst;
-
-       /* src is shared memory with the hypervisor, so we need to
-          make sure we get a consistent snapshot, even in the face of
-          being preempted. */
-       src = &__get_cpu_var(xen_vcpu)->time;
-       dst = &__get_cpu_var(shadow_time);
-
-       do {
-               dst->version = src->version;
-               rmb();          /* fetch version before data */
-               dst->tsc_timestamp     = src->tsc_timestamp;
-               dst->system_timestamp  = src->system_time;
-               dst->tsc_to_nsec_mul   = src->tsc_to_system_mul;
-               dst->tsc_shift         = src->tsc_shift;
-               rmb();          /* test version after fetching data */
-       } while ((src->version & 1) | (dst->version ^ src->version));
-
-       return dst->version;
-}
-
-/*
- * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
- * yielding a 64-bit result.
- */
-static inline u64 scale_delta(u64 delta, u32 mul_frac, int shift)
-{
-       u64 product;
-#ifdef __i386__
-       u32 tmp1, tmp2;
-#endif
-
-       if (shift < 0)
-               delta >>= -shift;
-       else
-               delta <<= shift;
-
-#ifdef __i386__
-       __asm__ (
-               "mul  %5       ; "
-               "mov  %4,%%eax ; "
-               "mov  %%edx,%4 ; "
-               "mul  %5       ; "
-               "xor  %5,%5    ; "
-               "add  %4,%%eax ; "
-               "adc  %5,%%edx ; "
-               : "=A" (product), "=r" (tmp1), "=r" (tmp2)
-               : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
-#elif __x86_64__
-       __asm__ (
-               "mul %%rdx ; shrd $32,%%rdx,%%rax"
-               : "=a" (product) : "0" (delta), "d" ((u64)mul_frac) );
-#else
-#error implement me!
-#endif
-
-       return product;
-}
-
-static u64 get_nsec_offset(struct shadow_time_info *shadow)
-{
-       u64 now, delta;
-       now = native_read_tsc();
-       delta = now - shadow->tsc_timestamp;
-       return scale_delta(delta, shadow->tsc_to_nsec_mul, shadow->tsc_shift);
-}
-
 static cycle_t xen_clocksource_read(void)
 {
-       struct shadow_time_info *shadow = &get_cpu_var(shadow_time);
+        struct pvclock_vcpu_time_info *src;
        cycle_t ret;
-       unsigned version;
-
-       do {
-               version = get_time_values_from_xen();
-               barrier();
-               ret = shadow->system_timestamp + get_nsec_offset(shadow);
-               barrier();
-       } while (version != __get_cpu_var(xen_vcpu)->time.version);
-
-       put_cpu_var(shadow_time);
 
+       src = &get_cpu_var(xen_vcpu)->time;
+       ret = pvclock_clocksource_read(src);
+       put_cpu_var(xen_vcpu);
        return ret;
 }
 
 static void xen_read_wallclock(struct timespec *ts)
 {
-       const struct shared_info *s = HYPERVISOR_shared_info;
-       u32 version;
-       u64 delta;
-       struct timespec now;
-
-       /* get wallclock at system boot */
-       do {
-               version = s->wc_version;
-               rmb();          /* fetch version before time */
-               now.tv_sec  = s->wc_sec;
-               now.tv_nsec = s->wc_nsec;
-               rmb();          /* fetch time before checking version */
-       } while ((s->wc_version & 1) | (version ^ s->wc_version));
+       struct shared_info *s = HYPERVISOR_shared_info;
+       struct pvclock_wall_clock *wall_clock = &(s->wc);
+        struct pvclock_vcpu_time_info *vcpu_time;
 
-       delta = xen_clocksource_read(); /* time since system boot */
-       delta += now.tv_sec * (u64)NSEC_PER_SEC + now.tv_nsec;
-
-       now.tv_nsec = do_div(delta, NSEC_PER_SEC);
-       now.tv_sec = delta;
-
-       set_normalized_timespec(ts, now.tv_sec, now.tv_nsec);
+       vcpu_time = &get_cpu_var(xen_vcpu)->time;
+       pvclock_read_wallclock(wall_clock, vcpu_time, ts);
+       put_cpu_var(xen_vcpu);
 }
 
 unsigned long xen_get_wallclock(void)
@@ -345,7 +240,6 @@ unsigned long xen_get_wallclock(void)
        struct timespec ts;
 
        xen_read_wallclock(&ts);
-
        return ts.tv_sec;
 }
 
@@ -569,8 +463,6 @@ __init void xen_time_init(void)
 {
        int cpu = smp_processor_id();
 
-       get_time_values_from_xen();
-
        clocksource_register(&xen_clocksource);
 
        if (HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL) == 0) {
index 5b73f6a..831883b 100644 (file)
@@ -233,6 +233,9 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
 
        device = ac->device;
        switch (event) {
+       default:
+               ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+                                 "Unsupported event [0x%x]\n", event));
        case ACPI_AC_NOTIFY_STATUS:
        case ACPI_NOTIFY_BUS_CHECK:
        case ACPI_NOTIFY_DEVICE_CHECK:
@@ -244,11 +247,6 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
 #ifdef CONFIG_ACPI_SYSFS_POWER
                kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE);
 #endif
-               break;
-       default:
-               ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-                                 "Unsupported event [0x%x]\n", event));
-               break;
        }
 
        return;
index 26038c2..61b6c5b 100644 (file)
@@ -377,6 +377,9 @@ static int __init bay_init(void)
 
        INIT_LIST_HEAD(&drive_bays);
 
+       if (acpi_disabled)
+               return -ENODEV;
+
        /* look for dockable drive bays */
        acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
                ACPI_UINT32_MAX, find_bay, &bays, NULL);
index 96c542f..bb7c51f 100644 (file)
@@ -917,6 +917,9 @@ static int __init dock_init(void)
 
        dock_station = NULL;
 
+       if (acpi_disabled)
+               return 0;
+
        /* look for a dock station */
        acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
                            ACPI_UINT32_MAX, find_dock, &num, NULL);
index 2808dc6..9b227d4 100644 (file)
@@ -333,6 +333,9 @@ static int __init acpi_rtc_init(void)
 {
        struct device *dev = get_rtc_dev();
 
+       if (acpi_disabled)
+               return 0;
+
        if (dev) {
                rtc_wake_setup();
                rtc_info.wake_on = rtc_wake_on;
index 5e5dda3..d089c45 100644 (file)
@@ -1713,7 +1713,8 @@ acpi_video_bus_get_devices(struct acpi_video_bus *video,
 
                status = acpi_video_bus_get_one_device(dev, video);
                if (ACPI_FAILURE(status)) {
-                       ACPI_EXCEPTION((AE_INFO, status, "Cant attach device"));
+                       ACPI_DEBUG_PRINT((ACPI_DB_WARN,
+                                       "Cant attach device"));
                        continue;
                }
        }
index 9bf2986..ae84949 100644 (file)
@@ -651,9 +651,17 @@ config PATA_WINBOND_VLB
          Support for the Winbond W83759A controller on Vesa Local Bus
          systems.
 
+config HAVE_PATA_PLATFORM
+       bool
+       help
+         This is an internal configuration node for any machine that
+         uses pata-platform driver to enable the relevant driver in the
+         configuration structure without having to submit endless patches
+         to update the PATA_PLATFORM entry.
+
 config PATA_PLATFORM
        tristate "Generic platform device PATA support"
-       depends on EMBEDDED || ARCH_RPC || PPC
+       depends on EMBEDDED || ARCH_RPC || PPC || HAVE_PATA_PLATFORM
        help
          This option enables support for generic directly connected ATA
          devices commonly found on embedded systems.
index 966ab40..6a4a2a2 100644 (file)
@@ -90,6 +90,7 @@ enum {
        board_ahci_mv           = 4,
        board_ahci_sb700        = 5,
        board_ahci_mcp65        = 6,
+       board_ahci_nopmp        = 7,
 
        /* global controller registers */
        HOST_CAP                = 0x00, /* host capabilities */
@@ -401,6 +402,14 @@ static const struct ata_port_info ahci_port_info[] = {
                .udma_mask      = ATA_UDMA6,
                .port_ops       = &ahci_ops,
        },
+       /* board_ahci_nopmp */
+       {
+               AHCI_HFLAGS     (AHCI_HFLAG_NO_PMP),
+               .flags          = AHCI_FLAG_COMMON,
+               .pio_mask       = 0x1f, /* pio0-4 */
+               .udma_mask      = ATA_UDMA6,
+               .port_ops       = &ahci_ops,
+       },
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
@@ -525,9 +534,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci },            /* MCP7B */
 
        /* SiS */
-       { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
-       { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
-       { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
+       { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp },          /* SiS 966 */
+       { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp },          /* SiS 968 */
+       { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp },          /* SiS 968 */
 
        /* Marvell */
        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
@@ -653,6 +662,14 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
                cap &= ~HOST_CAP_PMP;
        }
 
+       if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
+           port_map != 1) {
+               dev_printk(KERN_INFO, &pdev->dev,
+                          "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
+                          port_map, 1);
+               port_map = 1;
+       }
+
        /*
         * Temporary Marvell 6145 hack: PATA port presence
         * is asserted through the standard AHCI port
index 81b7ae3..a90ae03 100644 (file)
@@ -1042,6 +1042,13 @@ static int piix_broken_suspend(void)
                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
                        },
                },
+               {
+                       .ident = "TECRA M4",
+                       .matches = {
+                               DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                               DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
+                       },
+               },
                {
                        .ident = "TECRA M5",
                        .matches = {
index cc816ca..303fc0d 100644 (file)
@@ -4297,7 +4297,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
 }
 
 /**
- *     ata_check_atapi_dma - Check whether ATAPI DMA can be supported
+ *     atapi_check_dma - Check whether ATAPI DMA can be supported
  *     @qc: Metadata associated with taskfile to check
  *
  *     Allow low-level driver to filter ATA PACKET commands, returning
@@ -4310,7 +4310,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
  *     RETURNS: 0 when ATAPI DMA can be used
  *               nonzero otherwise
  */
-int ata_check_atapi_dma(struct ata_queued_cmd *qc)
+int atapi_check_dma(struct ata_queued_cmd *qc)
 {
        struct ata_port *ap = qc->ap;
 
index 2e6e162..57a4364 100644 (file)
@@ -2343,8 +2343,8 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
 {
        struct scsi_cmnd *scmd = qc->scsicmd;
        struct ata_device *dev = qc->dev;
-       int using_pio = (dev->flags & ATA_DFLAG_PIO);
        int nodata = (scmd->sc_data_direction == DMA_NONE);
+       int using_pio = !nodata && (dev->flags & ATA_DFLAG_PIO);
        unsigned int nbytes;
 
        memset(qc->cdb, 0, dev->cdb_len);
@@ -2362,7 +2362,7 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
        ata_qc_set_pc_nbytes(qc);
 
        /* check whether ATAPI DMA is safe */
-       if (!using_pio && ata_check_atapi_dma(qc))
+       if (!nodata && !using_pio && atapi_check_dma(qc))
                using_pio = 1;
 
        /* Some controller variants snoop this value for Packet
@@ -2402,13 +2402,11 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
        qc->tf.lbam = (nbytes & 0xFF);
        qc->tf.lbah = (nbytes >> 8);
 
-       if (using_pio || nodata) {
-               /* no data, or PIO data xfer */
-               if (nodata)
-                       qc->tf.protocol = ATAPI_PROT_NODATA;
-               else
-                       qc->tf.protocol = ATAPI_PROT_PIO;
-       } else {
+       if (nodata)
+               qc->tf.protocol = ATAPI_PROT_NODATA;
+       else if (using_pio)
+               qc->tf.protocol = ATAPI_PROT_PIO;
+       else {
                /* DMA data xfer */
                qc->tf.protocol = ATAPI_PROT_DMA;
                qc->tf.feature |= ATAPI_PKT_DMA;
index 4514283..1cf803a 100644 (file)
@@ -106,7 +106,7 @@ extern void ata_sg_clean(struct ata_queued_cmd *qc);
 extern void ata_qc_free(struct ata_queued_cmd *qc);
 extern void ata_qc_issue(struct ata_queued_cmd *qc);
 extern void __ata_qc_complete(struct ata_queued_cmd *qc);
-extern int ata_check_atapi_dma(struct ata_queued_cmd *qc);
+extern int atapi_check_dma(struct ata_queued_cmd *qc);
 extern void swap_buf_le16(u16 *buf, unsigned int buf_words);
 extern void ata_dev_init(struct ata_device *dev);
 extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp);
index 3d39f9d..41b4361 100644 (file)
@@ -414,6 +414,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
        PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
        PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
        PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2      ", 0xe37be2b5, 0x8671043b),
+       PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
        PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
        PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
        PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
@@ -424,6 +425,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
        PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
        PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
        PCMCIA_DEVICE_PROD_ID1("TRANSCEND    512M   ", 0xd0909443),
+       PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
        PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
        PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
        PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
index 60391e9..28092bc 100644 (file)
@@ -1322,6 +1322,9 @@ static int mv_port_start(struct ata_port *ap)
                goto out_port_free_dma_mem;
        memset(pp->crpb, 0, MV_CRPB_Q_SZ);
 
+       /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
+       if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
+               ap->flags |= ATA_FLAG_AN;
        /*
         * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
         * For later hardware, we need one unique sg_tbl per NCQ tag.
@@ -1592,6 +1595,24 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
 
        if ((qc->tf.protocol != ATA_PROT_DMA) &&
            (qc->tf.protocol != ATA_PROT_NCQ)) {
+               static int limit_warnings = 10;
+               /*
+                * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
+                *
+                * Someday, we might implement special polling workarounds
+                * for these, but it all seems rather unnecessary since we
+                * normally use only DMA for commands which transfer more
+                * than a single block of data.
+                *
+                * Much of the time, this could just work regardless.
+                * So for now, just log the incident, and allow the attempt.
+                */
+               if (limit_warnings && (qc->nbytes / qc->sect_size) > 1) {
+                       --limit_warnings;
+                       ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
+                                       ": attempting PIO w/multiple DRQ: "
+                                       "this may fail due to h/w errata\n");
+               }
                /*
                 * We're about to send a non-EDMA capable command to the
                 * port.  Turn off EDMA so there won't be problems accessing
index 1ae64bb..df70264 100644 (file)
@@ -948,7 +948,7 @@ static void intel_i9xx_setup_flush(void)
        intel_private.ifp_resource.flags = IORESOURCE_MEM;
 
        /* Setup chipset flush for 915 */
-       if (IS_I965 || IS_G33) {
+       if (IS_I965 || IS_G33 || IS_G4X) {
                intel_i965_g33_setup_chipset_flush();
        } else {
                intel_i915_setup_chipset_flush();
index b710426..c533d0c 100644 (file)
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
                for (i = 0; i < pages; i++) {
                        if (!entry->busaddr[i])
                                break;
-                       pci_unmap_single(dev->pdev, entry->busaddr[i],
+                       pci_unmap_page(dev->pdev, entry->busaddr[i],
                                         PAGE_SIZE, PCI_DMA_TODEVICE);
                }
 
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
 
        for (i = 0; i < pages; i++) {
                /* we need to support large memory configurations */
-               entry->busaddr[i] = pci_map_single(dev->pdev,
-                                                  page_address(entry->
-                                                               pagelist[i]),
-                                                  PAGE_SIZE, PCI_DMA_TODEVICE);
+               entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
+                                                0, PAGE_SIZE, PCI_DMA_TODEVICE);
                if (entry->busaddr[i] == 0) {
                        DRM_ERROR("unable to map PCIGART pages!\n");
                        drm_ati_pcigart_cleanup(dev, gart_info);
index 3a05c6d..38d3c6b 100644 (file)
@@ -628,7 +628,7 @@ struct drm_set_version {
 #define DRM_IOCTL_AGP_BIND             DRM_IOW( 0x36, struct drm_agp_binding)
 #define DRM_IOCTL_AGP_UNBIND           DRM_IOW( 0x37, struct drm_agp_binding)
 
-#define DRM_IOCTL_SG_ALLOC             DRM_IOW0x38, struct drm_scatter_gather)
+#define DRM_IOCTL_SG_ALLOC             DRM_IOWR(0x38, struct drm_scatter_gather)
 #define DRM_IOCTL_SG_FREE              DRM_IOW( 0x39, struct drm_scatter_gather)
 
 #define DRM_IOCTL_WAIT_VBLANK          DRM_IOWR(0x3a, union drm_wait_vblank)
index fc54140..5641387 100644 (file)
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
        if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
            (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
                ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
-       else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE))
+       else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
                ioctl = &drm_ioctls[nr];
-       else
+               cmd = ioctl->cmd;
+       } else
                goto err_i1;
 
+       /* Do not trust userspace, use our own definition */
        func = ioctl->func;
        /* is there a local override? */
        if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
                func = dev->driver->dma_ioctl;
 
-
        if (!func) {
                DRM_DEBUG("no function\n");
                retcode = -EINVAL;
index a6a499f..135bd19 100644 (file)
        {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
        {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
-       {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-       {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-       {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-       {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+       {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+       {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+       {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+       {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
        {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-       {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-       {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-       {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-       {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+       {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+       {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
        {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
        {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
        {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
        {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+       {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+       {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+       {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
        {0, 0, 0}
index e8f3d68..93aed1c 100644 (file)
@@ -389,6 +389,7 @@ static int i915_resume(struct drm_device *dev)
        pci_restore_state(dev->pdev);
        if (pci_enable_device(dev->pdev))
                return -1;
+       pci_set_master(dev->pdev);
 
        pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 
index 1b20f7c..d7326d9 100644 (file)
@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
                       (dev)->pci_device == 0x29A2 || \
                       (dev)->pci_device == 0x2A02 || \
                       (dev)->pci_device == 0x2A12 || \
-                      (dev)->pci_device == 0x2A42)
+                      (dev)->pci_device == 0x2A42 || \
+                      (dev)->pci_device == 0x2E02 || \
+                      (dev)->pci_device == 0x2E12 || \
+                      (dev)->pci_device == 0x2E22)
 
 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 
 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
 
+#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
+                    (dev)->pci_device == 0x2E12 || \
+                    (dev)->pci_device == 0x2E22)
+
 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 || \
                        (dev)->pci_device == 0x29B2 ||  \
                        (dev)->pci_device == 0x29D2)
@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
                        IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
 
-#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev))
+#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
index f7f16e7..df03611 100644 (file)
@@ -62,11 +62,11 @@ static void i915_vblank_tasklet(struct drm_device *dev)
        u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
        RING_LOCALS;
 
-       if (sarea_priv->front_tiled) {
+       if (IS_I965G(dev) && sarea_priv->front_tiled) {
                cmd |= XY_SRC_COPY_BLT_DST_TILED;
                dst_pitch >>= 2;
        }
-       if (sarea_priv->back_tiled) {
+       if (IS_I965G(dev) && sarea_priv->back_tiled) {
                cmd |= XY_SRC_COPY_BLT_SRC_TILED;
                src_pitch >>= 2;
        }
index f535812..702df45 100644 (file)
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
        ADD_RANGE(R300_RE_CULL_CNTL, 1);
        ADD_RANGE(0x42C0, 2);
        ADD_RANGE(R300_RS_CNTL_0, 2);
-       ADD_RANGE(R300_RS_INTERP_0, 8);
-       ADD_RANGE(R300_RS_ROUTE_0, 8);
-       ADD_RANGE(0x43A4, 2);
+
+       ADD_RANGE(R300_SC_HYPERZ, 2);
        ADD_RANGE(0x43E8, 1);
-       ADD_RANGE(R300_PFS_CNTL_0, 3);
-       ADD_RANGE(R300_PFS_NODE_0, 4);
-       ADD_RANGE(R300_PFS_TEXI_0, 64);
+
        ADD_RANGE(0x46A4, 5);
-       ADD_RANGE(R300_PFS_INSTR0_0, 64);
-       ADD_RANGE(R300_PFS_INSTR1_0, 64);
-       ADD_RANGE(R300_PFS_INSTR2_0, 64);
-       ADD_RANGE(R300_PFS_INSTR3_0, 64);
+
        ADD_RANGE(R300_RE_FOG_STATE, 1);
        ADD_RANGE(R300_FOG_COLOR_R, 3);
        ADD_RANGE(R300_PP_ALPHA_TEST, 2);
@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
        ADD_RANGE(0x4E50, 9);
        ADD_RANGE(0x4E88, 1);
        ADD_RANGE(0x4EA0, 2);
-       ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
-       ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
-       ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);    /* check offset */
-       ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
-       ADD_RANGE(0x4F28, 1);
-       ADD_RANGE(0x4F30, 2);
-       ADD_RANGE(0x4F44, 1);
-       ADD_RANGE(0x4F54, 1);
+       ADD_RANGE(R300_ZB_CNTL, 3);
+       ADD_RANGE(R300_ZB_FORMAT, 4);
+       ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);      /* check offset */
+       ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
+       ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
+       ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
 
        ADD_RANGE(R300_TX_FILTER_0, 16);
        ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
        ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 
        /* Sporadic registers used as primitives are emitted */
-       ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
+       ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
        ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
        ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
        ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 
        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
-               ADD_RANGE(0x4074, 16);
+               ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
+               ADD_RANGE(R500_US_CONFIG, 2);
+               ADD_RANGE(R500_US_CODE_ADDR, 3);
+               ADD_RANGE(R500_US_FC_CTRL, 1);
+               ADD_RANGE(R500_RS_IP_0, 16);
+               ADD_RANGE(R500_RS_INST_0, 16);
+               ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
+               ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
+               ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
+       } else {
+               ADD_RANGE(R300_PFS_CNTL_0, 3);
+               ADD_RANGE(R300_PFS_NODE_0, 4);
+               ADD_RANGE(R300_PFS_TEXI_0, 64);
+               ADD_RANGE(R300_PFS_INSTR0_0, 64);
+               ADD_RANGE(R300_PFS_INSTR1_0, 64);
+               ADD_RANGE(R300_PFS_INSTR2_0, 64);
+               ADD_RANGE(R300_PFS_INSTR3_0, 64);
+               ADD_RANGE(R300_RS_INTERP_0, 8);
+               ADD_RANGE(R300_RS_ROUTE_0, 8);
+
        }
 }
 
@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
        BEGIN_RING(6);
        OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
        OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
-       OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-       OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
+       OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
+       OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
+                R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
        OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
        OUT_RING(0x0);
        ADVANCE_RING();
@@ -828,6 +840,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
        return 0;
 }
 
+/**
+ * Uploads user-supplied vertex program instructions or parameters onto
+ * the graphics card.
+ * Called by r300_do_cp_cmdbuf.
+ */
+static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
+                                      drm_radeon_kcmd_buffer_t *cmdbuf,
+                                      drm_r300_cmd_header_t header)
+{
+       int sz;
+       int addr;
+       int type;
+       int clamp;
+       int stride;
+       RING_LOCALS;
+
+       sz = header.r500fp.count;
+       /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
+       addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
+
+       type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
+       clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
+
+       addr |= (type << 16);
+       addr |= (clamp << 17);
+
+       stride = type ? 4 : 6;
+
+       DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
+       if (!sz)
+               return 0;
+       if (sz * stride * 4 > cmdbuf->bufsz)
+               return -EINVAL;
+
+       BEGIN_RING(3 + sz * stride);
+       OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
+       OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
+       OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
+
+       ADVANCE_RING();
+
+       cmdbuf->buf += sz * stride * 4;
+       cmdbuf->bufsz -= sz * stride * 4;
+
+       return 0;
+}
+
+
 /**
  * Parses and validates a user-supplied command buffer and emits appropriate
  * commands on the DMA ring buffer.
@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
                        }
                        break;
 
+               case R300_CMD_R500FP:
+                       if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+                               DRM_ERROR("Calling r500 command on r300 card\n");
+                               ret = -EINVAL;
+                               goto cleanup;
+                       }
+                       DRM_DEBUG("R300_CMD_R500FP\n");
+                       ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
+                       if (ret) {
+                               DRM_ERROR("r300_emit_r500fp failed\n");
+                               goto cleanup;
+                       }
+                       break;
                default:
                        DRM_ERROR("bad cmd_type %i at %p\n",
                                  header.header.cmd_type,
index 8f664af..a6802f2 100644 (file)
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #              define R300_RS_ROUTE_1_UNKNOWN11         (1 << 11)
 /* END: Rasterization / Interpolators - many guesses */
 
+/* Hierarchical Z Enable */
+#define R300_SC_HYPERZ                   0x43a4
+#      define R300_SC_HYPERZ_DISABLE     (0 << 0)
+#      define R300_SC_HYPERZ_ENABLE      (1 << 0)
+#      define R300_SC_HYPERZ_MIN         (0 << 1)
+#      define R300_SC_HYPERZ_MAX         (1 << 1)
+#      define R300_SC_HYPERZ_ADJ_256     (0 << 2)
+#      define R300_SC_HYPERZ_ADJ_128     (1 << 2)
+#      define R300_SC_HYPERZ_ADJ_64      (2 << 2)
+#      define R300_SC_HYPERZ_ADJ_32      (3 << 2)
+#      define R300_SC_HYPERZ_ADJ_16      (4 << 2)
+#      define R300_SC_HYPERZ_ADJ_8       (5 << 2)
+#      define R300_SC_HYPERZ_ADJ_4       (6 << 2)
+#      define R300_SC_HYPERZ_ADJ_2       (7 << 2)
+#      define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
+#      define R300_SC_HYPERZ_HZ_Z0MIN    (1 << 5)
+#      define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
+#      define R300_SC_HYPERZ_HZ_Z0MAX    (1 << 6)
+
+#define R300_SC_EDGERULE                 0x43a8
+
 /* BEGIN: Scissors and cliprects */
 
 /* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* Guess by Vladimir.
  * Set to 0A before 3D operations, set to 02 afterwards.
  */
-#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C
+/*#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C*/
 #       define R300_RB3D_DSTCACHE_UNKNOWN_02             0x00000002
 #       define R300_RB3D_DSTCACHE_UNKNOWN_0A             0x0000000A
 
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * for this.
  * Bit (1<<8) is the "test" bit. so plain write is 6  - vd
  */
-#define R300_RB3D_ZSTENCIL_CNTL_0                   0x4F00
-#       define R300_RB3D_Z_DISABLED_1            0x00000010
-#       define R300_RB3D_Z_DISABLED_2            0x00000014
-#       define R300_RB3D_Z_TEST                  0x00000012
-#       define R300_RB3D_Z_TEST_AND_WRITE        0x00000016
-#       define R300_RB3D_Z_WRITE_ONLY           0x00000006
-
-#       define R300_RB3D_Z_TEST                  0x00000012
-#       define R300_RB3D_Z_TEST_AND_WRITE        0x00000016
-#       define R300_RB3D_Z_WRITE_ONLY           0x00000006
-#      define R300_RB3D_STENCIL_ENABLE          0x00000001
-
-#define R300_RB3D_ZSTENCIL_CNTL_1                   0x4F04
+#define R300_ZB_CNTL                             0x4F00
+#      define R300_STENCIL_ENABLE               (1 << 0)
+#      define R300_Z_ENABLE                     (1 << 1)
+#      define R300_Z_WRITE_ENABLE               (1 << 2)
+#      define R300_Z_SIGNED_COMPARE             (1 << 3)
+#      define R300_STENCIL_FRONT_BACK           (1 << 4)
+
+#define R300_ZB_ZSTENCILCNTL                   0x4f04
        /* functions */
 #      define R300_ZS_NEVER                    0
 #      define R300_ZS_LESS                     1
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #      define R300_ZS_INVERT                   5
 #      define R300_ZS_INCR_WRAP                6
 #      define R300_ZS_DECR_WRAP                7
+#      define R300_Z_FUNC_SHIFT                0
        /* front and back refer to operations done for front
           and back faces, i.e. separate stencil function support */
-#      define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT           0
-#      define R300_RB3D_ZS1_FRONT_FUNC_SHIFT           3
-#      define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT        6
-#      define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT       9
-#      define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT      12
-#      define R300_RB3D_ZS1_BACK_FUNC_SHIFT           15
-#      define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT        18
-#      define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT       21
-#      define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT       24
-
-#define R300_RB3D_ZSTENCIL_CNTL_2                   0x4F08
-#      define R300_RB3D_ZS2_STENCIL_REF_SHIFT          0
-#      define R300_RB3D_ZS2_STENCIL_MASK               0xFF
-#      define R300_RB3D_ZS2_STENCIL_MASK_SHIFT         8
-#      define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT   16
+#      define R300_S_FRONT_FUNC_SHIFT          3
+#      define R300_S_FRONT_SFAIL_OP_SHIFT      6
+#      define R300_S_FRONT_ZPASS_OP_SHIFT      9
+#      define R300_S_FRONT_ZFAIL_OP_SHIFT      12
+#      define R300_S_BACK_FUNC_SHIFT           15
+#      define R300_S_BACK_SFAIL_OP_SHIFT       18
+#      define R300_S_BACK_ZPASS_OP_SHIFT       21
+#      define R300_S_BACK_ZFAIL_OP_SHIFT       24
+
+#define R300_ZB_STENCILREFMASK                        0x4f08
+#      define R300_STENCILREF_SHIFT       0
+#      define R300_STENCILREF_MASK        0x000000ff
+#      define R300_STENCILMASK_SHIFT      8
+#      define R300_STENCILMASK_MASK       0x0000ff00
+#      define R300_STENCILWRITEMASK_SHIFT 16
+#      define R300_STENCILWRITEMASK_MASK  0x00ff0000
 
 /* gap */
 
-#define R300_RB3D_ZSTENCIL_FORMAT                   0x4F10
-#      define R300_DEPTH_FORMAT_16BIT_INT_Z     (0 << 0)
-#      define R300_DEPTH_FORMAT_24BIT_INT_Z     (2 << 0)
-       /* 16 bit format or some aditional bit ? */
-#      define R300_DEPTH_FORMAT_UNK32          (32 << 0)
+#define R300_ZB_FORMAT                             0x4f10
+#      define R300_DEPTHFORMAT_16BIT_INT_Z   (0 << 0)
+#      define R300_DEPTHFORMAT_16BIT_13E3    (1 << 0)
+#      define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL   (2 << 0)
+/* reserved up to (15 << 0) */
+#      define R300_INVERT_13E3_LEADING_ONES  (0 << 4)
+#      define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
 
-#define R300_RB3D_EARLY_Z                           0x4F14
-#      define R300_EARLY_Z_DISABLE              (0 << 0)
-#      define R300_EARLY_Z_ENABLE               (1 << 0)
+#define R300_ZB_ZTOP                             0x4F14
+#      define R300_ZTOP_DISABLE                 (0 << 0)
+#      define R300_ZTOP_ENABLE                  (1 << 0)
 
 /* gap */
 
-#define R300_RB3D_ZCACHE_CTLSTAT            0x4F18 /* GUESS */
-#       define R300_RB3D_ZCACHE_UNKNOWN_01  0x1
-#       define R300_RB3D_ZCACHE_UNKNOWN_03  0x3
+#define R300_ZB_ZCACHE_CTLSTAT            0x4f18
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT      (0 << 0)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT       (0 << 1)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE            (1 << 1)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE            (0 << 31)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY            (1 << 31)
+
+#define R300_ZB_BW_CNTL                     0x4f1c
+#      define R300_HIZ_DISABLE                              (0 << 0)
+#      define R300_HIZ_ENABLE                               (1 << 0)
+#      define R300_HIZ_MIN                                  (0 << 1)
+#      define R300_HIZ_MAX                                  (1 << 1)
+#      define R300_FAST_FILL_DISABLE                        (0 << 2)
+#      define R300_FAST_FILL_ENABLE                         (1 << 2)
+#      define R300_RD_COMP_DISABLE                          (0 << 3)
+#      define R300_RD_COMP_ENABLE                           (1 << 3)
+#      define R300_WR_COMP_DISABLE                          (0 << 4)
+#      define R300_WR_COMP_ENABLE                           (1 << 4)
+#      define R300_ZB_CB_CLEAR_RMW                          (0 << 5)
+#      define R300_ZB_CB_CLEAR_CACHE_LINEAR                 (1 << 5)
+#      define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE   (0 << 6)
+#      define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE    (1 << 6)
+
+#      define R500_ZEQUAL_OPTIMIZE_ENABLE                   (0 << 7)
+#      define R500_ZEQUAL_OPTIMIZE_DISABLE                  (1 << 7)
+#      define R500_SEQUAL_OPTIMIZE_ENABLE                   (0 << 8)
+#      define R500_SEQUAL_OPTIMIZE_DISABLE                  (1 << 8)
+
+#      define R500_BMASK_ENABLE                             (0 << 10)
+#      define R500_BMASK_DISABLE                            (1 << 10)
+#      define R500_HIZ_EQUAL_REJECT_DISABLE                 (0 << 11)
+#      define R500_HIZ_EQUAL_REJECT_ENABLE                  (1 << 11)
+#      define R500_HIZ_FP_EXP_BITS_DISABLE                  (0 << 12)
+#      define R500_HIZ_FP_EXP_BITS_1                        (1 << 12)
+#      define R500_HIZ_FP_EXP_BITS_2                        (2 << 12)
+#      define R500_HIZ_FP_EXP_BITS_3                        (3 << 12)
+#      define R500_HIZ_FP_EXP_BITS_4                        (4 << 12)
+#      define R500_HIZ_FP_EXP_BITS_5                        (5 << 12)
+#      define R500_HIZ_FP_INVERT_LEADING_ONES               (0 << 15)
+#      define R500_HIZ_FP_INVERT_LEADING_ZEROS              (1 << 15)
+#      define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE      (0 << 16)
+#      define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE     (1 << 16)
+#      define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE           (0 << 17)
+#      define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE          (1 << 17)
+#      define R500_PEQ_PACKING_DISABLE                      (0 << 18)
+#      define R500_PEQ_PACKING_ENABLE                       (1 << 18)
+#      define R500_COVERED_PTR_MASKING_DISABLE              (0 << 18)
+#      define R500_COVERED_PTR_MASKING_ENABLE               (1 << 18)
+
 
 /* gap */
 
-#define R300_RB3D_DEPTHOFFSET               0x4F20
-#define R300_RB3D_DEPTHPITCH                0x4F24
-#       define R300_DEPTHPITCH_MASK              0x00001FF8 /* GUESS */
-#       define R300_DEPTH_TILE_ENABLE            (1 << 16) /* GUESS */
-#       define R300_DEPTH_MICROTILE_ENABLE       (1 << 17) /* GUESS */
-#       define R300_DEPTH_ENDIAN_NO_SWAP         (0 << 18) /* GUESS */
-#       define R300_DEPTH_ENDIAN_WORD_SWAP       (1 << 18) /* GUESS */
-#       define R300_DEPTH_ENDIAN_DWORD_SWAP      (2 << 18) /* GUESS */
+/* Z Buffer Address Offset.
+ * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
+ */
+#define R300_ZB_DEPTHOFFSET               0x4f20
+
+/* Z Buffer Pitch and Endian Control */
+#define R300_ZB_DEPTHPITCH                0x4f24
+#       define R300_DEPTHPITCH_MASK              0x00003FFC
+#       define R300_DEPTHMACROTILE_DISABLE      (0 << 16)
+#       define R300_DEPTHMACROTILE_ENABLE       (1 << 16)
+#       define R300_DEPTHMICROTILE_LINEAR       (0 << 17)
+#       define R300_DEPTHMICROTILE_TILED        (1 << 17)
+#       define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
+#       define R300_DEPTHENDIAN_NO_SWAP         (0 << 18)
+#       define R300_DEPTHENDIAN_WORD_SWAP       (1 << 18)
+#       define R300_DEPTHENDIAN_DWORD_SWAP      (2 << 18)
+#       define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
+
+/* Z Buffer Clear Value */
+#define R300_ZB_DEPTHCLEARVALUE                  0x4f28
+
+#define R300_ZB_ZMASK_OFFSET                    0x4f30
+#define R300_ZB_ZMASK_PITCH                     0x4f34
+#define R300_ZB_ZMASK_WRINDEX                   0x4f38
+#define R300_ZB_ZMASK_DWORD                     0x4f3c
+#define R300_ZB_ZMASK_RDINDEX                   0x4f40
+
+/* Hierarchical Z Memory Offset */
+#define R300_ZB_HIZ_OFFSET                       0x4f44
+
+/* Hierarchical Z Write Index */
+#define R300_ZB_HIZ_WRINDEX                      0x4f48
+
+/* Hierarchical Z Data */
+#define R300_ZB_HIZ_DWORD                        0x4f4c
+
+/* Hierarchical Z Read Index */
+#define R300_ZB_HIZ_RDINDEX                      0x4f50
+
+/* Hierarchical Z Pitch */
+#define R300_ZB_HIZ_PITCH                        0x4f54
+
+/* Z Buffer Z Pass Counter Data */
+#define R300_ZB_ZPASS_DATA                       0x4f58
+
+/* Z Buffer Z Pass Counter Address */
+#define R300_ZB_ZPASS_ADDR                       0x4f5c
+
+/* Depth buffer X and Y coordinate offset */
+#define R300_ZB_DEPTHXY_OFFSET                   0x4f60
+#      define R300_DEPTHX_OFFSET_SHIFT  1
+#      define R300_DEPTHX_OFFSET_MASK   0x000007FE
+#      define R300_DEPTHY_OFFSET_SHIFT  17
+#      define R300_DEPTHY_OFFSET_MASK   0x07FE0000
+
+/* Sets the fifo sizes */
+#define R500_ZB_FIFO_SIZE                        0x4fd0
+#      define R500_OP_FIFO_SIZE_FULL   (0 << 0)
+#      define R500_OP_FIFO_SIZE_HALF   (1 << 0)
+#      define R500_OP_FIFO_SIZE_QUATER (2 << 0)
+#      define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
+
+/* Stencil Reference Value and Mask for backfacing quads */
+/* R300_ZB_STENCILREFMASK handles front face */
+#define R500_ZB_STENCILREFMASK_BF                0x4fd4
+#      define R500_STENCILREF_SHIFT       0
+#      define R500_STENCILREF_MASK        0x000000ff
+#      define R500_STENCILMASK_SHIFT      8
+#      define R500_STENCILMASK_MASK       0x0000ff00
+#      define R500_STENCILWRITEMASK_SHIFT 16
+#      define R500_STENCILWRITEMASK_MASK  0x00ff0000
 
 /* BEGIN: Vertex program instruction set */
 
@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define R300_CP_CMD_BITBLT_MULTI       0xC0009B00
 
+#define R500_VAP_INDEX_OFFSET          0x208c
+
+#define R500_GA_US_VECTOR_INDEX         0x4250
+#define R500_GA_US_VECTOR_DATA          0x4254
+
+#define R500_RS_IP_0                    0x4074
+#define R500_RS_INST_0                  0x4320
+
+#define R500_US_CONFIG                  0x4600
+
+#define R500_US_FC_CTRL                        0x4624
+#define R500_US_CODE_ADDR              0x4630
+
+#define R500_RB3D_COLOR_CLEAR_VALUE_AR  0x46c0
+#define R500_RB3D_CONSTANT_COLOR_AR     0x4ef8
+
 #endif /* _R300_REG_H */
index f6f6c92..e53158f 100644 (file)
@@ -2,6 +2,7 @@
 /*
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * Copyright 2007 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
 #include "radeon_drv.h"
 #include "r300_reg.h"
 
+#include "radeon_microcode.h"
+
 #define RADEON_FIFO_DEBUG      0
 
 static int radeon_do_cleanup_cp(struct drm_device * dev);
 
-/* CP microcode (from ATI) */
-static const u32 R200_cp_microcode[][2] = {
-       {0x21007000, 0000000000},
-       {0x20007000, 0000000000},
-       {0x000000ab, 0x00000004},
-       {0x000000af, 0x00000004},
-       {0x66544a49, 0000000000},
-       {0x49494174, 0000000000},
-       {0x54517d83, 0000000000},
-       {0x498d8b64, 0000000000},
-       {0x49494949, 0000000000},
-       {0x49da493c, 0000000000},
-       {0x49989898, 0000000000},
-       {0xd34949d5, 0000000000},
-       {0x9dc90e11, 0000000000},
-       {0xce9b9b9b, 0000000000},
-       {0x000f0000, 0x00000016},
-       {0x352e232c, 0000000000},
-       {0x00000013, 0x00000004},
-       {0x000f0000, 0x00000016},
-       {0x352e272c, 0000000000},
-       {0x000f0001, 0x00000016},
-       {0x3239362f, 0000000000},
-       {0x000077ef, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x00000020, 0x0000001a},
-       {0x00004000, 0x0000001e},
-       {0x00061000, 0x00000002},
-       {0x00000020, 0x0000001a},
-       {0x00004000, 0x0000001e},
-       {0x00061000, 0x00000002},
-       {0x00000020, 0x0000001a},
-       {0x00004000, 0x0000001e},
-       {0x00000016, 0x00000004},
-       {0x0003802a, 0x00000002},
-       {0x040067e0, 0x00000002},
-       {0x00000016, 0x00000004},
-       {0x000077e0, 0x00000002},
-       {0x00065000, 0x00000002},
-       {0x000037e1, 0x00000002},
-       {0x040067e1, 0x00000006},
-       {0x000077e0, 0x00000002},
-       {0x000077e1, 0x00000002},
-       {0x000077e1, 0x00000006},
-       {0xffffffff, 0000000000},
-       {0x10000000, 0000000000},
-       {0x0003802a, 0x00000002},
-       {0x040067e0, 0x00000006},
-       {0x00007675, 0x00000002},
-       {0x00007676, 0x00000002},
-       {0x00007677, 0x00000002},
-       {0x00007678, 0x00000006},
-       {0x0003802b, 0x00000002},
-       {0x04002676, 0x00000002},
-       {0x00007677, 0x00000002},
-       {0x00007678, 0x00000006},
-       {0x0000002e, 0x00000018},
-       {0x0000002e, 0x00000018},
-       {0000000000, 0x00000006},
-       {0x0000002f, 0x00000018},
-       {0x0000002f, 0x00000018},
-       {0000000000, 0x00000006},
-       {0x01605000, 0x00000002},
-       {0x00065000, 0x00000002},
-       {0x00098000, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x64c0603d, 0x00000004},
-       {0x00080000, 0x00000016},
-       {0000000000, 0000000000},
-       {0x0400251d, 0x00000002},
-       {0x00007580, 0x00000002},
-       {0x00067581, 0x00000002},
-       {0x04002580, 0x00000002},
-       {0x00067581, 0x00000002},
-       {0x00000046, 0x00000004},
-       {0x00005000, 0000000000},
-       {0x00061000, 0x00000002},
-       {0x0000750e, 0x00000002},
-       {0x00019000, 0x00000002},
-       {0x00011055, 0x00000014},
-       {0x00000055, 0x00000012},
-       {0x0400250f, 0x00000002},
-       {0x0000504a, 0x00000004},
-       {0x00007565, 0x00000002},
-       {0x00007566, 0x00000002},
-       {0x00000051, 0x00000004},
-       {0x01e655b4, 0x00000002},
-       {0x4401b0dc, 0x00000002},
-       {0x01c110dc, 0x00000002},
-       {0x2666705d, 0x00000018},
-       {0x040c2565, 0x00000002},
-       {0x0000005d, 0x00000018},
-       {0x04002564, 0x00000002},
-       {0x00007566, 0x00000002},
-       {0x00000054, 0x00000004},
-       {0x00401060, 0x00000008},
-       {0x00101000, 0x00000002},
-       {0x000d80ff, 0x00000002},
-       {0x00800063, 0x00000008},
-       {0x000f9000, 0x00000002},
-       {0x000e00ff, 0x00000002},
-       {0000000000, 0x00000006},
-       {0x00000080, 0x00000018},
-       {0x00000054, 0x00000004},
-       {0x00007576, 0x00000002},
-       {0x00065000, 0x00000002},
-       {0x00009000, 0x00000002},
-       {0x00041000, 0x00000002},
-       {0x0c00350e, 0x00000002},
-       {0x00049000, 0x00000002},
-       {0x00051000, 0x00000002},
-       {0x01e785f8, 0x00000002},
-       {0x00200000, 0x00000002},
-       {0x00600073, 0x0000000c},
-       {0x00007563, 0x00000002},
-       {0x006075f0, 0x00000021},
-       {0x20007068, 0x00000004},
-       {0x00005068, 0x00000004},
-       {0x00007576, 0x00000002},
-       {0x00007577, 0x00000002},
-       {0x0000750e, 0x00000002},
-       {0x0000750f, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00600076, 0x0000000c},
-       {0x006075f0, 0x00000021},
-       {0x000075f8, 0x00000002},
-       {0x00000076, 0x00000004},
-       {0x000a750e, 0x00000002},
-       {0x0020750f, 0x00000002},
-       {0x00600079, 0x00000004},
-       {0x00007570, 0x00000002},
-       {0x00007571, 0x00000002},
-       {0x00007572, 0x00000006},
-       {0x00005000, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00007568, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x00000084, 0x0000000c},
-       {0x00058000, 0x00000002},
-       {0x0c607562, 0x00000002},
-       {0x00000086, 0x00000004},
-       {0x00600085, 0x00000004},
-       {0x400070dd, 0000000000},
-       {0x000380dd, 0x00000002},
-       {0x00000093, 0x0000001c},
-       {0x00065095, 0x00000018},
-       {0x040025bb, 0x00000002},
-       {0x00061096, 0x00000018},
-       {0x040075bc, 0000000000},
-       {0x000075bb, 0x00000002},
-       {0x000075bc, 0000000000},
-       {0x00090000, 0x00000006},
-       {0x00090000, 0x00000002},
-       {0x000d8002, 0x00000006},
-       {0x00005000, 0x00000002},
-       {0x00007821, 0x00000002},
-       {0x00007800, 0000000000},
-       {0x00007821, 0x00000002},
-       {0x00007800, 0000000000},
-       {0x01665000, 0x00000002},
-       {0x000a0000, 0x00000002},
-       {0x000671cc, 0x00000002},
-       {0x0286f1cd, 0x00000002},
-       {0x000000a3, 0x00000010},
-       {0x21007000, 0000000000},
-       {0x000000aa, 0x0000001c},
-       {0x00065000, 0x00000002},
-       {0x000a0000, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x000b0000, 0x00000002},
-       {0x38067000, 0x00000002},
-       {0x000a00a6, 0x00000004},
-       {0x20007000, 0000000000},
-       {0x01200000, 0x00000002},
-       {0x20077000, 0x00000002},
-       {0x01200000, 0x00000002},
-       {0x20007000, 0000000000},
-       {0x00061000, 0x00000002},
-       {0x0120751b, 0x00000002},
-       {0x8040750a, 0x00000002},
-       {0x8040750b, 0x00000002},
-       {0x00110000, 0x00000002},
-       {0x000380dd, 0x00000002},
-       {0x000000bd, 0x0000001c},
-       {0x00061096, 0x00000018},
-       {0x844075bd, 0x00000002},
-       {0x00061095, 0x00000018},
-       {0x840075bb, 0x00000002},
-       {0x00061096, 0x00000018},
-       {0x844075bc, 0x00000002},
-       {0x000000c0, 0x00000004},
-       {0x804075bd, 0x00000002},
-       {0x800075bb, 0x00000002},
-       {0x804075bc, 0x00000002},
-       {0x00108000, 0x00000002},
-       {0x01400000, 0x00000002},
-       {0x006000c4, 0x0000000c},
-       {0x20c07000, 0x00000020},
-       {0x000000c6, 0x00000012},
-       {0x00800000, 0x00000006},
-       {0x0080751d, 0x00000006},
-       {0x000025bb, 0x00000002},
-       {0x000040c0, 0x00000004},
-       {0x0000775c, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00661000, 0x00000002},
-       {0x0460275d, 0x00000020},
-       {0x00004000, 0000000000},
-       {0x00007999, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00661000, 0x00000002},
-       {0x0460299b, 0x00000020},
-       {0x00004000, 0000000000},
-       {0x01e00830, 0x00000002},
-       {0x21007000, 0000000000},
-       {0x00005000, 0x00000002},
-       {0x00038042, 0x00000002},
-       {0x040025e0, 0x00000002},
-       {0x000075e1, 0000000000},
-       {0x00000001, 0000000000},
-       {0x000380d9, 0x00000002},
-       {0x04007394, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-};
-
-static const u32 radeon_cp_microcode[][2] = {
-       {0x21007000, 0000000000},
-       {0x20007000, 0000000000},
-       {0x000000b4, 0x00000004},
-       {0x000000b8, 0x00000004},
-       {0x6f5b4d4c, 0000000000},
-       {0x4c4c427f, 0000000000},
-       {0x5b568a92, 0000000000},
-       {0x4ca09c6d, 0000000000},
-       {0xad4c4c4c, 0000000000},
-       {0x4ce1af3d, 0000000000},
-       {0xd8afafaf, 0000000000},
-       {0xd64c4cdc, 0000000000},
-       {0x4cd10d10, 0000000000},
-       {0x000f0000, 0x00000016},
-       {0x362f242d, 0000000000},
-       {0x00000012, 0x00000004},
-       {0x000f0000, 0x00000016},
-       {0x362f282d, 0000000000},
-       {0x000380e7, 0x00000002},
-       {0x04002c97, 0x00000002},
-       {0x000f0001, 0x00000016},
-       {0x333a3730, 0000000000},
-       {0x000077ef, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x00000021, 0x0000001a},
-       {0x00004000, 0x0000001e},
-       {0x00061000, 0x00000002},
-       {0x00000021, 0x0000001a},
-       {0x00004000, 0x0000001e},
-       {0x00061000, 0x00000002},
-       {0x00000021, 0x0000001a},
-       {0x00004000, 0x0000001e},
-       {0x00000017, 0x00000004},
-       {0x0003802b, 0x00000002},
-       {0x040067e0, 0x00000002},
-       {0x00000017, 0x00000004},
-       {0x000077e0, 0x00000002},
-       {0x00065000, 0x00000002},
-       {0x000037e1, 0x00000002},
-       {0x040067e1, 0x00000006},
-       {0x000077e0, 0x00000002},
-       {0x000077e1, 0x00000002},
-       {0x000077e1, 0x00000006},
-       {0xffffffff, 0000000000},
-       {0x10000000, 0000000000},
-       {0x0003802b, 0x00000002},
-       {0x040067e0, 0x00000006},
-       {0x00007675, 0x00000002},
-       {0x00007676, 0x00000002},
-       {0x00007677, 0x00000002},
-       {0x00007678, 0x00000006},
-       {0x0003802c, 0x00000002},
-       {0x04002676, 0x00000002},
-       {0x00007677, 0x00000002},
-       {0x00007678, 0x00000006},
-       {0x0000002f, 0x00000018},
-       {0x0000002f, 0x00000018},
-       {0000000000, 0x00000006},
-       {0x00000030, 0x00000018},
-       {0x00000030, 0x00000018},
-       {0000000000, 0x00000006},
-       {0x01605000, 0x00000002},
-       {0x00065000, 0x00000002},
-       {0x00098000, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x64c0603e, 0x00000004},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00080000, 0x00000016},
-       {0000000000, 0000000000},
-       {0x0400251d, 0x00000002},
-       {0x00007580, 0x00000002},
-       {0x00067581, 0x00000002},
-       {0x04002580, 0x00000002},
-       {0x00067581, 0x00000002},
-       {0x00000049, 0x00000004},
-       {0x00005000, 0000000000},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x0000750e, 0x00000002},
-       {0x00019000, 0x00000002},
-       {0x00011055, 0x00000014},
-       {0x00000055, 0x00000012},
-       {0x0400250f, 0x00000002},
-       {0x0000504f, 0x00000004},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00007565, 0x00000002},
-       {0x00007566, 0x00000002},
-       {0x00000058, 0x00000004},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x01e655b4, 0x00000002},
-       {0x4401b0e4, 0x00000002},
-       {0x01c110e4, 0x00000002},
-       {0x26667066, 0x00000018},
-       {0x040c2565, 0x00000002},
-       {0x00000066, 0x00000018},
-       {0x04002564, 0x00000002},
-       {0x00007566, 0x00000002},
-       {0x0000005d, 0x00000004},
-       {0x00401069, 0x00000008},
-       {0x00101000, 0x00000002},
-       {0x000d80ff, 0x00000002},
-       {0x0080006c, 0x00000008},
-       {0x000f9000, 0x00000002},
-       {0x000e00ff, 0x00000002},
-       {0000000000, 0x00000006},
-       {0x0000008f, 0x00000018},
-       {0x0000005b, 0x00000004},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00007576, 0x00000002},
-       {0x00065000, 0x00000002},
-       {0x00009000, 0x00000002},
-       {0x00041000, 0x00000002},
-       {0x0c00350e, 0x00000002},
-       {0x00049000, 0x00000002},
-       {0x00051000, 0x00000002},
-       {0x01e785f8, 0x00000002},
-       {0x00200000, 0x00000002},
-       {0x0060007e, 0x0000000c},
-       {0x00007563, 0x00000002},
-       {0x006075f0, 0x00000021},
-       {0x20007073, 0x00000004},
-       {0x00005073, 0x00000004},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00007576, 0x00000002},
-       {0x00007577, 0x00000002},
-       {0x0000750e, 0x00000002},
-       {0x0000750f, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00600083, 0x0000000c},
-       {0x006075f0, 0x00000021},
-       {0x000075f8, 0x00000002},
-       {0x00000083, 0x00000004},
-       {0x000a750e, 0x00000002},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x0020750f, 0x00000002},
-       {0x00600086, 0x00000004},
-       {0x00007570, 0x00000002},
-       {0x00007571, 0x00000002},
-       {0x00007572, 0x00000006},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00005000, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00007568, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x00000095, 0x0000000c},
-       {0x00058000, 0x00000002},
-       {0x0c607562, 0x00000002},
-       {0x00000097, 0x00000004},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x00600096, 0x00000004},
-       {0x400070e5, 0000000000},
-       {0x000380e6, 0x00000002},
-       {0x040025c5, 0x00000002},
-       {0x000380e5, 0x00000002},
-       {0x000000a8, 0x0000001c},
-       {0x000650aa, 0x00000018},
-       {0x040025bb, 0x00000002},
-       {0x000610ab, 0x00000018},
-       {0x040075bc, 0000000000},
-       {0x000075bb, 0x00000002},
-       {0x000075bc, 0000000000},
-       {0x00090000, 0x00000006},
-       {0x00090000, 0x00000002},
-       {0x000d8002, 0x00000006},
-       {0x00007832, 0x00000002},
-       {0x00005000, 0x00000002},
-       {0x000380e7, 0x00000002},
-       {0x04002c97, 0x00000002},
-       {0x00007820, 0x00000002},
-       {0x00007821, 0x00000002},
-       {0x00007800, 0000000000},
-       {0x01200000, 0x00000002},
-       {0x20077000, 0x00000002},
-       {0x01200000, 0x00000002},
-       {0x20007000, 0x00000002},
-       {0x00061000, 0x00000002},
-       {0x0120751b, 0x00000002},
-       {0x8040750a, 0x00000002},
-       {0x8040750b, 0x00000002},
-       {0x00110000, 0x00000002},
-       {0x000380e5, 0x00000002},
-       {0x000000c6, 0x0000001c},
-       {0x000610ab, 0x00000018},
-       {0x844075bd, 0x00000002},
-       {0x000610aa, 0x00000018},
-       {0x840075bb, 0x00000002},
-       {0x000610ab, 0x00000018},
-       {0x844075bc, 0x00000002},
-       {0x000000c9, 0x00000004},
-       {0x804075bd, 0x00000002},
-       {0x800075bb, 0x00000002},
-       {0x804075bc, 0x00000002},
-       {0x00108000, 0x00000002},
-       {0x01400000, 0x00000002},
-       {0x006000cd, 0x0000000c},
-       {0x20c07000, 0x00000020},
-       {0x000000cf, 0x00000012},
-       {0x00800000, 0x00000006},
-       {0x0080751d, 0x00000006},
-       {0000000000, 0000000000},
-       {0x0000775c, 0x00000002},
-       {0x00a05000, 0x00000002},
-       {0x00661000, 0x00000002},
-       {0x0460275d, 0x00000020},
-       {0x00004000, 0000000000},
-       {0x01e00830, 0x00000002},
-       {0x21007000, 0000000000},
-       {0x6464614d, 0000000000},
-       {0x69687420, 0000000000},
-       {0x00000073, 0000000000},
-       {0000000000, 0000000000},
-       {0x00005000, 0x00000002},
-       {0x000380d0, 0x00000002},
-       {0x040025e0, 0x00000002},
-       {0x000075e1, 0000000000},
-       {0x00000001, 0000000000},
-       {0x000380e0, 0x00000002},
-       {0x04002394, 0x00000002},
-       {0x00005000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0x00000008, 0000000000},
-       {0x00000004, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-};
-
-static const u32 R300_cp_microcode[][2] = {
-       {0x4200e000, 0000000000},
-       {0x4000e000, 0000000000},
-       {0x000000af, 0x00000008},
-       {0x000000b3, 0x00000008},
-       {0x6c5a504f, 0000000000},
-       {0x4f4f497a, 0000000000},
-       {0x5a578288, 0000000000},
-       {0x4f91906a, 0000000000},
-       {0x4f4f4f4f, 0000000000},
-       {0x4fe24f44, 0000000000},
-       {0x4f9c9c9c, 0000000000},
-       {0xdc4f4fde, 0000000000},
-       {0xa1cd4f4f, 0000000000},
-       {0xd29d9d9d, 0000000000},
-       {0x4f0f9fd7, 0000000000},
-       {0x000ca000, 0x00000004},
-       {0x000d0012, 0x00000038},
-       {0x0000e8b4, 0x00000004},
-       {0x000d0014, 0x00000038},
-       {0x0000e8b6, 0x00000004},
-       {0x000d0016, 0x00000038},
-       {0x0000e854, 0x00000004},
-       {0x000d0018, 0x00000038},
-       {0x0000e855, 0x00000004},
-       {0x000d001a, 0x00000038},
-       {0x0000e856, 0x00000004},
-       {0x000d001c, 0x00000038},
-       {0x0000e857, 0x00000004},
-       {0x000d001e, 0x00000038},
-       {0x0000e824, 0x00000004},
-       {0x000d0020, 0x00000038},
-       {0x0000e825, 0x00000004},
-       {0x000d0022, 0x00000038},
-       {0x0000e830, 0x00000004},
-       {0x000d0024, 0x00000038},
-       {0x0000f0c0, 0x00000004},
-       {0x000d0026, 0x00000038},
-       {0x0000f0c1, 0x00000004},
-       {0x000d0028, 0x00000038},
-       {0x0000f041, 0x00000004},
-       {0x000d002a, 0x00000038},
-       {0x0000f184, 0x00000004},
-       {0x000d002c, 0x00000038},
-       {0x0000f185, 0x00000004},
-       {0x000d002e, 0x00000038},
-       {0x0000f186, 0x00000004},
-       {0x000d0030, 0x00000038},
-       {0x0000f187, 0x00000004},
-       {0x000d0032, 0x00000038},
-       {0x0000f180, 0x00000004},
-       {0x000d0034, 0x00000038},
-       {0x0000f393, 0x00000004},
-       {0x000d0036, 0x00000038},
-       {0x0000f38a, 0x00000004},
-       {0x000d0038, 0x00000038},
-       {0x0000f38e, 0x00000004},
-       {0x0000e821, 0x00000004},
-       {0x0140a000, 0x00000004},
-       {0x00000043, 0x00000018},
-       {0x00cce800, 0x00000004},
-       {0x001b0001, 0x00000004},
-       {0x08004800, 0x00000004},
-       {0x001b0001, 0x00000004},
-       {0x08004800, 0x00000004},
-       {0x001b0001, 0x00000004},
-       {0x08004800, 0x00000004},
-       {0x0000003a, 0x00000008},
-       {0x0000a000, 0000000000},
-       {0x02c0a000, 0x00000004},
-       {0x000ca000, 0x00000004},
-       {0x00130000, 0x00000004},
-       {0x000c2000, 0x00000004},
-       {0xc980c045, 0x00000008},
-       {0x2000451d, 0x00000004},
-       {0x0000e580, 0x00000004},
-       {0x000ce581, 0x00000004},
-       {0x08004580, 0x00000004},
-       {0x000ce581, 0x00000004},
-       {0x0000004c, 0x00000008},
-       {0x0000a000, 0000000000},
-       {0x000c2000, 0x00000004},
-       {0x0000e50e, 0x00000004},
-       {0x00032000, 0x00000004},
-       {0x00022056, 0x00000028},
-       {0x00000056, 0x00000024},
-       {0x0800450f, 0x00000004},
-       {0x0000a050, 0x00000008},
-       {0x0000e565, 0x00000004},
-       {0x0000e566, 0x00000004},
-       {0x00000057, 0x00000008},
-       {0x03cca5b4, 0x00000004},
-       {0x05432000, 0x00000004},
-       {0x00022000, 0x00000004},
-       {0x4ccce063, 0x00000030},
-       {0x08274565, 0x00000004},
-       {0x00000063, 0x00000030},
-       {0x08004564, 0x00000004},
-       {0x0000e566, 0x00000004},
-       {0x0000005a, 0x00000008},
-       {0x00802066, 0x00000010},
-       {0x00202000, 0x00000004},
-       {0x001b00ff, 0x00000004},
-       {0x01000069, 0x00000010},
-       {0x001f2000, 0x00000004},
-       {0x001c00ff, 0x00000004},
-       {0000000000, 0x0000000c},
-       {0x00000085, 0x00000030},
-       {0x0000005a, 0x00000008},
-       {0x0000e576, 0x00000004},
-       {0x000ca000, 0x00000004},
-       {0x00012000, 0x00000004},
-       {0x00082000, 0x00000004},
-       {0x1800650e, 0x00000004},
-       {0x00092000, 0x00000004},
-       {0x000a2000, 0x00000004},
-       {0x000f0000, 0x00000004},
-       {0x00400000, 0x00000004},
-       {0x00000079, 0x00000018},
-       {0x0000e563, 0x00000004},
-       {0x00c0e5f9, 0x000000c2},
-       {0x0000006e, 0x00000008},
-       {0x0000a06e, 0x00000008},
-       {0x0000e576, 0x00000004},
-       {0x0000e577, 0x00000004},
-       {0x0000e50e, 0x00000004},
-       {0x0000e50f, 0x00000004},
-       {0x0140a000, 0x00000004},
-       {0x0000007c, 0x00000018},
-       {0x00c0e5f9, 0x000000c2},
-       {0x0000007c, 0x00000008},
-       {0x0014e50e, 0x00000004},
-       {0x0040e50f, 0x00000004},
-       {0x00c0007f, 0x00000008},
-       {0x0000e570, 0x00000004},
-       {0x0000e571, 0x00000004},
-       {0x0000e572, 0x0000000c},
-       {0x0000a000, 0x00000004},
-       {0x0140a000, 0x00000004},
-       {0x0000e568, 0x00000004},
-       {0x000c2000, 0x00000004},
-       {0x00000089, 0x00000018},
-       {0x000b0000, 0x00000004},
-       {0x18c0e562, 0x00000004},
-       {0x0000008b, 0x00000008},
-       {0x00c0008a, 0x00000008},
-       {0x000700e4, 0x00000004},
-       {0x00000097, 0x00000038},
-       {0x000ca099, 0x00000030},
-       {0x080045bb, 0x00000004},
-       {0x000c209a, 0x00000030},
-       {0x0800e5bc, 0000000000},
-       {0x0000e5bb, 0x00000004},
-       {0x0000e5bc, 0000000000},
-       {0x00120000, 0x0000000c},
-       {0x00120000, 0x00000004},
-       {0x001b0002, 0x0000000c},
-       {0x0000a000, 0x00000004},
-       {0x0000e821, 0x00000004},
-       {0x0000e800, 0000000000},
-       {0x0000e821, 0x00000004},
-       {0x0000e82e, 0000000000},
-       {0x02cca000, 0x00000004},
-       {0x00140000, 0x00000004},
-       {0x000ce1cc, 0x00000004},
-       {0x050de1cd, 0x00000004},
-       {0x000000a7, 0x00000020},
-       {0x4200e000, 0000000000},
-       {0x000000ae, 0x00000038},
-       {0x000ca000, 0x00000004},
-       {0x00140000, 0x00000004},
-       {0x000c2000, 0x00000004},
-       {0x00160000, 0x00000004},
-       {0x700ce000, 0x00000004},
-       {0x001400aa, 0x00000008},
-       {0x4000e000, 0000000000},
-       {0x02400000, 0x00000004},
-       {0x400ee000, 0x00000004},
-       {0x02400000, 0x00000004},
-       {0x4000e000, 0000000000},
-       {0x000c2000, 0x00000004},
-       {0x0240e51b, 0x00000004},
-       {0x0080e50a, 0x00000005},
-       {0x0080e50b, 0x00000005},
-       {0x00220000, 0x00000004},
-       {0x000700e4, 0x00000004},
-       {0x000000c1, 0x00000038},
-       {0x000c209a, 0x00000030},
-       {0x0880e5bd, 0x00000005},
-       {0x000c2099, 0x00000030},
-       {0x0800e5bb, 0x00000005},
-       {0x000c209a, 0x00000030},
-       {0x0880e5bc, 0x00000005},
-       {0x000000c4, 0x00000008},
-       {0x0080e5bd, 0x00000005},
-       {0x0000e5bb, 0x00000005},
-       {0x0080e5bc, 0x00000005},
-       {0x00210000, 0x00000004},
-       {0x02800000, 0x00000004},
-       {0x00c000c8, 0x00000018},
-       {0x4180e000, 0x00000040},
-       {0x000000ca, 0x00000024},
-       {0x01000000, 0x0000000c},
-       {0x0100e51d, 0x0000000c},
-       {0x000045bb, 0x00000004},
-       {0x000080c4, 0x00000008},
-       {0x0000f3ce, 0x00000004},
-       {0x0140a000, 0x00000004},
-       {0x00cc2000, 0x00000004},
-       {0x08c053cf, 0x00000040},
-       {0x00008000, 0000000000},
-       {0x0000f3d2, 0x00000004},
-       {0x0140a000, 0x00000004},
-       {0x00cc2000, 0x00000004},
-       {0x08c053d3, 0x00000040},
-       {0x00008000, 0000000000},
-       {0x0000f39d, 0x00000004},
-       {0x0140a000, 0x00000004},
-       {0x00cc2000, 0x00000004},
-       {0x08c0539e, 0x00000040},
-       {0x00008000, 0000000000},
-       {0x03c00830, 0x00000004},
-       {0x4200e000, 0000000000},
-       {0x0000a000, 0x00000004},
-       {0x200045e0, 0x00000004},
-       {0x0000e5e1, 0000000000},
-       {0x00000001, 0000000000},
-       {0x000700e1, 0x00000004},
-       {0x0800e394, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-       {0000000000, 0000000000},
-};
-
-static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
        u32 ret;
        RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
        return ret;
 }
 
+static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+       u32 ret;
+       RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
+       ret = RADEON_READ(RS480_NB_MC_DATA);
+       RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
+       return ret;
+}
+
 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
+       u32 ret;
        RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
-       return RADEON_READ(RS690_MC_DATA);
+       ret = RADEON_READ(RS690_MC_DATA);
+       RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
+       return ret;
+}
+
+static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+               return RS690_READ_MCIND(dev_priv, addr);
+       else
+               return RS480_READ_MCIND(dev_priv, addr);
 }
 
 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 {
 
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-               return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+               return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
                return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-               return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
+               return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
        else
                return RADEON_READ(RADEON_MC_FB_LOCATION);
 }
@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 {
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-               RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+               R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
                RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-               RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
+               R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
        else
                RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 }
@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 {
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-               RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+               R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
                RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-               RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
+               R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
        else
                RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 }
 
+static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+{
+       u32 agp_base_hi = upper_32_bits(agp_base);
+       u32 agp_base_lo = agp_base & 0xffffffff;
+
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
+               R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
+               R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+               RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
+               RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
+               R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
+               R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
+               RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+               RADEON_WRITE(RS480_AGP_BASE_2, 0);
+       } else {
+               RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+               if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
+                       RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
+       }
+}
+
 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
        return RADEON_READ(RADEON_PCIE_DATA);
 }
 
-static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
-{
-       u32 ret;
-       RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
-       ret = RADEON_READ(RADEON_IGPGART_DATA);
-       RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
-       return ret;
-}
-
 #if RADEON_FIFO_DEBUG
 static void radeon_status(drm_radeon_private_t * dev_priv)
 {
@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 
        dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-       tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
-       tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-       RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
+               tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
+               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+               RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 
-       for (i = 0; i < dev_priv->usec_timeout; i++) {
-               if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
-                     & RADEON_RB3D_DC_BUSY)) {
-                       return 0;
+               for (i = 0; i < dev_priv->usec_timeout; i++) {
+                       if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
+                             & RADEON_RB3D_DC_BUSY)) {
+                               return 0;
+                       }
+                       DRM_UDELAY(1);
+               }
+       } else {
+               /* 3D */
+               tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
+               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+               RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
+
+               /* 2D */
+               tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
+               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+               RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
+
+               for (i = 0; i < dev_priv->usec_timeout; i++) {
+                       if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
+                         & RADEON_RB3D_DC_BUSY)) {
+                               return 0;
+                       }
+                       DRM_UDELAY(1);
                }
-               DRM_UDELAY(1);
        }
 
 #if RADEON_FIFO_DEBUG
@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
        return -EBUSY;
 }
 
+static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
+{
+       uint32_t gb_tile_config, gb_pipe_sel = 0;
+
+       /* RS4xx/RS6xx/R4xx/R5xx */
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
+               gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
+               dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+       } else {
+               /* R3xx */
+               if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
+                       dev_priv->num_gb_pipes = 2;
+               } else {
+                       /* R3Vxx */
+                       dev_priv->num_gb_pipes = 1;
+               }
+       }
+       DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
+
+       gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
+
+       switch (dev_priv->num_gb_pipes) {
+       case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+       case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+       case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+       default:
+       case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
+       }
+
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
+               RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
+               RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
+       }
+       RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
+       radeon_do_wait_for_idle(dev_priv);
+       RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
+       RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
+                                              R300_DC_AUTOFLUSH_ENABLE |
+                                              R300_DC_DC_DISABLE_IGNORE_PE));
+
+
+}
+
 /* ================================================================
  * CP control, initialization
  */
@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
        radeon_do_wait_for_idle(dev_priv);
 
        RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
-
-       if (dev_priv->microcode_version == UCODE_R200) {
+       if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
+               DRM_INFO("Loading R100 Microcode\n");
+               for (i = 0; i < 256; i++) {
+                       RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+                                    R100_cp_microcode[i][1]);
+                       RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+                                    R100_cp_microcode[i][0]);
+               }
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
                DRM_INFO("Loading R200 Microcode\n");
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                     R200_cp_microcode[i][0]);
                }
-       } else if (dev_priv->microcode_version == UCODE_R300) {
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
                DRM_INFO("Loading R300 Microcode\n");
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                     R300_cp_microcode[i][0]);
                }
-       } else {
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
+               DRM_INFO("Loading R400 Microcode\n");
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-                                    radeon_cp_microcode[i][1]);
+                                    R420_cp_microcode[i][1]);
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-                                    radeon_cp_microcode[i][0]);
+                                    R420_cp_microcode[i][0]);
+               }
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+               DRM_INFO("Loading RS690 Microcode\n");
+               for (i = 0; i < 256; i++) {
+                       RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+                                    RS690_cp_microcode[i][1]);
+                       RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+                                    RS690_cp_microcode[i][0]);
+               }
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
+               DRM_INFO("Loading R500 Microcode\n");
+               for (i = 0; i < 256; i++) {
+                       RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+                                    R520_cp_microcode[i][1]);
+                       RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+                                    R520_cp_microcode[i][0]);
                }
        }
 }
@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 static int radeon_do_engine_reset(struct drm_device * dev)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
-       u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
+       u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
        DRM_DEBUG("\n");
 
        radeon_do_pixcache_flush(dev_priv);
 
-       if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
+               /* may need something similar for newer chips */
                clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
                mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 
@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
                                                    RADEON_FORCEON_YCLKB |
                                                    RADEON_FORCEON_MC |
                                                    RADEON_FORCEON_AIC));
+       }
 
-               rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
-               RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-                                                     RADEON_SOFT_RESET_CP |
-                                                     RADEON_SOFT_RESET_HI |
-                                                     RADEON_SOFT_RESET_SE |
-                                                     RADEON_SOFT_RESET_RE |
-                                                     RADEON_SOFT_RESET_PP |
-                                                     RADEON_SOFT_RESET_E2 |
-                                                     RADEON_SOFT_RESET_RB));
-               RADEON_READ(RADEON_RBBM_SOFT_RESET);
-               RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
-                                                     ~(RADEON_SOFT_RESET_CP |
-                                                       RADEON_SOFT_RESET_HI |
-                                                       RADEON_SOFT_RESET_SE |
-                                                       RADEON_SOFT_RESET_RE |
-                                                       RADEON_SOFT_RESET_PP |
-                                                       RADEON_SOFT_RESET_E2 |
-                                                       RADEON_SOFT_RESET_RB)));
-               RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
+       rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+       RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+                                             RADEON_SOFT_RESET_CP |
+                                             RADEON_SOFT_RESET_HI |
+                                             RADEON_SOFT_RESET_SE |
+                                             RADEON_SOFT_RESET_RE |
+                                             RADEON_SOFT_RESET_PP |
+                                             RADEON_SOFT_RESET_E2 |
+                                             RADEON_SOFT_RESET_RB));
+       RADEON_READ(RADEON_RBBM_SOFT_RESET);
+       RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+                                             ~(RADEON_SOFT_RESET_CP |
+                                               RADEON_SOFT_RESET_HI |
+                                               RADEON_SOFT_RESET_SE |
+                                               RADEON_SOFT_RESET_RE |
+                                               RADEON_SOFT_RESET_PP |
+                                               RADEON_SOFT_RESET_E2 |
+                                               RADEON_SOFT_RESET_RB)));
+       RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
                RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
                RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
                RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
        }
 
+       /* setup the raster pipes */
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
+           radeon_init_pipes(dev_priv);
+
        /* Reset the CP ring */
        radeon_do_cp_reset(dev_priv);
 
@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 
 #if __OS_HAS_AGP
        if (dev_priv->flags & RADEON_IS_AGP) {
-               RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
+               radeon_write_agp_base(dev_priv, dev->agp->base);
+
                radeon_write_agp_location(dev_priv,
                             (((dev_priv->gart_vm_start - 1 +
                                dev_priv->gart_size) & 0xffff0000) |
@@ -1338,103 +711,71 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 
 /* Enable or disable IGP GART on the chip */
 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
-{
-       u32 temp, tmp;
-
-       tmp = RADEON_READ(RADEON_AIC_CNTL);
-       if (on) {
-               DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
-                        dev_priv->gart_vm_start,
-                        (long)dev_priv->gart_info.bus_addr,
-                        dev_priv->gart_size);
-
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
-                                    dev_priv->gart_info.bus_addr);
-
-               temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
-
-               RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
-               dev_priv->gart_size = 32*1024*1024;
-               radeon_write_agp_location(dev_priv,
-                            (((dev_priv->gart_vm_start - 1 +
-                              dev_priv->gart_size) & 0xffff0000) |
-                            (dev_priv->gart_vm_start >> 16)));
-
-               temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
-
-               RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
-               RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-               RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
-       }
-}
-
-/* Enable or disable RS690 GART on the chip */
-static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
 {
        u32 temp;
 
        if (on) {
-               DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
+               DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
                          dev_priv->gart_vm_start,
                          (long)dev_priv->gart_info.bus_addr,
                          dev_priv->gart_size);
 
-               temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
-               RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
+               temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
+               if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+                       IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
+                                                            RS690_BLOCK_GFX_D3_EN));
+               else
+                       IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 
-               RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-                                 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
+               IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+                                                              RS480_VA_SIZE_32MB));
 
-               temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
-               RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
+               temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
+               IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
+                                                       RS480_TLB_ENABLE |
+                                                       RS480_GTW_LAC_EN |
+                                                       RS480_1LEVEL_GART));
 
-               RS690_WRITE_MCIND(RS690_MC_GART_BASE,
-                                 dev_priv->gart_info.bus_addr);
+               temp = dev_priv->gart_info.bus_addr & 0xfffff000;
+               temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
+               IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 
-               temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
-               RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
+               temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
+               IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
+                                                     RS480_REQ_TYPE_SNOOP_DIS));
 
-               RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
-                                 (unsigned int)dev_priv->gart_vm_start);
+               radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 
                dev_priv->gart_size = 32*1024*1024;
                temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 
-               RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
+               radeon_write_agp_location(dev_priv, temp);
 
-               temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
-               RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-                                 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
+               temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
+               IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+                                                              RS480_VA_SIZE_32MB));
 
                do {
-                       temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
-                       if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
-                           RS690_MC_GART_CLEAR_DONE)
+                       temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
+                       if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
                                break;
                        DRM_UDELAY(1);
                } while (1);
 
-               RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
-                                 RS690_MC_GART_CC_CLEAR);
+               IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
+                               RS480_GART_CACHE_INVALIDATE);
+
                do {
-                       temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
-                       if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
-                                  RS690_MC_GART_CLEAR_DONE)
+                       temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
+                       if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
                                break;
                        DRM_UDELAY(1);
                } while (1);
 
-               RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
-                                 RS690_MC_GART_CC_NO_CHANGE);
+               IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
        } else {
-               RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
+               IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
        }
 }
 
@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 {
        u32 tmp;
 
-       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
-               radeon_set_rs690gart(dev_priv, on);
-               return;
-       }
-
-       if (dev_priv->flags & RADEON_IS_IGPGART) {
+       if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+           (dev_priv->flags & RADEON_IS_IGPGART)) {
                radeon_set_igpgart(dev_priv, on);
                return;
        }
@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
        radeon_cp_init_ring_buffer(dev, dev_priv);
 
        radeon_do_engine_reset(dev);
+       radeon_enable_interrupt(dev);
 
        DRM_DEBUG("radeon_do_resume_cp() complete\n");
 
index aab82e1..73ff51f 100644 (file)
@@ -240,6 +240,7 @@ typedef union {
 #      define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN    0x8
 
 #define R300_CMD_SCRATCH               8
+#define R300_CMD_R500FP                 9
 
 typedef union {
        unsigned int u;
@@ -268,6 +269,9 @@ typedef union {
        struct {
                unsigned char cmd_type, reg, n_bufs, flags;
        } scratch;
+       struct {
+               unsigned char cmd_type, count, adrlo, adrhi_flags;
+       } r500fp;
 } drm_r300_cmd_header_t;
 
 #define RADEON_FRONT                   0x1
@@ -278,6 +282,9 @@ typedef union {
 #define RADEON_USE_HIERZ               0x40000000
 #define RADEON_USE_COMP_ZBUF           0x20000000
 
+#define R500FP_CONSTANT_TYPE  (1 << 1)
+#define R500FP_CONSTANT_CLAMP (1 << 2)
+
 /* Primitive types
  */
 #define RADEON_POINTS                  0x1
@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_CARD_TYPE             12
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
+#define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 
 typedef struct drm_radeon_getparam {
        int param;
index 173ae62..3f0eca9 100644 (file)
@@ -38,7 +38,7 @@
 
 #define DRIVER_NAME            "radeon"
 #define DRIVER_DESC            "ATI Radeon"
-#define DRIVER_DATE            "20060524"
+#define DRIVER_DATE            "20080528"
 
 /* Interface history:
  *
  * 1.26- Add support for variable size PCI(E) gart aperture
  * 1.27- Add support for IGP GART
  * 1.28- Add support for VBL on CRTC2
+ * 1.29- R500 3D cmd buffer support
  */
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           28
+#define DRIVER_MINOR           29
 #define DRIVER_PATCHLEVEL      0
 
 /*
@@ -122,7 +123,7 @@ enum radeon_family {
        CHIP_RV380,
        CHIP_R420,
        CHIP_RV410,
-       CHIP_RS400,
+       CHIP_RS480,
        CHIP_RS690,
        CHIP_RV515,
        CHIP_R520,
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
        int vblank_crtc;
        uint32_t irq_enable_reg;
        int irq_enabled;
+       uint32_t r500_disp_irq_reg;
 
        struct radeon_surface surfaces[RADEON_MAX_SURFACES];
        struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -307,6 +309,8 @@ typedef struct drm_radeon_private {
        /* starting from here on, data is preserved accross an open */
        uint32_t flags;         /* see radeon_chip_flags */
        unsigned long fb_aper_offset;
+
+       int num_gb_pipes;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
+extern void radeon_enable_interrupt(struct drm_device *dev);
 extern int radeon_vblank_crtc_get(struct drm_device *dev);
 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
 
@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PCIE_DATA                0x0034
 #define RADEON_PCIE_TX_GART_CNTL       0x10
 #      define RADEON_PCIE_TX_GART_EN           (1 << 0)
-#      define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
-#      define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1<<1)
-#      define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3<<1)
-#      define RADEON_PCIE_TX_GART_MODE_32_128_CACHE    (0<<3)
-#      define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE   (1<<3)
-#      define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1<<5)
-#      define RADEON_PCIE_TX_GART_INVALIDATE_TLB       (1<<8)
+#      define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
+#      define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1 << 1)
+#      define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3 << 1)
+#      define RADEON_PCIE_TX_GART_MODE_32_128_CACHE    (0 << 3)
+#      define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE   (1 << 3)
+#      define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1 << 5)
+#      define RADEON_PCIE_TX_GART_INVALIDATE_TLB       (1 << 8)
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
 #define RADEON_PCIE_TX_GART_BASE       0x13
@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PCIE_TX_GART_END_LO     0x16
 #define RADEON_PCIE_TX_GART_END_HI     0x17
 
-#define RADEON_IGPGART_INDEX            0x168
-#define RADEON_IGPGART_DATA             0x16c
-#define RADEON_IGPGART_UNK_18           0x18
-#define RADEON_IGPGART_CTRL             0x2b
-#define RADEON_IGPGART_BASE_ADDR        0x2c
-#define RADEON_IGPGART_FLUSH            0x2e
-#define RADEON_IGPGART_ENABLE           0x38
-#define RADEON_IGPGART_UNK_39           0x39
+#define RS480_NB_MC_INDEX               0x168
+#      define RS480_NB_MC_IND_WR_EN    (1 << 8)
+#define RS480_NB_MC_DATA                0x16c
 
 #define RS690_MC_INDEX                  0x78
 #   define RS690_MC_INDEX_MASK          0x1ff
@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #   define RS690_MC_INDEX_WR_ACK        0x7f
 #define RS690_MC_DATA                   0x7c
 
-#define RS690_MC_MISC_CNTL              0x18
-#define RS690_MC_GART_FEATURE_ID        0x2b
-#define RS690_MC_GART_BASE              0x2c
-#define RS690_MC_GART_CACHE_CNTL       0x2e
-#   define RS690_MC_GART_CC_NO_CHANGE   0x0
-#   define RS690_MC_GART_CC_CLEAR       0x1
-#   define RS690_MC_GART_CLEAR_STATUS   (1 << 1)
-#       define RS690_MC_GART_CLEAR_DONE     (0 << 1)
-#       define RS690_MC_GART_CLEAR_PENDING  (1 << 1)
-#define RS690_MC_AGP_SIZE               0x38
-#   define RS690_MC_GART_DIS            0x0
-#   define RS690_MC_GART_EN             0x1
-#   define RS690_MC_AGP_SIZE_32MB       (0 << 1)
-#   define RS690_MC_AGP_SIZE_64MB       (1 << 1)
-#   define RS690_MC_AGP_SIZE_128MB      (2 << 1)
-#   define RS690_MC_AGP_SIZE_256MB      (3 << 1)
-#   define RS690_MC_AGP_SIZE_512MB      (4 << 1)
-#   define RS690_MC_AGP_SIZE_1GB        (5 << 1)
-#   define RS690_MC_AGP_SIZE_2GB        (6 << 1)
-#define RS690_MC_AGP_MODE_CONTROL       0x39
+/* MC indirect registers */
+#define RS480_MC_MISC_CNTL              0x18
+#      define RS480_DISABLE_GTW        (1 << 1)
+/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
+#      define RS480_GART_INDEX_REG_EN  (1 << 12)
+#      define RS690_BLOCK_GFX_D3_EN    (1 << 14)
+#define RS480_K8_FB_LOCATION            0x1e
+#define RS480_GART_FEATURE_ID           0x2b
+#      define RS480_HANG_EN            (1 << 11)
+#      define RS480_TLB_ENABLE         (1 << 18)
+#      define RS480_P2P_ENABLE         (1 << 19)
+#      define RS480_GTW_LAC_EN         (1 << 25)
+#      define RS480_2LEVEL_GART        (0 << 30)
+#      define RS480_1LEVEL_GART        (1 << 30)
+#      define RS480_PDC_EN             (1 << 31)
+#define RS480_GART_BASE                 0x2c
+#define RS480_GART_CACHE_CNTRL          0x2e
+#      define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
+#define RS480_AGP_ADDRESS_SPACE_SIZE    0x38
+#      define RS480_GART_EN            (1 << 0)
+#      define RS480_VA_SIZE_32MB       (0 << 1)
+#      define RS480_VA_SIZE_64MB       (1 << 1)
+#      define RS480_VA_SIZE_128MB      (2 << 1)
+#      define RS480_VA_SIZE_256MB      (3 << 1)
+#      define RS480_VA_SIZE_512MB      (4 << 1)
+#      define RS480_VA_SIZE_1GB        (5 << 1)
+#      define RS480_VA_SIZE_2GB        (6 << 1)
+#define RS480_AGP_MODE_CNTL             0x39
+#      define RS480_POST_GART_Q_SIZE   (1 << 18)
+#      define RS480_NONGART_SNOOP      (1 << 19)
+#      define RS480_AGP_RD_BUF_SIZE    (1 << 20)
+#      define RS480_REQ_TYPE_SNOOP_SHIFT 22
+#      define RS480_REQ_TYPE_SNOOP_MASK  0x3
+#      define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
+#define RS480_MC_MISC_UMA_CNTL          0x5f
+#define RS480_MC_MCLK_CNTL              0x7a
+#define RS480_MC_UMA_DUALCH_CNTL        0x86
+
 #define RS690_MC_FB_LOCATION            0x100
 #define RS690_MC_AGP_LOCATION           0x101
 #define RS690_MC_AGP_BASE               0x102
+#define RS690_MC_AGP_BASE_2             0x103
 
 #define R520_MC_IND_INDEX 0x70
-#define R520_MC_IND_WR_EN (1<<24)
+#define R520_MC_IND_WR_EN (1 << 24)
 #define R520_MC_IND_DATA  0x74
 
 #define RV515_MC_FB_LOCATION 0x01
 #define RV515_MC_AGP_LOCATION 0x02
+#define RV515_MC_AGP_BASE     0x03
+#define RV515_MC_AGP_BASE_2   0x04
 
 #define R520_MC_FB_LOCATION 0x04
 #define R520_MC_AGP_LOCATION 0x05
+#define R520_MC_AGP_BASE     0x06
+#define R520_MC_AGP_BASE_2   0x07
 
 #define RADEON_MPP_TB_CONFIG           0x01c0
 #define RADEON_MEM_CNTL                        0x0140
 #define RADEON_MEM_SDRAM_MODE_REG      0x0158
+#define RADEON_AGP_BASE_2              0x015c /* r200+ only */
+#define RS480_AGP_BASE_2               0x0164
 #define RADEON_AGP_BASE                        0x0170
 
+/* pipe config regs */
+#define R400_GB_PIPE_SELECT             0x402c
+#define R500_DYN_SCLK_PWMEM_PIPE        0x000d /* PLL */
+#define R500_SU_REG_DEST                0x42c8
+#define R300_GB_TILE_CONFIG             0x4018
+#       define R300_ENABLE_TILING       (1 << 0)
+#       define R300_PIPE_COUNT_RV350    (0 << 1)
+#       define R300_PIPE_COUNT_R300     (3 << 1)
+#       define R300_PIPE_COUNT_R420_3P  (6 << 1)
+#       define R300_PIPE_COUNT_R420     (7 << 1)
+#       define R300_TILE_SIZE_8         (0 << 4)
+#       define R300_TILE_SIZE_16        (1 << 4)
+#       define R300_TILE_SIZE_32        (2 << 4)
+#       define R300_SUBPIXEL_1_12       (0 << 16)
+#       define R300_SUBPIXEL_1_16       (1 << 16)
+#define R300_DST_PIPE_CONFIG            0x170c
+#       define R300_PIPE_AUTO_CONFIG    (1 << 31)
+#define R300_RB2D_DSTCACHE_MODE         0x3428
+#       define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
+#       define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
+
 #define RADEON_RB3D_COLOROFFSET                0x1c40
 #define RADEON_RB3D_COLORPITCH         0x1c48
 
@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PP_TXFILTER_1           0x1c6c
 #define RADEON_PP_TXFILTER_2           0x1c84
 
-#define RADEON_RB2D_DSTCACHE_CTLSTAT   0x342c
-#      define RADEON_RB2D_DC_FLUSH             (3 << 0)
-#      define RADEON_RB2D_DC_FREE              (3 << 2)
-#      define RADEON_RB2D_DC_FLUSH_ALL         0xf
-#      define RADEON_RB2D_DC_BUSY              (1 << 31)
+#define R300_RB2D_DSTCACHE_CTLSTAT     0x342c /* use R300_DSTCACHE_CTLSTAT */
+#define R300_DSTCACHE_CTLSTAT          0x1714
+#      define R300_RB2D_DC_FLUSH               (3 << 0)
+#      define R300_RB2D_DC_FREE                (3 << 2)
+#      define R300_RB2D_DC_FLUSH_ALL           0xf
+#      define R300_RB2D_DC_BUSY                (1 << 31)
 #define RADEON_RB3D_CNTL               0x1c3c
 #      define RADEON_ALPHA_BLEND_ENABLE        (1 << 0)
 #      define RADEON_PLANE_MASK_ENABLE         (1 << 1)
@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #      define RADEON_RB3D_ZC_FREE              (1 << 2)
 #      define RADEON_RB3D_ZC_FLUSH_ALL         0x5
 #      define RADEON_RB3D_ZC_BUSY              (1 << 31)
+#define R300_ZB_ZCACHE_CTLSTAT                  0x4f18
+#      define R300_ZC_FLUSH                    (1 << 0)
+#      define R300_ZC_FREE                     (1 << 1)
+#      define R300_ZC_FLUSH_ALL                0x3
+#      define R300_ZC_BUSY                     (1 << 31)
 #define RADEON_RB3D_DSTCACHE_CTLSTAT   0x325c
 #      define RADEON_RB3D_DC_FLUSH             (3 << 0)
 #      define RADEON_RB3D_DC_FREE              (3 << 2)
 #      define RADEON_RB3D_DC_FLUSH_ALL         0xf
 #      define RADEON_RB3D_DC_BUSY              (1 << 31)
+#define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
+#      define R300_RB3D_DC_FINISH              (1 << 4)
 #define RADEON_RB3D_ZSTENCILCNTL       0x1c2c
 #      define RADEON_Z_TEST_MASK               (7 << 4)
 #      define RADEON_Z_TEST_ALWAYS             (7 << 4)
@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 
 #define R200_VAP_PVS_CNTL_1               0x22D0
 
+#define R500_D1CRTC_STATUS 0x609c
+#define R500_D2CRTC_STATUS 0x689c
+#define R500_CRTC_V_BLANK (1<<0)
+
+#define R500_D1CRTC_FRAME_COUNT 0x60a4
+#define R500_D2CRTC_FRAME_COUNT 0x68a4
+
+#define R500_D1MODE_V_COUNTER 0x6530
+#define R500_D2MODE_V_COUNTER 0x6d30
+
+#define R500_D1MODE_VBLANK_STATUS 0x6534
+#define R500_D2MODE_VBLANK_STATUS 0x6d34
+#define R500_VBLANK_OCCURED (1<<0)
+#define R500_VBLANK_ACK     (1<<4)
+#define R500_VBLANK_STAT    (1<<12)
+#define R500_VBLANK_INT     (1<<16)
+
+#define R500_DxMODE_INT_MASK 0x6540
+#define R500_D1MODE_INT_MASK (1<<0)
+#define R500_D2MODE_INT_MASK (1<<8)
+
+#define R500_DISP_INTERRUPT_STATUS 0x7edc
+#define R500_D1_VBLANK_INTERRUPT (1 << 4)
+#define R500_D2_VBLANK_INTERRUPT (1 << 5)
+
 /* Constants */
 #define RADEON_MAX_USEC_TIMEOUT                100000  /* 100 ms */
 
@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_READ8(reg)      DRM_READ8(  dev_priv->mmio, (reg) )
 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
 
-#define RADEON_WRITE_PLL( addr, val )                                  \
+#define RADEON_WRITE_PLL(addr, val)                                    \
 do {                                                                   \
-       RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,                         \
+       RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX,                          \
                       ((addr) & 0x1f) | RADEON_PLL_WR_EN );            \
-       RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );                  \
+       RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));                    \
 } while (0)
 
-#define RADEON_WRITE_IGPGART( addr, val )                              \
+#define RADEON_WRITE_PCIE(addr, val)                                   \
 do {                                                                   \
-       RADEON_WRITE( RADEON_IGPGART_INDEX,                             \
-                       ((addr) & 0x7f) | (1 << 8));                    \
-       RADEON_WRITE( RADEON_IGPGART_DATA, (val) );                     \
-       RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f );                     \
+       RADEON_WRITE8(RADEON_PCIE_INDEX,                                \
+                       ((addr) & 0xff));                               \
+       RADEON_WRITE(RADEON_PCIE_DATA, (val));                  \
 } while (0)
 
-#define RADEON_WRITE_PCIE( addr, val )                                 \
-do {                                                                   \
-       RADEON_WRITE8( RADEON_PCIE_INDEX,                               \
-                       ((addr) & 0xff));                               \
-       RADEON_WRITE( RADEON_PCIE_DATA, (val) );                        \
+#define R500_WRITE_MCIND(addr, val)                                    \
+do {                                                           \
+       RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));    \
+       RADEON_WRITE(R520_MC_IND_DATA, (val));                  \
+       RADEON_WRITE(R520_MC_IND_INDEX, 0);     \
 } while (0)
 
-#define RADEON_WRITE_MCIND( addr, val )                                        \
-       do {                                                            \
-               RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));    \
-               RADEON_WRITE(R520_MC_IND_DATA, (val));                  \
-               RADEON_WRITE(R520_MC_IND_INDEX, 0);     \
-       } while (0)
+#define RS480_WRITE_MCIND(addr, val)                           \
+do {                                                                   \
+       RADEON_WRITE(RS480_NB_MC_INDEX,                         \
+                       ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);       \
+       RADEON_WRITE(RS480_NB_MC_DATA, (val));                  \
+       RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);                  \
+} while (0)
 
-#define RS690_WRITE_MCIND( addr, val )                                 \
+#define RS690_WRITE_MCIND(addr, val)                                   \
 do {                                                           \
        RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));    \
        RADEON_WRITE(RS690_MC_DATA, val);                       \
        RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);    \
 } while (0)
 
+#define IGP_WRITE_MCIND(addr, val)                             \
+do {                                                                   \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \
+               RS690_WRITE_MCIND(addr, val);                           \
+       else                                                            \
+               RS480_WRITE_MCIND(addr, val);                           \
+} while (0)
+
 #define CP_PACKET0( reg, n )                                           \
        (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET0_TABLE( reg, n )                                     \
@@ -1154,23 +1241,43 @@ do {                                                            \
 } while (0)
 
 #define RADEON_FLUSH_CACHE() do {                                      \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
-       OUT_RING( RADEON_RB3D_DC_FLUSH );                               \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
+               OUT_RING(RADEON_RB3D_DC_FLUSH);                         \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_DC_FLUSH);                         \
+       }                                                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {                                      \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
-       OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );                           \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
+               OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+       }                                                               \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {                                     \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );        \
-       OUT_RING( RADEON_RB3D_ZC_FLUSH );                               \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_ZC_FLUSH);                         \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));        \
+               OUT_RING(R300_ZC_FLUSH);                                \
+       }                                                               \
 } while (0)
 
 #define RADEON_PURGE_ZCACHE() do {                                     \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );        \
-       OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );                           \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);                     \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+               OUT_RING(R300_ZC_FLUSH_ALL);                            \
+       }                                                               \
 } while (0)
 
 /* ================================================================
index 009af38..ee40d19 100644 (file)
@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
        return radeon_wait_irq(dev, irqwait->irq_seq);
 }
 
-static void radeon_enable_interrupt(struct drm_device *dev)
+void radeon_enable_interrupt(struct drm_device *dev)
 {
        drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h
new file mode 100644 (file)
index 0000000..a348c9e
--- /dev/null
@@ -0,0 +1,1844 @@
+/*
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RADEON_MICROCODE_H
+#define RADEON_MICROCODE_H
+
+/* production radeon ucode r1xx-r6xx */
+static const u32 R100_cp_microcode[][2] = {
+    { 0x21007000, 0000000000 },
+    { 0x20007000, 0000000000 },
+    { 0x000000b4, 0x00000004 },
+    { 0x000000b8, 0x00000004 },
+    { 0x6f5b4d4c, 0000000000 },
+    { 0x4c4c427f, 0000000000 },
+    { 0x5b568a92, 0000000000 },
+    { 0x4ca09c6d, 0000000000 },
+    { 0xad4c4c4c, 0000000000 },
+    { 0x4ce1af3d, 0000000000 },
+    { 0xd8afafaf, 0000000000 },
+    { 0xd64c4cdc, 0000000000 },
+    { 0x4cd10d10, 0000000000 },
+    { 0x000f0000, 0x00000016 },
+    { 0x362f242d, 0000000000 },
+    { 0x00000012, 0x00000004 },
+    { 0x000f0000, 0x00000016 },
+    { 0x362f282d, 0000000000 },
+    { 0x000380e7, 0x00000002 },
+    { 0x04002c97, 0x00000002 },
+    { 0x000f0001, 0x00000016 },
+    { 0x333a3730, 0000000000 },
+    { 0x000077ef, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00000017, 0x00000004 },
+    { 0x0003802b, 0x00000002 },
+    { 0x040067e0, 0x00000002 },
+    { 0x00000017, 0x00000004 },
+    { 0x000077e0, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x000037e1, 0x00000002 },
+    { 0x040067e1, 0x00000006 },
+    { 0x000077e0, 0x00000002 },
+    { 0x000077e1, 0x00000002 },
+    { 0x000077e1, 0x00000006 },
+    { 0xffffffff, 0000000000 },
+    { 0x10000000, 0000000000 },
+    { 0x0003802b, 0x00000002 },
+    { 0x040067e0, 0x00000006 },
+    { 0x00007675, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0000002f, 0x00000018 },
+    { 0x0000002f, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x00000030, 0x00000018 },
+    { 0x00000030, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x01605000, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00098000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x64c0603e, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00080000, 0x00000016 },
+    { 0000000000, 0000000000 },
+    { 0x0400251d, 0x00000002 },
+    { 0x00007580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x04002580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x00000049, 0x00000004 },
+    { 0x00005000, 0000000000 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x00019000, 0x00000002 },
+    { 0x00011055, 0x00000014 },
+    { 0x00000055, 0x00000012 },
+    { 0x0400250f, 0x00000002 },
+    { 0x0000504f, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007565, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000058, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x01e655b4, 0x00000002 },
+    { 0x4401b0e4, 0x00000002 },
+    { 0x01c110e4, 0x00000002 },
+    { 0x26667066, 0x00000018 },
+    { 0x040c2565, 0x00000002 },
+    { 0x00000066, 0x00000018 },
+    { 0x04002564, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x0000005d, 0x00000004 },
+    { 0x00401069, 0x00000008 },
+    { 0x00101000, 0x00000002 },
+    { 0x000d80ff, 0x00000002 },
+    { 0x0080006c, 0x00000008 },
+    { 0x000f9000, 0x00000002 },
+    { 0x000e00ff, 0x00000002 },
+    { 0000000000, 0x00000006 },
+    { 0x0000008f, 0x00000018 },
+    { 0x0000005b, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007576, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00009000, 0x00000002 },
+    { 0x00041000, 0x00000002 },
+    { 0x0c00350e, 0x00000002 },
+    { 0x00049000, 0x00000002 },
+    { 0x00051000, 0x00000002 },
+    { 0x01e785f8, 0x00000002 },
+    { 0x00200000, 0x00000002 },
+    { 0x0060007e, 0x0000000c },
+    { 0x00007563, 0x00000002 },
+    { 0x006075f0, 0x00000021 },
+    { 0x20007073, 0x00000004 },
+    { 0x00005073, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007576, 0x00000002 },
+    { 0x00007577, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x0000750f, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00600083, 0x0000000c },
+    { 0x006075f0, 0x00000021 },
+    { 0x000075f8, 0x00000002 },
+    { 0x00000083, 0x00000004 },
+    { 0x000a750e, 0x00000002 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x0020750f, 0x00000002 },
+    { 0x00600086, 0x00000004 },
+    { 0x00007570, 0x00000002 },
+    { 0x00007571, 0x00000002 },
+    { 0x00007572, 0x00000006 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00005000, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00007568, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000095, 0x0000000c },
+    { 0x00058000, 0x00000002 },
+    { 0x0c607562, 0x00000002 },
+    { 0x00000097, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00600096, 0x00000004 },
+    { 0x400070e5, 0000000000 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x000380e5, 0x00000002 },
+    { 0x000000a8, 0x0000001c },
+    { 0x000650aa, 0x00000018 },
+    { 0x040025bb, 0x00000002 },
+    { 0x000610ab, 0x00000018 },
+    { 0x040075bc, 0000000000 },
+    { 0x000075bb, 0x00000002 },
+    { 0x000075bc, 0000000000 },
+    { 0x00090000, 0x00000006 },
+    { 0x00090000, 0x00000002 },
+    { 0x000d8002, 0x00000006 },
+    { 0x00007832, 0x00000002 },
+    { 0x00005000, 0x00000002 },
+    { 0x000380e7, 0x00000002 },
+    { 0x04002c97, 0x00000002 },
+    { 0x00007820, 0x00000002 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x01200000, 0x00000002 },
+    { 0x20077000, 0x00000002 },
+    { 0x01200000, 0x00000002 },
+    { 0x20007000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x0120751b, 0x00000002 },
+    { 0x8040750a, 0x00000002 },
+    { 0x8040750b, 0x00000002 },
+    { 0x00110000, 0x00000002 },
+    { 0x000380e5, 0x00000002 },
+    { 0x000000c6, 0x0000001c },
+    { 0x000610ab, 0x00000018 },
+    { 0x844075bd, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x840075bb, 0x00000002 },
+    { 0x000610ab, 0x00000018 },
+    { 0x844075bc, 0x00000002 },
+    { 0x000000c9, 0x00000004 },
+    { 0x804075bd, 0x00000002 },
+    { 0x800075bb, 0x00000002 },
+    { 0x804075bc, 0x00000002 },
+    { 0x00108000, 0x00000002 },
+    { 0x01400000, 0x00000002 },
+    { 0x006000cd, 0x0000000c },
+    { 0x20c07000, 0x00000020 },
+    { 0x000000cf, 0x00000012 },
+    { 0x00800000, 0x00000006 },
+    { 0x0080751d, 0x00000006 },
+    { 0000000000, 0000000000 },
+    { 0x0000775c, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460275d, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x01e00830, 0x00000002 },
+    { 0x21007000, 0000000000 },
+    { 0x6464614d, 0000000000 },
+    { 0x69687420, 0000000000 },
+    { 0x00000073, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x00005000, 0x00000002 },
+    { 0x000380d0, 0x00000002 },
+    { 0x040025e0, 0x00000002 },
+    { 0x000075e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000380e0, 0x00000002 },
+    { 0x04002394, 0x00000002 },
+    { 0x00005000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x00000008, 0000000000 },
+    { 0x00000004, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R200_cp_microcode[][2] = {
+    { 0x21007000, 0000000000 },
+    { 0x20007000, 0000000000 },
+    { 0x000000bf, 0x00000004 },
+    { 0x000000c3, 0x00000004 },
+    { 0x7a685e5d, 0000000000 },
+    { 0x5d5d5588, 0000000000 },
+    { 0x68659197, 0000000000 },
+    { 0x5da19f78, 0000000000 },
+    { 0x5d5d5d5d, 0000000000 },
+    { 0x5dee5d50, 0000000000 },
+    { 0xf2acacac, 0000000000 },
+    { 0xe75df9e9, 0000000000 },
+    { 0xb1dd0e11, 0000000000 },
+    { 0xe2afafaf, 0000000000 },
+    { 0x000f0000, 0x00000016 },
+    { 0x452f232d, 0000000000 },
+    { 0x00000013, 0x00000004 },
+    { 0x000f0000, 0x00000016 },
+    { 0x452f272d, 0000000000 },
+    { 0x000f0001, 0x00000016 },
+    { 0x3e4d4a37, 0000000000 },
+    { 0x000077ef, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00000016, 0x00000004 },
+    { 0x0003802a, 0x00000002 },
+    { 0x040067e0, 0x00000002 },
+    { 0x00000016, 0x00000004 },
+    { 0x000077e0, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x000037e1, 0x00000002 },
+    { 0x040067e1, 0x00000006 },
+    { 0x000077e0, 0x00000002 },
+    { 0x000077e1, 0x00000002 },
+    { 0x000077e1, 0x00000006 },
+    { 0xffffffff, 0000000000 },
+    { 0x10000000, 0000000000 },
+    { 0x07f007f0, 0000000000 },
+    { 0x0003802a, 0x00000002 },
+    { 0x040067e0, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007675, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802b, 0x00000002 },
+    { 0x04002676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0000002f, 0x00000018 },
+    { 0x0000002f, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x00000037, 0x00000018 },
+    { 0x00000037, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x01605000, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00098000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x64c06051, 0x00000004 },
+    { 0x00080000, 0x00000016 },
+    { 0000000000, 0000000000 },
+    { 0x0400251d, 0x00000002 },
+    { 0x00007580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x04002580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x0000005a, 0x00000004 },
+    { 0x00005000, 0000000000 },
+    { 0x00061000, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x00019000, 0x00000002 },
+    { 0x00011064, 0x00000014 },
+    { 0x00000064, 0x00000012 },
+    { 0x0400250f, 0x00000002 },
+    { 0x0000505e, 0x00000004 },
+    { 0x00007565, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000065, 0x00000004 },
+    { 0x01e655b4, 0x00000002 },
+    { 0x4401b0f0, 0x00000002 },
+    { 0x01c110f0, 0x00000002 },
+    { 0x26667071, 0x00000018 },
+    { 0x040c2565, 0x00000002 },
+    { 0x00000071, 0x00000018 },
+    { 0x04002564, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000068, 0x00000004 },
+    { 0x00401074, 0x00000008 },
+    { 0x00101000, 0x00000002 },
+    { 0x000d80ff, 0x00000002 },
+    { 0x00800077, 0x00000008 },
+    { 0x000f9000, 0x00000002 },
+    { 0x000e00ff, 0x00000002 },
+    { 0000000000, 0x00000006 },
+    { 0x00000094, 0x00000018 },
+    { 0x00000068, 0x00000004 },
+    { 0x00007576, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00009000, 0x00000002 },
+    { 0x00041000, 0x00000002 },
+    { 0x0c00350e, 0x00000002 },
+    { 0x00049000, 0x00000002 },
+    { 0x00051000, 0x00000002 },
+    { 0x01e785f8, 0x00000002 },
+    { 0x00200000, 0x00000002 },
+    { 0x00600087, 0x0000000c },
+    { 0x00007563, 0x00000002 },
+    { 0x006075f0, 0x00000021 },
+    { 0x2000707c, 0x00000004 },
+    { 0x0000507c, 0x00000004 },
+    { 0x00007576, 0x00000002 },
+    { 0x00007577, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x0000750f, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x0060008a, 0x0000000c },
+    { 0x006075f0, 0x00000021 },
+    { 0x000075f8, 0x00000002 },
+    { 0x0000008a, 0x00000004 },
+    { 0x000a750e, 0x00000002 },
+    { 0x0020750f, 0x00000002 },
+    { 0x0060008d, 0x00000004 },
+    { 0x00007570, 0x00000002 },
+    { 0x00007571, 0x00000002 },
+    { 0x00007572, 0x00000006 },
+    { 0x00005000, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00007568, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000098, 0x0000000c },
+    { 0x00058000, 0x00000002 },
+    { 0x0c607562, 0x00000002 },
+    { 0x0000009a, 0x00000004 },
+    { 0x00600099, 0x00000004 },
+    { 0x400070f1, 0000000000 },
+    { 0x000380f1, 0x00000002 },
+    { 0x000000a7, 0x0000001c },
+    { 0x000650a9, 0x00000018 },
+    { 0x040025bb, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x040075bc, 0000000000 },
+    { 0x000075bb, 0x00000002 },
+    { 0x000075bc, 0000000000 },
+    { 0x00090000, 0x00000006 },
+    { 0x00090000, 0x00000002 },
+    { 0x000d8002, 0x00000006 },
+    { 0x00005000, 0x00000002 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x01665000, 0x00000002 },
+    { 0x000a0000, 0x00000002 },
+    { 0x000671cc, 0x00000002 },
+    { 0x0286f1cd, 0x00000002 },
+    { 0x000000b7, 0x00000010 },
+    { 0x21007000, 0000000000 },
+    { 0x000000be, 0x0000001c },
+    { 0x00065000, 0x00000002 },
+    { 0x000a0000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x000b0000, 0x00000002 },
+    { 0x38067000, 0x00000002 },
+    { 0x000a00ba, 0x00000004 },
+    { 0x20007000, 0000000000 },
+    { 0x01200000, 0x00000002 },
+    { 0x20077000, 0x00000002 },
+    { 0x01200000, 0x00000002 },
+    { 0x20007000, 0000000000 },
+    { 0x00061000, 0x00000002 },
+    { 0x0120751b, 0x00000002 },
+    { 0x8040750a, 0x00000002 },
+    { 0x8040750b, 0x00000002 },
+    { 0x00110000, 0x00000002 },
+    { 0x000380f1, 0x00000002 },
+    { 0x000000d1, 0x0000001c },
+    { 0x000610aa, 0x00000018 },
+    { 0x844075bd, 0x00000002 },
+    { 0x000610a9, 0x00000018 },
+    { 0x840075bb, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x844075bc, 0x00000002 },
+    { 0x000000d4, 0x00000004 },
+    { 0x804075bd, 0x00000002 },
+    { 0x800075bb, 0x00000002 },
+    { 0x804075bc, 0x00000002 },
+    { 0x00108000, 0x00000002 },
+    { 0x01400000, 0x00000002 },
+    { 0x006000d8, 0x0000000c },
+    { 0x20c07000, 0x00000020 },
+    { 0x000000da, 0x00000012 },
+    { 0x00800000, 0x00000006 },
+    { 0x0080751d, 0x00000006 },
+    { 0x000025bb, 0x00000002 },
+    { 0x000040d4, 0x00000004 },
+    { 0x0000775c, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460275d, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x00007999, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460299b, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x01e00830, 0x00000002 },
+    { 0x21007000, 0000000000 },
+    { 0x00005000, 0x00000002 },
+    { 0x00038056, 0x00000002 },
+    { 0x040025e0, 0x00000002 },
+    { 0x000075e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000380ed, 0x00000002 },
+    { 0x04007394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000078c4, 0x00000002 },
+    { 0x000078c5, 0x00000002 },
+    { 0x000078c6, 0x00000002 },
+    { 0x00007924, 0x00000002 },
+    { 0x00007925, 0x00000002 },
+    { 0x00007926, 0x00000002 },
+    { 0x000000f2, 0x00000004 },
+    { 0x00007924, 0x00000002 },
+    { 0x00007925, 0x00000002 },
+    { 0x00007926, 0x00000002 },
+    { 0x000000f9, 0x00000004 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R300_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x000000ae, 0x00000008 },
+    { 0x000000b2, 0x00000008 },
+    { 0x67554b4a, 0000000000 },
+    { 0x4a4a4475, 0000000000 },
+    { 0x55527d83, 0000000000 },
+    { 0x4a8c8b65, 0000000000 },
+    { 0x4aef4af6, 0000000000 },
+    { 0x4ae14a4a, 0000000000 },
+    { 0xe4979797, 0000000000 },
+    { 0xdb4aebdd, 0000000000 },
+    { 0x9ccc4a4a, 0000000000 },
+    { 0xd1989898, 0000000000 },
+    { 0x4a0f9ad6, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000080, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00012000, 0x00000004 },
+    { 0x00082000, 0x00000004 },
+    { 0x1800650e, 0x00000004 },
+    { 0x00092000, 0x00000004 },
+    { 0x000a2000, 0x00000004 },
+    { 0x000f0000, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000074, 0x00000018 },
+    { 0x0000e563, 0x00000004 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0000a069, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000077, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000077, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0007a, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000084, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000086, 0x00000008 },
+    { 0x00c00085, 0x00000008 },
+    { 0x000700e3, 0x00000004 },
+    { 0x00000092, 0x00000038 },
+    { 0x000ca094, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x000000a4, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x000000a1, 0x00000008 },
+    { 0x000000a6, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x000000ad, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x001400a9, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700e3, 0x00000004 },
+    { 0x000000c0, 0x00000038 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2094, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000c3, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000c7, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000c9, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080c3, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700e0, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000e4, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000eb, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000f3, 0x00000034 },
+    { 0x000000f0, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R420_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x00000099, 0x00000008 },
+    { 0x0000009d, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0xd9d3dff6, 0000000000 },
+    { 0x4ac54a4a, 0000000000 },
+    { 0xc8828282, 0000000000 },
+    { 0xbf4acfc1, 0000000000 },
+    { 0x87b04a4a, 0000000000 },
+    { 0xb5838383, 0000000000 },
+    { 0x4a0f85ba, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700c7, 0x00000004 },
+    { 0x00000080, 0x00000038 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x0000008f, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x0000008c, 0x00000008 },
+    { 0x00000091, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x00000098, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x00140094, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700c7, 0x00000004 },
+    { 0x000000a4, 0x00000038 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000ab, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000ad, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080a7, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c4, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000c8, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cf, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000d7, 0x00000034 },
+    { 0x000000d4, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x0000e1cc, 0x00000004 },
+    { 0x0500e1cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000de, 0x00000034 },
+    { 0x000000da, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x0019e1cc, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x0500a000, 0x00000004 },
+    { 0x080041cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 RS600_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x000000a0, 0x00000008 },
+    { 0x000000a4, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0x4ae74af6, 0000000000 },
+    { 0x4ad34a4a, 0000000000 },
+    { 0xd6898989, 0000000000 },
+    { 0xcd4addcf, 0000000000 },
+    { 0x8ebe4ae2, 0000000000 },
+    { 0xc38a8a8a, 0000000000 },
+    { 0x4a0f8cc8, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700d5, 0x00000004 },
+    { 0x00000084, 0x00000038 },
+    { 0x000ca086, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000096, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x00000093, 0x00000008 },
+    { 0x00000098, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000009f, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x0014009b, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700d5, 0x00000004 },
+    { 0x000000b2, 0x00000038 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2086, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000b5, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000b9, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000bb, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080b5, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700d2, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000d6, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000dd, 0x00000008 },
+    { 0x00e00116, 0000000000 },
+    { 0x000700e1, 0x00000004 },
+    { 0x0800401c, 0x00000004 },
+    { 0x200050e7, 0x00000004 },
+    { 0x0000e01d, 0x00000004 },
+    { 0x000000e4, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000eb, 0x00000034 },
+    { 0x000000e8, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 RS690_cp_microcode[][2] = {
+    { 0x000000dd, 0x00000008 },
+    { 0x000000df, 0x00000008 },
+    { 0x000000a0, 0x00000008 },
+    { 0x000000a4, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0x4ad74af6, 0000000000 },
+    { 0x4ac94a4a, 0000000000 },
+    { 0xcc898989, 0000000000 },
+    { 0xc34ad3c5, 0000000000 },
+    { 0x8e4a4a4a, 0000000000 },
+    { 0x4a8a8a8a, 0000000000 },
+    { 0x4a0f8c4a, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700cb, 0x00000004 },
+    { 0x00000084, 0x00000038 },
+    { 0x000ca086, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000096, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x00000093, 0x00000008 },
+    { 0x00000098, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000009f, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x0014009b, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x00100000, 0x0000002c },
+    { 0x00004000, 0000000000 },
+    { 0x080045c8, 0x00000004 },
+    { 0x00240005, 0x00000004 },
+    { 0x08004d0b, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700cb, 0x00000004 },
+    { 0x000000b7, 0x00000038 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2086, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000ba, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000be, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000c0, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080ba, 0x00000008 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c8, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cc, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000d3, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000db, 0x00000034 },
+    { 0x000000d8, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x000000e1, 0x00000030 },
+    { 0x4200e000, 0000000000 },
+    { 0x000000e1, 0x00000030 },
+    { 0x4000e000, 0000000000 },
+    { 0x0025001b, 0x00000004 },
+    { 0x00230000, 0x00000004 },
+    { 0x00250005, 0x00000004 },
+    { 0x000000e6, 0x00000034 },
+    { 0000000000, 0x0000000c },
+    { 0x00244000, 0x00000004 },
+    { 0x080045c8, 0x00000004 },
+    { 0x00240005, 0x00000004 },
+    { 0x08004d0b, 0x0000000c },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R520_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x00000099, 0x00000008 },
+    { 0x0000009d, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0xe0dae6f6, 0000000000 },
+    { 0x4ac54a4a, 0000000000 },
+    { 0xc8828282, 0000000000 },
+    { 0xbf4acfc1, 0000000000 },
+    { 0x87b04ad5, 0000000000 },
+    { 0xb5838383, 0000000000 },
+    { 0x4a0f85ba, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047,&