drm/i915: Add an interface to dynamically change the cache level
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 4 Apr 2011 08:44:39 +0000 (09:44 +0100)
committerKeith Packard <keithp@keithp.com>
Fri, 10 Jun 2011 04:51:16 +0000 (21:51 -0700)
commite4ffd173a1c2f96b43127c2537dd99d89e759bba
tree932a67f5eebb7884ba6b28a4ebf0893d84a44eec
parentd5bd144959e639443f387c34989cec7c9efff091
drm/i915: Add an interface to dynamically change the cache level

[anholt v2: Don't forget that when going from cached to uncached, we
haven't been tracking the write domain from the CPU perspective, since
we haven't needed it for GPU coherency.]

[ickle v3: We also need to make sure we relinquish any fences on older
chipsets and clear the GTT for sane domain tracking.]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/intel_ringbuffer.c