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(parent: 7af0ea5) | patch
serial: of: add a PORT_RT2880 definition
authorJohn Crispin <blogic@openwrt.org>
Thu, 16 Oct 2014 19:48:21 +0000 (21:48 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 6 Nov 2014 22:57:18 +0000 (14:57 -0800)
commit9b8777e3473e31b2aabd669e5f34866d4a3afb6a
tree151015ce45bd2bc3284b1bcbebbedb462f7e690dtree | snapshot
parent7af0ea5dee68c18259b07b86835d2648156d47f4commit | diff
serial: of: add a PORT_RT2880 definition

The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/8250/8250_core.c diff | blob | history
drivers/tty/serial/of_serial.c diff | blob | history
include/uapi/linux/serial_core.h diff | blob | history
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