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ASoC: Debugged improper setting of PLL fields in WM8580 driver
authorjassi brar <jassisinghbrar@gmail.com>
Tue, 1 Sep 2009 02:35:08 +0000 (11:35 +0900)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Tue, 1 Sep 2009 10:37:41 +0000 (11:37 +0100)
commit5c0d38c9478e79ab7deb1b470dd181d2308a608e
treec0342e0d3614bab54473e59f144d849925a950fbtree | snapshot
parentdce944dbb2d0046628bcdba882e8edc2c1d93200commit | diff
ASoC: Debugged improper setting of PLL fields in WM8580 driver

Bug was caught while trying to use WM8580 as I2S master on SMDK.
Symptoms were lesser LRCLK read by CRO(41.02 instead of 44.1 KHz) Solved
by referring to WM8580A manual and setting mask value correctly and
making the code to not touch 'reserved' bits of PLL4 register.

Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
sound/soc/codecs/wm8580.c diff | blob | history
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