drm/i915: Force sync command ordering (Gen6+)
authorBen Widawsky <ben@bwidawsk.net>
Tue, 13 Dec 2011 03:21:58 +0000 (19:21 -0800)
committerBen Hutchings <ben@decadent.org.uk>
Fri, 11 May 2012 12:14:38 +0000 (13:14 +0100)
commit487020e781b754a33510169f05d08f07ca83979f
treed9bb2c7f41843867ff13ba7bb49dc4fd3a3cba7c
parent4829cd25743cd337e484b8cd69e3f434c577f0cb
drm/i915: Force sync command ordering (Gen6+)

commit 84f9f938be4156e4baea466688bd6abae1c9e6ba upstream.

The docs say this is required for Gen7, and since the bit was added for
Gen6, we are also setting it there pit pf paranoia. Particularly as
Chris points out, if PIPE_CONTROL counts as a 3d state packet.

This was found through doc inspection by Ken and applies to Gen6+;

Reported-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c