x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC
authorAndreas Herrmann <andreas.herrmann3@amd.com>
Thu, 18 Sep 2008 19:12:10 +0000 (21:12 +0200)
committerThomas Gleixner <tglx@linutronix.de>
Tue, 23 Sep 2008 09:38:53 +0000 (11:38 +0200)
commit09bfeea13cea843fb03eaa96b5d891fa0abdcc90
tree83777d26c3029d373d67f61f6d08884ae275cea3
parenta8d6829044901a67732904be5f1eacdf8539604f
x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC

Impact: Functional TSC is marked unstable on AMD family 0x10 and 0x11 CPUs.

This would be wrong because for those CPUs "invariant TSC" means:

   "The TSC counts at the same rate in all P-states, all C states, S0,
   or S1"

(See "Processor BIOS and Kernel Developer's Guides" for those CPUs.)

[ tglx: Changed C1E to AMD C1E in the printks to avoid confusion
with Intel C1E ]

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/kernel/process.c