Masahiro Yamada [Fri, 11 Sep 2015 11:17:35 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 11 Sep 2015 11:17:34 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 11 Sep 2015 11:17:33 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Peng Fan [Tue, 15 Sep 2015 06:05:08 +0000 (14:05 +0800)]
imx: fix coding style
Fix coding style.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Tue, 15 Sep 2015 06:05:07 +0000 (14:05 +0800)]
imx: mx7dsabresd: drop code for CONFIG_CMD_BMODE
We use outer pmic reset and drop internal reset signal, bmode will
not work as expected, so drop boot mode code for 7dsabresd board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Adrian Alonso <aalonso@freescale.com>
Peng Fan [Tue, 15 Sep 2015 06:05:06 +0000 (14:05 +0800)]
imx-common: wrap boot_mode_apply with CONFIG_CMD_BMODE
boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Tue, 15 Sep 2015 06:05:05 +0000 (14:05 +0800)]
imx: mx7: discard unused global variable
Discard unused global variable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Sun, 20 Sep 2015 14:26:01 +0000 (22:26 +0800)]
imx: boards: Add maintainers info
Add MAINTAINERS info for mx6slevk_spl, mx6ul_9x9_evk and mx6qpsabreauto.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Wed, 23 Sep 2015 03:13:28 +0000 (11:13 +0800)]
imx-common: consider mux_ctrl_ofs when setting mux_mode
Some i.MXes use __NA_ or 0 to avoid setting mux_mode, but the following patch
only take i.MX6/7 into consideration.
"
c3c8a5748897b24f18618047804317167a531dd3 imx-common: fix iomux settings"
Use is_soc_type(MXC_CPU_MX7) to avoid breaking other i.MXes when
setting mux_mode.
In this patch, switch to use "asm/imx-common/sys_proto.h" to avoid
build break for "is_soc_type" for vf610 and mx25.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Marek Vasut [Thu, 24 Sep 2015 07:06:06 +0000 (09:06 +0200)]
arm: socfpga: Enable env support on MCV
Enable support for env in eMMC on MCV SoM.
Signed-off-by: Marek Vasut <marex@denx.de>
Dinh Nguyen [Wed, 23 Sep 2015 20:38:01 +0000 (15:38 -0500)]
arm: socfpga: Enable saveenv for SD/MMC
Enable the able to save the environment variables when SD/MMC is used.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Masahiro Yamada [Fri, 11 Sep 2015 11:17:32 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier pinctrl core support
The core support for the pinctrl drivers for all the UniPhier SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 23 Sep 2015 02:09:31 +0000 (22:09 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Dinh Nguyen [Tue, 22 Sep 2015 22:01:33 +0000 (17:01 -0500)]
arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdk
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh Nguyen [Tue, 22 Sep 2015 22:01:32 +0000 (17:01 -0500)]
arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files
Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Stefan Roese [Thu, 17 Sep 2015 15:30:29 +0000 (17:30 +0200)]
arm: socfpga: Fix cache configuration
By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache
policy is selected. This leads to much better performance on the SoCFPGA.
A quick network test shows this:
Without this patch:
=> tftp 100000 big-40mb
Speed: 1000, full duplex
Using dwmac.
ff702000 device
TFTP from server 192.168.1.54; our IP address is 192.168.1.252
Filename 'big-40mb'.
Load address: 0x100000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
##########################
2.5 MiB/s
With this patch:
=> tftp 100000 big-40mb
Speed: 1000, full duplex
Using dwmac.
ff702000 device
TFTP from server 192.168.1.54; our IP address is 192.168.1.252
Filename 'big-40mb'.
Load address: 0x100000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
##########################
7.6 MiB/s
A performance improvement of factor ~3.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:36 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add GPL-2.0+ SPDX-License-Identifier
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:35 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add commands for VLAN ingress filtering
The command:
ethsw [port <port_no>] ingress filtering
{ [help] | show | enable | disable }
- enable/disable VLAN ingress filtering on port
can be used to enable/disable/show VLAN ingress filtering on a port.
This command has also been added to the ethsw generic parser
from common/cmd_ethsw.c
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:34 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add command for shared/private VLAN learning
The command:
ethsw vlan fdb { [help] | show | shared | private }
- make VLAN learning shared or private"
configures the FDB to share the FDB entries learned on multiple VLANs
or to keep them separated. By default, the FBD uses private VLAN
learning. This command has also been added to the ethsw generic parser
from common/cmd_ethsw.c
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:33 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add VLAN commands for VSC9953
The new added commands can be used to configure VLANs for a port
on both ingress and egress.
The new commands are:
ethsw [port <port_no>] pvid { [help] | show | <pvid> }
- set/show PVID (ingress and egress VLAN tagging) for a port;
ethsw [port <port_no>] vlan { [help] | show | add <vid> | del <vid> }
- add a VLAN to a port (VLAN members);
ethsw [port <port_no>] untagged { [help] | show | all | none | pvid }
- set egress tagging mod for a port"
ethsw [port <port_no>] egress tag { [help] | show | pvid | classified }
- Configure VID source for egress tag. Tag's VID could be the
frame's classified VID or the PVID of the port
These commands have also been added to the ethsw generic parser from
common/cmd_ethsw.c
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Wed, 9 Sep 2015 15:00:52 +0000 (18:00 +0300)]
drivers/net/vsc9953: Add commands to manipulate the FDB for VSC9953
The new command:
ethsw [port <port_no>] [vlan <vid>] fdb
{ [help] | show | flush | { add | del } <mac> }
Can be used to add and delete FDB entries. Also, the command can be used
to show entries from the FDB tables. When used with [port <port_no>]
and [vlan <vid>], only the matching the FDB entries can be seen or
flushed. The command has also been added to the generic ethsw parser
from cmd_ethsw.c.
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Wed, 9 Sep 2015 15:00:51 +0000 (18:00 +0300)]
common/env_flags.c: Add function to validate a MAC address
The code that checks if a string has the format of a MAC address has been
moved to a separate function called eth_validate_ethaddr_str().
This has been done to allow other components (such as vsc9953 driver)
to validate a MAC address.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:30 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add commands to enable/disable HW learning
The command:
ethsw [port <port_no>] learning { [help] | show | auto | disable }
can be used to enable/disable HW learning on a port.
This patch also adds this command to the generic ethsw parser from
cmd_ethsw.
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:29 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add command to show/clear port counters
The new added command:
ethsw [port <port_no>] statistics { [help] | [clear] }
will print counters like the number of Rx/Tx frames,
number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc.
This patch also adds this commnd in the genereric ethsw
parser from cmd_ethsw.c
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:28 +0000 (16:55 +0300)]
drivers/net/vsc9953: Use the generic Ethernet Switch parser
This patch replaces the parser used by VSC9953 L2 Switch driver with
the generic one. Also, the config macro that enables the
VSC9953 commands has been replaced in all the platforms that
use this driver with the config macro that corresponds to the
generic parser.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:27 +0000 (16:55 +0300)]
common/cmd_ethsw: Add generic commands for Ethernet Switches
This patch creates a flexible parser for Ethernet Switch
configurations that should support complex commands.
The parser searches for predefined keywords in the command
and calls the proper function when a match is found.
Also, the parser allows for optional keywords, such as
"port", to apply the command on a port
or on all ports. For now, the defined commands are:
ethsw [port <port_no>] { enable | disable | show }
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:26 +0000 (16:55 +0300)]
drivers/net/vsc9953: Add default configuration for VSC9953 L2 Switch
At startup, the default configuration should be:
- enable HW learning on all ports (HW default);
- all ports are VLAN aware;
- all ports are members of VLAN 1;
- all ports have Port-based VLAN 1;
- on all ports, the switch is allowed to remove
maximum one VLAN tag,
- on egress, the switch should add a VLAN tag if the
frame is classified to a different VLAN than the port's
Port-based VLAN;
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:25 +0000 (16:55 +0300)]
include/bitfield: Add new bitfield operations
These new operations allow manipulation of bitfields
within a word by using a mask instead of width and
shift values to extract/replace the bitfields.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:55:24 +0000 (16:55 +0300)]
drivers/net/vsc9953: Fix missing reserved register
The VSC9953 DS reserves a register between vlan_mask and anag_efil
registers.
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:52:46 +0000 (16:52 +0300)]
drivers/net/vsc9953: Fix bug when enabling a port
When a port is enabled at init time, the initializing function
touches more bits than necessary to enable a port (also touches
reserved bits and default bit values). This patch fixes this issue
by changing the value of the define used to enable the port and
assures that no other bits are changes by replacing out_le32()
with setbits_le32().
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:52:45 +0000 (16:52 +0300)]
drivers/net/vsc9953: Cleanup patch
This patch groups some macros defined for registers and
replaces some magic numbers from vsc9953 with macros. Also,
"port" and "port_nr" words are replaced with "port_no",
puts each variable declaration on a line and removes
unnecessary tabs.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 24 Jul 2015 13:52:44 +0000 (16:52 +0300)]
drivers/net/vsc9953: Remove 'CONFIG_' from macros' name
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Otavio Salvador [Thu, 17 Sep 2015 18:13:20 +0000 (15:13 -0300)]
cgtqmx6eval: Add USB Mass Storage support
=> ums 0 mmc 0 (Mounts the micro SD)
=> ums 0 mmc 1 (Mounts the eMMC)
=> ums 0 mmc 2 (Mounts the big SD)
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 17 Sep 2015 18:13:19 +0000 (15:13 -0300)]
cgtqmx6eval: Add a maintainer entry
Add me as the board maintainer and move the status to 'Maintained'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 17 Sep 2015 18:13:18 +0000 (15:13 -0300)]
cgtqmx6eval: Fit into a single line
The printf can be put in a single line of code, so make it
simpler
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Heiko Schocher [Thu, 17 Sep 2015 08:39:38 +0000 (10:39 +0200)]
imx6, aristaintetos2: add me as maintainer
Add me as Maintainer for the aristainetos2b board.
Signed-off-by: Heiko Schocher <hs@denx.de>
Peng Fan [Mon, 7 Sep 2015 08:12:11 +0000 (16:12 +0800)]
mtd: nand: mxs check maximum ecc that platfrom supports
Check maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Han Xu <b45815@freescale.com>
Tested-By: Tim Harvey <tharvey at gateworks.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Mon, 14 Sep 2015 14:18:34 +0000 (22:18 +0800)]
imx: mx7dsabresd: drop SYS_SOC from board Kconfig
We have defined this kconfig entry in arch/arm/cpu/armv7/mx7/Kconfig,
no need to redefine it in board Kconfig.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Mon, 14 Sep 2015 14:18:33 +0000 (22:18 +0800)]
imx: mx7: drop select CPU_V7 for board target
drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Mon, 14 Sep 2015 14:06:32 +0000 (11:06 -0300)]
mx6ul_14x14_evk: Remove get_board_rev()
get_board_rev() is not actually providing the board revision.
It just returns the CPU revision instead.
As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Mon, 14 Sep 2015 14:06:31 +0000 (11:06 -0300)]
mx6ul_14x14_evk: Staticize when possible
Make the internal symbols static when possible.
This prevents sparse build warnings.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Mon, 14 Sep 2015 14:06:30 +0000 (11:06 -0300)]
mx6ul_14x14_evk: Remove dead code
iox74lv_set() is not used anywhere, so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sun, 13 Sep 2015 16:06:46 +0000 (13:06 -0300)]
mx7dsabresd: Remove unused config option
CONFIG_FEC_DMA_MINALIGN is not used anywhere, so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sun, 13 Sep 2015 16:06:45 +0000 (13:06 -0300)]
mx7dsabresd: Remove get_board_rev()
get_board_rev() is not actually providing the board revision.
It just returns the CPU revision instead.
As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sun, 13 Sep 2015 16:06:44 +0000 (13:06 -0300)]
mx7dsabresd: Include USB header
Include <usb/ehci-fsl.h> in order to fix the following sparse warning:
board/freescale/mx7dsabresd/mx7dsabresd.c:538:5: warning: symbol 'board_ehci_hcd_init' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sun, 13 Sep 2015 16:06:43 +0000 (13:06 -0300)]
mx7dsabreasd: Remove dead code
iox74lv_set() is not used anywhere, so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sun, 13 Sep 2015 16:06:42 +0000 (13:06 -0300)]
mx7dsabresd: Staticize when possible
Make the internal symbols static when possible.
This prevents sparse build warnings.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 10 Sep 2015 19:03:38 +0000 (16:03 -0300)]
mx6sabre_common: Add Fastboot support
Tested basic fastboot commands, such as:
On the mx6qsabresd U-boot prompt:
=> fastboot 0
On the host PC:
$ fastboot getvar bootloader-version -i 0x0525
bootloader-version: U-Boot 2015.10-rc2-23960-g2462cce-dirty
finished. total time: 0.000s
$ fastboot reboot -i 0x0525 --> board reboots fine.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Peng Fan [Mon, 14 Sep 2015 05:34:45 +0000 (13:34 +0800)]
imx: mx7dsabresd set wdog SRS bit
We use trigger pmic reset to reset the board, so set bit SRS to
disable internal WDOG_RESET_B_DEB to make reset stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Peng Fan [Mon, 14 Sep 2015 05:34:44 +0000 (13:34 +0800)]
imx: wdog: correct wcr register settings
We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set
wcr, since this will override bits set before reset_cpu.
Use clrsetbits_le16 instead of writew to fix this issue.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Sebastian Siewior <bigeasy@linutronix.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Peng Fan [Mon, 14 Sep 2015 05:34:43 +0000 (13:34 +0800)]
imx-common: fix iomux settings
When setting iomux for a pin mux, there is no need to check mux_ctrl_ofs.
Also If still checking mux_ctrl_ofs, we have no chance to set iomux
for i.MX7D IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00, because the mux_ctrl_ofs
for this register is 0.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Masahiro Yamada [Sat, 5 Sep 2015 16:44:50 +0000 (01:44 +0900)]
pinctrl: move dm_scan_fdt_node() out of pinctrl uclass
Commit
c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs")
added some additional change that was not mentioned in the git-log.
That commit added dm_scan_fdt_node() in the pinctrl uclass binding.
It should be handled by the simple-bus driver or the low-level
driver, not by the pinctrl framework.
I guess Simon's motivation was to bind GPIO banks located under the
Rockchip pinctrl device. It is true some chips have sub-devices
under their pinctrl devices, but it is basically SoC-specific matter.
This commit partly reverts commit
c5acf4a2b3c6 to keep the only
pinctrl-generic features in the uclass. The dm_scan_fdt_node()
should be called from the rk3288_pinctrl driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 17 Sep 2015 21:00:08 +0000 (17:00 -0400)]
Merge git://git.denx.de/u-boot-x86
Tom Rini [Thu, 17 Sep 2015 20:59:58 +0000 (16:59 -0400)]
Merge git://git.denx.de/u-boot-dm
Bin Meng [Mon, 14 Sep 2015 07:07:41 +0000 (00:07 -0700)]
x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.
We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.
With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:30 +0000 (23:20 -0700)]
x86: doc: Add DMI to the TODO list
Desktop Management Interface (DMI) is not supported by U-Boot now.
Add it to the TODO list.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:29 +0000 (23:20 -0700)]
x86: doc: Document some porting hints about Intel Quark
Document porting considerations for Intel Quark based board,
including MRC parameters and PCIe initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:28 +0000 (23:20 -0700)]
x86: galileo: Add PCIe root port IRQ routing
Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:27 +0000 (23:20 -0700)]
x86: quark: Initialize thermal sensor properly
Thermal sensor on Quark SoC needs to be properly initialized per
Quark firmware writer guide, otherwise when booting Linux kernel,
it triggers system shutdown because of wrong temperature in the
thermal sensor is detected by the kernel driver (see below):
[ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down
[ 5.128997] Failed to start orderly shutdown: forcing the issue
[ 5.135495] Emergency Sync complete
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:26 +0000 (23:20 -0700)]
x86: quark: Lock HMBOUND register before jumping to kernel
When Linux kernel boots, it hangs at:
[ 0.829408] Intel Quark side-band driver registered
This happens when Quark kernel Isolated Memory Region (IMR) driver
tries to lock an IMR register to protect kernel's text and rodata
sections. However in order to have IMR function correctly, HMBOUND
register must be locked otherwise the system just hangs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:25 +0000 (23:20 -0700)]
x86: quark: Convert to use clrbits, setbits, clrsetbits macros
Change existing codes to use clrbits, setbits, clrsetbits macros.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:24 +0000 (23:20 -0700)]
x86: quark: Add clrbits, setbits, clrsetbits macros for message port access
On Intel Quark, lots of registers on the message port need be
programmed. Add handy clrbits, setbits, clrsetbits macros for
message port access.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 10 Sep 2015 06:20:23 +0000 (23:20 -0700)]
x86: galileo: Enable random mac address for Quark
Not like other Intel Ethernet controllers (e.g.: E1000), Intel Quark
SoC integrated designware Ethernet controller does not have a chipset
defined way to store/restore mac address. Enable random mac address
so that we can use Ethernet even without 'ethaddr'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 11 Sep 2015 10:24:37 +0000 (03:24 -0700)]
x86: quark: Add PCIe/USB static register programming after memory init
This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 11 Sep 2015 10:24:36 +0000 (03:24 -0700)]
x86: Convert to use driver model eth on quark/galileo
Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 11 Sep 2015 10:24:35 +0000 (03:24 -0700)]
net: designware: Add support to PCI designware devices
The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 11 Sep 2015 10:24:34 +0000 (03:24 -0700)]
dm: pci: Add an inline API to test if a device is on a PCI bus
Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Mon, 31 Aug 2015 10:36:24 +0000 (19:36 +0900)]
dts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrl
These properties are necessary to use full-featured pinctrl drivers
in SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Thierry Reding [Tue, 8 Sep 2015 09:38:04 +0000 (11:38 +0200)]
ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Tue, 8 Sep 2015 09:38:03 +0000 (11:38 +0200)]
ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Mirza Krak [Wed, 19 Aug 2015 11:50:50 +0000 (13:50 +0200)]
ARM: tegra: Add Tegra20 SPI device nodes
Add the device tree node for the SPI controllers found on Tegra20 SOCs.
Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:42:23 +0000 (11:42 +0200)]
p2571: Remove hard-coded counter frequency
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:42:22 +0000 (11:42 +0200)]
p2371: Remove hard-coded counter frequency
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:42:21 +0000 (11:42 +0200)]
e2220-1170: Remove hard-coded counter frequency
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:42:20 +0000 (11:42 +0200)]
ARM: tegra: clk_m is the architected timer source clock
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:42:19 +0000 (11:42 +0200)]
ARM: tegra: Implement clk_m
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Thu, 20 Aug 2015 09:42:18 +0000 (11:42 +0200)]
armv8: Make COUNTER_FREQUENCY optional
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 20 Aug 2015 23:38:42 +0000 (17:38 -0600)]
ARM: tegra: replace V_PROMPT define with kconfig
Commit
181bd9dc61d2 "kconfig: add config option for shell prompt" replaced
define V_PROMPT with Kconfig option SYS_PROMPT. This crossed with patches
adding Tegra T210 boards. Migrate the boards to the new scheme.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 19 Aug 2015 23:03:59 +0000 (17:03 -0600)]
ARM: tegra: fix PLLP frequency calc on T210
AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency
is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on
T210 is the VCO output, and divp is not applied. pllP_out2 does have divp
applied. All other pllP_outN are divided down from pllP_out0. We only
support pllP_out0 in U-Boot at the time of writing.
Fix clock_get_rate() to handle this special case.
This corrects the returned rate for PLLP to be 408MHz rather than 204MHz.
In turn, this causes high enough dividers to be calculated for the various
peripheral clocks that feed off of PLLP. Without this, some peripherals
failed to operate correctly. For instance, one of my SD cards worked
perfectly but an older (presumably slower) card could not be read.
Note that prior to commit
722e000ccd72 "Tegra: PLL: use per-SoC pllinfo
table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was
816MHz since the wrong values were being extracted from the PLLP divider
register. This caused overly large peripheral dividers to be calculated,
which while wrong, didn't cause any correctness issues; things simply ran
slower than they could.
Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 19 Aug 2015 21:15:41 +0000 (15:15 -0600)]
ARM: tegra: fix COUNTER_FREQUENCY for T210
While T210 boards all have 38.4MHz crystals, per the TRM, the only
supported configuration is to divide the crystal frequency by 2 to
generate clk_m, which is what feeds the ARM generic timers amongst other
things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2.
When I queried the 19.2 value in Tom's original T210 patches, I wasn't
aware of this extra divide-by-2, and didn't notice any effect from the
incorrect value, since its only used if U-Boot is booted in EL3, whereas
I'm booting it in EL2.
Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Axel Lin [Wed, 11 Mar 2015 07:16:29 +0000 (15:16 +0800)]
tegra: Remove tegra_spl_gpio_direction_output declaration from header file
This function is deleted by commit
2fccd2d96bad
"tegra: Convert tegra GPIO driver to use driver model".
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Fri, 14 Aug 2015 04:34:22 +0000 (22:34 -0600)]
ARM: tegra: Add p2371-2180 board
P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
two GPIO expansion headers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Wed, 16 Sep 2015 13:53:37 +0000 (09:53 -0400)]
Merge git://git.denx.de/u-boot-fdt
Masahiro Yamada [Tue, 15 Sep 2015 03:54:38 +0000 (12:54 +0900)]
kbuild: fixdep: drop meaningless hash table initialization
The clear_config() is called just once at the beginning of this
program, but the global variable hashtab[] is already zero-filled
at the start-up.
[ Linux commit:
d179e22762fd38414c4108acedd5feca4cf7e0d8 ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
Andreas Färber [Mon, 14 Sep 2015 10:21:34 +0000 (12:21 +0200)]
api_storage: Fix non-first storage device enumeration
When enabling CONFIG_API and chain-loading GRUB2 on jetson-tk1, only the
eMMC would show up as (hd0), but not the SD card, leading to GRUB not
finding its configuration and modules, falling back to a rescue shell.
This is because enum_ended would get set for !more after returning a
cookie for the first MMC device in group 3.
Fix this by properly setting the "more" argument also in the case of the
first storage device of a group.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Stefan Roese [Mon, 14 Sep 2015 07:32:55 +0000 (09:32 +0200)]
arm: Remove unused reference to nomadik
Commit
0abdd9d0 "arm: Remove nhk8815 boards and nomadik arch" missed one
reference to this arch. Lets remove this as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Stefan Roese [Mon, 14 Sep 2015 07:17:36 +0000 (09:17 +0200)]
arm: Remove unused ST-Ericsson u8500 arch
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.
Please note that this patch also removes these config options:
- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.
If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Stefan Roese [Mon, 14 Sep 2015 06:47:47 +0000 (08:47 +0200)]
mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()
This patch addresses some comments raised by Scott in the last versions.
Here the changes in detail:
- Removed __maybe_unused as its not needed
- Added check for strength == 4 and error out for the unsupported
ECC strength values
- Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
will be done in nand_scan_tail()
- Set .caclulate back to fsmc_read_hwecc() in the HW case
- Added comment that this function will only be called on SPEAr platforms,
not supporting the BCH8 HW ECC (FSMC_VER8)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Lukasz Majewski [Sun, 13 Sep 2015 22:57:04 +0000 (00:57 +0200)]
env: import: hashtable: Free memory allocated before exiting from himport_r()
ithout this patch memory is not released on early exit.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Lukasz Majewski [Sun, 13 Sep 2015 22:57:03 +0000 (00:57 +0200)]
env: import: hashtable: Prevent buffer overrun when importing environment from file
Lets consider following scenario:
- One uses echo -n "key=value" to define environment variable in a file (single variable)
- The file content is "key=value" without any terminating byte (e.g. 0x0a or
0x0d).
- The file is loaded to u-boot non zero'ed RAM buffer (with load command).
- Then "env import -t -r $loadaddr $filesize" is executed.
- Due to lack of proper termination byte we have classical example of buffer
overrun.
This patch prevents from this by allocating one extra byte than size and
explicitly null terminate it.
There should be no change for normal env import operation after applying
this patch.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Imran Zaman [Mon, 7 Sep 2015 08:24:08 +0000 (11:24 +0300)]
cli_simple.c: fix possible overflow when copying the string
Bigger source buffer than dest buffer could overflow when copying
strings. Source and destination buffer sizes are same now.
Signed-off-by: Imran Zaman <imran.zaman@intel.com>
Tom Rini [Thu, 3 Sep 2015 18:54:04 +0000 (14:54 -0400)]
ti816x: Switch to SYS_GENERIC_BOARD
Tested on my TI186x rev E. (PG2.0) and take over maintainership.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 3 Sep 2015 18:54:03 +0000 (14:54 -0400)]
ti814x_evm: Switch to SYS_GENERIC_BOARD
Take over maintainership as well. Not tested as PG2.0 (which I have)
needs additional work over PG1.0 (which Matt has).
Cc: Matt Porter <mporter@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 3 Sep 2015 18:54:02 +0000 (14:54 -0400)]
omap3_evm_common.h: Switch to SYS_GENERIC_BOARD
Tested on my OMAP3 uEVM.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Thu, 6 Aug 2015 21:31:02 +0000 (15:31 -0600)]
fdt: add new fdt address parsing functions
fdtdec_get_addr_size() hard-codes the number of cells used to represent
an address or size in DT. This is incorrect in many cases depending on
the DT binding for a particular node or property (e.g. it is incorrect
for the "reg" property). In most cases, DT parsing code must use the
properties #address-cells and #size-cells to parse addres properties.
This change splits up the implementation of fdtdec_get_addr_size() so
that the core logic can be used for both hard-coded and non-hard-coded
cases. Various wrapper functions are implemented that support cases
where hard-coded cell counts should or should not be used, and where
the client does and doesn't know the parent node ID that contains the
properties #address-cells and #size-cells.
dev_get_addr() is updated to use the new functions.
Core functionality in fdtdec_get_addr_size_fixed() is widely tested via
fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and
dev_get_addr() by manually modifying the Tegra I2C driver to invoke them.
Much of the core implementation of fdtdec_get_addr_size_fixed(),
fdtdec_get_addr_size_auto_parent(), and
fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's
previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit".
Based-on-work-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dropped #define DEBUG at the top of fdtdec.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sun, 13 Sep 2015 21:25:16 +0000 (17:25 -0400)]
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
Simon Guinot [Thu, 3 Sep 2015 09:12:20 +0000 (11:12 +0200)]
ARM: Kirkwood: fix IDE configuration on LaCie boards
On the LaCie boards netspace_max_v2 and net2big_v2, two internal hard
drives are available. Additionally on the d2net_v2 board, an extra hard
drive can be plugged via eSATA.
This patch updates CONFIG_SYS_IDE_MAXBUS and CONFIG_SYS_IDE_MAXDEVICE
accordingly for this boards.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Sergey Kostanbaev [Wed, 9 Sep 2015 22:40:01 +0000 (01:40 +0300)]
arm: move edb93xx to generic board architecture
Use CONFIG_SYS_GENERIC_BOARD in EDB93XX board family
Simon Guinot [Tue, 1 Sep 2015 17:01:02 +0000 (19:01 +0200)]
ARM: Kirkwood: enable generic board support for LaCie boards
This patch enables generic board support for the following
Kirkwood-based LaCie boards:
- Network Space v2 (Mini, Lite and Max).
- Internet Space v2.
- D2 Network v2.
- 2Big Network v2.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Fabio Estevam [Fri, 11 Sep 2015 16:32:50 +0000 (13:32 -0300)]
udoo: Fix the error handling in board_eth_init()
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
git.openpandora.org / pandora-u-boot.git / log