Merge branch 'spi/merge' into spi/next

diff --combined arch/arm/mach-ep93xx/core.c
index cc9f1d4,1d4b65f..ce07e0a
--- 1/arch/arm/mach-ep93xx/core.c
--- 2/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@@ -402,11 -402,15 +402,15 @@@ static struct resource ep93xx_eth_resou
        }
  };
  
+ static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
+ 
  static struct platform_device ep93xx_eth_device = {
        .name           = "ep93xx-eth",
        .id             = -1,
        .dev            = {
-               .platform_data  = &ep93xx_eth_data,
+               .platform_data          = &ep93xx_eth_data,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+               .dma_mask               = &ep93xx_eth_dma_mask,
        },
        .num_resources  = ARRAY_SIZE(ep93xx_eth_resource),
        .resource       = ep93xx_eth_resource,
@@@ -488,15 -492,11 +492,15 @@@ static struct resource ep93xx_spi_resou
        },
  };
  
 +static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
 +
  static struct platform_device ep93xx_spi_device = {
        .name           = "ep93xx-spi",
        .id             = 0,
        .dev            = {
 -              .platform_data = &ep93xx_spi_master_data,
 +              .platform_data          = &ep93xx_spi_master_data,
 +              .coherent_dma_mask      = DMA_BIT_MASK(32),
 +              .dma_mask               = &ep93xx_spi_dma_mask,
        },
        .num_resources  = ARRAY_SIZE(ep93xx_spi_resources),
        .resource       = ep93xx_spi_resources,

diff --combined drivers/spi/spi-bfin5xx.c
index f706dba,cc880c9..cc880c9
--- 1/drivers/spi/spi-bfin5xx.c
--- 2/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi-bfin5xx.c
@@@ -681,13 -681,14 +681,14 @@@ static void bfin_spi_pump_transfers(uns
        drv_data->cs_change = transfer->cs_change;
  
        /* Bits per word setup */
-       bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
-       if ((bits_per_word > 0) && (bits_per_word % 16 == 0)) {
+       bits_per_word = transfer->bits_per_word ? :
+               message->spi->bits_per_word ? : 8;
+       if (bits_per_word % 16 == 0) {
                drv_data->n_bytes = bits_per_word/8;
                drv_data->len = (transfer->len) >> 1;
                cr_width = BIT_CTL_WORDSIZE;
                drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
-       } else if ((bits_per_word > 0) && (bits_per_word % 8 == 0)) {
+       } else if (bits_per_word % 8 == 0) {
                drv_data->n_bytes = bits_per_word/8;
                drv_data->len = transfer->len;
                cr_width = 0;

diff --combined drivers/spi/spi-pl022.c
index 77ffd18,d18ce9e..eba88c7
--- 1/drivers/spi/spi-pl022.c
--- 2/drivers/spi/amba-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@@ -1,4 -1,6 +1,4 @@@
  /*
 - * drivers/spi/amba-pl022.c
 - *
   * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
   *
   * Copyright (C) 2008-2009 ST-Ericsson AB
@@@ -40,7 -42,6 +40,7 @@@
  #include <linux/dmaengine.h>
  #include <linux/dma-mapping.h>
  #include <linux/scatterlist.h>
 +#include <linux/pm_runtime.h>
  
  /*
   * This macro is used to define some register default values.
@@@ -382,8 -383,6 +382,8 @@@ struct pl022 
        enum ssp_reading                read;
        enum ssp_writing                write;
        u32                             exp_fifo_level;
 +      enum ssp_rx_level_trig          rx_lev_trig;
 +      enum ssp_tx_level_trig          tx_lev_trig;
        /* DMA settings */
  #ifdef CONFIG_DMA_ENGINE
        struct dma_chan                 *dma_rx_channel;
@@@ -518,7 -517,6 +518,7 @@@ static void giveback(struct pl022 *pl02
        clk_disable(pl022->clk);
        amba_pclk_disable(pl022->adev);
        amba_vcore_disable(pl022->adev);
 +      pm_runtime_put(&pl022->adev->dev);
  }
  
  /**
@@@ -911,10 -909,12 +911,10 @@@ static int configure_dma(struct pl022 *
        struct dma_slave_config rx_conf = {
                .src_addr = SSP_DR(pl022->phybase),
                .direction = DMA_FROM_DEVICE,
 -              .src_maxburst = pl022->vendor->fifodepth >> 1,
        };
        struct dma_slave_config tx_conf = {
                .dst_addr = SSP_DR(pl022->phybase),
                .direction = DMA_TO_DEVICE,
 -              .dst_maxburst = pl022->vendor->fifodepth >> 1,
        };
        unsigned int pages;
        int ret;
@@@ -928,54 -928,6 +928,54 @@@
        if (!rxchan || !txchan)
                return -ENODEV;
  
 +      /*
 +       * If supplied, the DMA burstsize should equal the FIFO trigger level.
 +       * Notice that the DMA engine uses one-to-one mapping. Since we can
 +       * not trigger on 2 elements this needs explicit mapping rather than
 +       * calculation.
 +       */
 +      switch (pl022->rx_lev_trig) {
 +      case SSP_RX_1_OR_MORE_ELEM:
 +              rx_conf.src_maxburst = 1;
 +              break;
 +      case SSP_RX_4_OR_MORE_ELEM:
 +              rx_conf.src_maxburst = 4;
 +              break;
 +      case SSP_RX_8_OR_MORE_ELEM:
 +              rx_conf.src_maxburst = 8;
 +              break;
 +      case SSP_RX_16_OR_MORE_ELEM:
 +              rx_conf.src_maxburst = 16;
 +              break;
 +      case SSP_RX_32_OR_MORE_ELEM:
 +              rx_conf.src_maxburst = 32;
 +              break;
 +      default:
 +              rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
 +              break;
 +      }
 +
 +      switch (pl022->tx_lev_trig) {
 +      case SSP_TX_1_OR_MORE_EMPTY_LOC:
 +              tx_conf.dst_maxburst = 1;
 +              break;
 +      case SSP_TX_4_OR_MORE_EMPTY_LOC:
 +              tx_conf.dst_maxburst = 4;
 +              break;
 +      case SSP_TX_8_OR_MORE_EMPTY_LOC:
 +              tx_conf.dst_maxburst = 8;
 +              break;
 +      case SSP_TX_16_OR_MORE_EMPTY_LOC:
 +              tx_conf.dst_maxburst = 16;
 +              break;
 +      case SSP_TX_32_OR_MORE_EMPTY_LOC:
 +              tx_conf.dst_maxburst = 32;
 +              break;
 +      default:
 +              tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
 +              break;
 +      }
 +
        switch (pl022->read) {
        case READING_NULL:
                /* Use the same as for writing */
@@@ -1544,7 -1496,6 +1544,7 @@@ static void pump_messages(struct work_s
         * and core will be disabled when giveback() is called in each method
         * (poll/interrupt/DMA)
         */
 +      pm_runtime_get_sync(&pl022->adev->dev);
        amba_vcore_enable(pl022->adev);
        amba_pclk_enable(pl022->adev);
        clk_enable(pl022->clk);
@@@ -1678,57 -1629,17 +1678,57 @@@ static int verify_controller_parameters
                        "Communication mode is configured incorrectly\n");
                return -EINVAL;
        }
 -      if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
 -          || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
 +      switch (chip_info->rx_lev_trig) {
 +      case SSP_RX_1_OR_MORE_ELEM:
 +      case SSP_RX_4_OR_MORE_ELEM:
 +      case SSP_RX_8_OR_MORE_ELEM:
 +              /* These are always OK, all variants can handle this */
 +              break;
 +      case SSP_RX_16_OR_MORE_ELEM:
 +              if (pl022->vendor->fifodepth < 16) {
 +                      dev_err(&pl022->adev->dev,
 +                      "RX FIFO Trigger Level is configured incorrectly\n");
 +                      return -EINVAL;
 +              }
 +              break;
 +      case SSP_RX_32_OR_MORE_ELEM:
 +              if (pl022->vendor->fifodepth < 32) {
 +                      dev_err(&pl022->adev->dev,
 +                      "RX FIFO Trigger Level is configured incorrectly\n");
 +                      return -EINVAL;
 +              }
 +              break;
 +      default:
                dev_err(&pl022->adev->dev,
                        "RX FIFO Trigger Level is configured incorrectly\n");
                return -EINVAL;
 +              break;
        }
 -      if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
 -          || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
 +      switch (chip_info->tx_lev_trig) {
 +      case SSP_TX_1_OR_MORE_EMPTY_LOC:
 +      case SSP_TX_4_OR_MORE_EMPTY_LOC:
 +      case SSP_TX_8_OR_MORE_EMPTY_LOC:
 +              /* These are always OK, all variants can handle this */
 +              break;
 +      case SSP_TX_16_OR_MORE_EMPTY_LOC:
 +              if (pl022->vendor->fifodepth < 16) {
 +                      dev_err(&pl022->adev->dev,
 +                      "TX FIFO Trigger Level is configured incorrectly\n");
 +                      return -EINVAL;
 +              }
 +              break;
 +      case SSP_TX_32_OR_MORE_EMPTY_LOC:
 +              if (pl022->vendor->fifodepth < 32) {
 +                      dev_err(&pl022->adev->dev,
 +                      "TX FIFO Trigger Level is configured incorrectly\n");
 +                      return -EINVAL;
 +              }
 +              break;
 +      default:
                dev_err(&pl022->adev->dev,
                        "TX FIFO Trigger Level is configured incorrectly\n");
                return -EINVAL;
 +              break;
        }
        if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
                if ((chip_info->ctrl_len < SSP_BITS_4)
@@@ -1950,6 -1861,7 +1950,7 @@@ static int pl022_setup(struct spi_devic
        }
        if ((clk_freq.cpsdvsr < CPSDVR_MIN)
            || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
+               status = -EINVAL;
                dev_err(&spi->dev,
                        "cpsdvsr is configured incorrectly\n");
                goto err_config_params;
@@@ -1962,9 -1874,6 +1963,9 @@@
                goto err_config_params;
        }
  
 +      pl022->rx_lev_trig = chip_info->rx_lev_trig;
 +      pl022->tx_lev_trig = chip_info->tx_lev_trig;
 +
        /* Now set controller state based on controller data */
        chip->xfer_type = chip_info->com_mode;
        if (!chip_info->cs_control) {
@@@ -2185,8 -2094,6 +2186,8 @@@ pl022_probe(struct amba_device *adev, c
        }
        printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
               adev->res.start, pl022->virtbase);
 +      pm_runtime_enable(dev);
 +      pm_runtime_resume(dev);
  
        pl022->clk = clk_get(&adev->dev, NULL);
        if (IS_ERR(pl022->clk)) {
@@@ -2248,7 -2155,6 +2249,7 @@@
        destroy_queue(pl022);
        pl022_dma_remove(pl022);
        free_irq(adev->irq[0], pl022);
 +      pm_runtime_disable(&adev->dev);
   err_no_irq:
        clk_put(pl022->clk);
   err_no_clk: