Merge branch 'tegra/clk' into next/dt2

This is a dependency for the tegra/dt branch.

Conflicts:
	drivers/clocksource/tegra20_timer.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --combined arch/arm/Kconfig
index 2e4386c,0f7bbe7..318c1f9
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -473,14 -473,12 +473,14 @@@ config ARCH_MX
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
 +      select CLKSRC_OF
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
        select HAVE_CLK_PREPARE
        select MULTI_IRQ_HANDLER
        select PINCTRL
        select SPARSE_IRQ
 +      select STMP_DEVICE
        select USE_OF
        help
          Support for Freescale MXS-based family of processors
@@@ -675,6 -673,7 +675,7 @@@ config ARCH_TEGR
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
+       select SOC_BUS
        select SPARSE_IRQ
        select USE_OF
        help
@@@ -1595,7 -1594,6 +1596,7 @@@ config HAVE_ARM_ARCH_TIME
  config HAVE_ARM_TWD
        bool
        depends on SMP
 +      select CLKSRC_OF if OF
        help
          This options enables support for the ARM timer and watchdog unit
  

diff --combined arch/arm/boot/dts/tegra20.dtsi
index 3d3f64d,0dad700..fc7febc
--- 1/arch/arm/boot/dts/tegra20.dtsi
--- 2/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@@ -145,6 -145,7 +145,7 @@@
                              0 1 0x04
                              0 41 0x04
                              0 42 0x04>;
+               clocks = <&tegra_car 5>;
        };
  
        tegra_car: clock {
@@@ -304,6 -305,7 +305,7 @@@
                compatible = "nvidia,tegra20-rtc";
                reg = <0x7000e000 0x100>;
                interrupts = <0 2 0x04>;
+               clocks = <&tegra_car 4>;
        };
  
        i2c@7000c000 {
@@@ -385,7 -387,7 +387,7 @@@
  
        spi@7000d800 {
                compatible = "nvidia,tegra20-slink";
 -              reg = <0x7000d480 0x200>;
 +              reg = <0x7000d800 0x200>;
                interrupts = <0 83 0x04>;
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
@@@ -416,6 -418,8 +418,8 @@@
        pmc {
                compatible = "nvidia,tegra20-pmc";
                reg = <0x7000e400 0x400>;
+               clocks = <&tegra_car 110>, <&clk32k_in>;
+               clock-names = "pclk", "clk32k_in";
        };
  
        memory-controller@7000f000 {

diff --combined arch/arm/boot/dts/tegra30.dtsi
index dbf46c2,9d7869f..9fe7a92
--- 1/arch/arm/boot/dts/tegra30.dtsi
--- 2/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@@ -148,6 -148,7 +148,7 @@@
                              0 42 0x04
                              0 121 0x04
                              0 122 0x04>;
+               clocks = <&tegra_car 5>;
        };
  
        tegra_car: clock {
@@@ -291,6 -292,7 +292,7 @@@
                compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                reg = <0x7000e000 0x100>;
                interrupts = <0 2 0x04>;
+               clocks = <&tegra_car 4>;
        };
  
        i2c@7000c000 {
@@@ -372,7 -374,7 +374,7 @@@
  
        spi@7000d800 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 -              reg = <0x7000d480 0x200>;
 +              reg = <0x7000d800 0x200>;
                interrupts = <0 83 0x04>;
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
@@@ -423,8 -425,10 +425,10 @@@
        };
  
        pmc {
-               compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+               compatible = "nvidia,tegra30-pmc";
                reg = <0x7000e400 0x400>;
+               clocks = <&tegra_car 218>, <&clk32k_in>;
+               clock-names = "pclk", "clk32k_in";
        };
  
        memory-controller {

diff --combined drivers/clocksource/tegra20_timer.c
index 2e4d8a6,bc4b8ad..ae877b0
--- 1/drivers/clocksource/tegra20_timer.c
--- 2/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@@ -154,12 -154,29 +154,12 @@@ static struct irqaction tegra_timer_ir
        .dev_id         = &tegra_clockevent,
  };
  
 -static const struct of_device_id timer_match[] __initconst = {
 -      { .compatible = "nvidia,tegra20-timer" },
 -      {}
 -};
 -
 -static const struct of_device_id rtc_match[] __initconst = {
 -      { .compatible = "nvidia,tegra20-rtc" },
 -      {}
 -};
 -
 -static void __init tegra20_init_timer(void)
 +static void __init tegra20_init_timer(struct device_node *np)
  {
 -      struct device_node *np;
        struct clk *clk;
        unsigned long rate;
        int ret;
  
 -      np = of_find_matching_node(NULL, timer_match);
 -      if (!np) {
 -              pr_err("Failed to find timer DT node\n");
 -              BUG();
 -      }
 -
        timer_reg_base = of_iomap(np, 0);
        if (!timer_reg_base) {
                pr_err("Can't map timer registers\n");
@@@ -172,7 -189,7 +172,7 @@@
                BUG();
        }
  
-       clk = clk_get_sys("timer", NULL);
+       clk = of_clk_get(np, 0);
        if (IS_ERR(clk)) {
                pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
                rate = 12000000;
@@@ -183,6 -200,30 +183,6 @@@
  
        of_node_put(np);
  
 -      np = of_find_matching_node(NULL, rtc_match);
 -      if (!np) {
 -              pr_err("Failed to find RTC DT node\n");
 -              BUG();
 -      }
 -
 -      rtc_base = of_iomap(np, 0);
 -      if (!rtc_base) {
 -              pr_err("Can't map RTC registers");
 -              BUG();
 -      }
 -
 -      /*
 -       * rtc registers are used by read_persistent_clock, keep the rtc clock
 -       * enabled
 -       */
 -      clk = of_clk_get(np, 0);
 -      if (IS_ERR(clk))
 -              pr_warn("Unable to get rtc-tegra clock\n");
 -      else
 -              clk_prepare_enable(clk);
 -
 -      of_node_put(np);
 -
        switch (rate) {
        case 12000000:
                timer_writel(0x000b, TIMERUS_USEC_CFG);
@@@ -218,34 -259,12 +218,34 @@@
        tegra_clockevent.irq = tegra_timer_irq.irq;
        clockevents_config_and_register(&tegra_clockevent, 1000000,
                                        0x1, 0x1fffffff);
 -#ifdef CONFIG_HAVE_ARM_TWD
 -      twd_local_timer_of_register();
 -#endif
 +}
 +CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
 +
 +static void __init tegra20_init_rtc(struct device_node *np)
 +{
 +      struct clk *clk;
 +
 +      rtc_base = of_iomap(np, 0);
 +      if (!rtc_base) {
 +              pr_err("Can't map RTC registers");
 +              BUG();
 +      }
 +
 +      /*
 +       * rtc registers are used by read_persistent_clock, keep the rtc clock
 +       * enabled
 +       */
-       clk = clk_get_sys("rtc-tegra", NULL);
++      clk = of_clk_get(np, 0);
 +      if (IS_ERR(clk))
 +              pr_warn("Unable to get rtc-tegra clock\n");
 +      else
 +              clk_prepare_enable(clk);
 +
 +      of_node_put(np);
 +
        register_persistent_clock(NULL, tegra_read_persistent_clock);
  }
 -CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer);
 +CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
  
  #ifdef CONFIG_PM
  static u32 usec_config;