drm/radeon: fix resume on some rs4xx boards (v2)

commit acf88deb8ddbb73acd1c3fa32fde51af9153227f upstream.

Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on
some boards on resume.  The systems seem to work fine
without touching this bit so leave it as is.

v2: read-modify-write the GART_INDEX_REG_EN bit.
I suspect the problem is that we are losing the other
settings in the register.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=52952

Reported-by: Ondrej Zary <linux@rainbow-software.org>
Tested-by: Daniel Tobias <dan.g.tob@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 4dd9512..c087434 100644 (file)
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -174,10 +174,13 @@ int rs400_gart_enable(struct radeon_device *rdev)
        /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
         * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
        if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
-               WREG32_MC(RS480_MC_MISC_CNTL,
-                         (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
+               tmp = RREG32_MC(RS480_MC_MISC_CNTL);
+               tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
+               WREG32_MC(RS480_MC_MISC_CNTL, tmp);
        } else {
-               WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
+               tmp = RREG32_MC(RS480_MC_MISC_CNTL);
+               tmp |= RS480_GART_INDEX_REG_EN;
+               WREG32_MC(RS480_MC_MISC_CNTL, tmp);
        }
        /* Enable gart */
        WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));