cxgb4: Fix PCI-E Memory window interface for big-endian systems

When doing reads and writes to adapter memory via the PCI-E Memory Window
interface, data gets swizzled on 4-byte boundaries on Big-Endian systems
because we need to account for the register read/write interface which
incorporates a swizzle onto the Little-Endian PCI-E Bus.

Based on original work by Casey Leedom <leedom@chelsio.com>

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --cc drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
Simple merge