xilinx: Replace PHY_VITESSE by PHY_MSCC
authorMichal Simek <michal.simek@amd.com>
Tue, 30 Sep 2025 07:09:26 +0000 (09:09 +0200)
committerMichal Simek <michal.simek@amd.com>
Thu, 9 Oct 2025 10:31:09 +0000 (12:31 +0200)
Enable MSCC phy driver instead of VITESSE. Vitesse driver is much older and
is on the way out that's why switch to MSCC driver which covers VSC8531
which is used on one Versal board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a441e488a29bd1c93677a6f63a4a04a3cc1c9f5.1759216164.git.michal.simek@amd.com
configs/amd_versal2_virt_defconfig
configs/xilinx_versal_net_virt_defconfig
configs/xilinx_versal_virt_defconfig
configs/xilinx_zynqmp_virt_defconfig

index 5791f04..72c53ef 100644 (file)
@@ -107,10 +107,10 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MSCC=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
index 13d89c4..fb031d6 100644 (file)
@@ -110,10 +110,10 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_ANEG_TIMEOUT=20000
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MSCC=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
index 52142bc..39c7bd4 100644 (file)
@@ -119,10 +119,10 @@ CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_ANEG_TIMEOUT=20000
 CONFIG_PHY_ADIN=y
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MSCC=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
index b45ac80..6bb6a8c 100644 (file)
@@ -170,10 +170,10 @@ CONFIG_PHY_ADIN=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_MSCC=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
-CONFIG_PHY_VITESSE=y
 CONFIG_PHY_XILINX=y
 CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y