[ARM] 3540/1: ixp23xx: deal with gap in interrupt bitmasks

Patch from Lennert Buytenhek

On the ixp23xx, the microengine thread interrupt sources are numbered
56..119, but their mask/status bits are located in bit positions 64..127
in the various registers in the interrupt controller (bit positions
56..63 are unused.)

We don't deal with this, so currently, when asked to enable IRQ 64, we
will enable IRQ 56 instead.

The only interrupts >= 64 are the thread interrupt sources, and there
are no in-tree users of those yet, so this is fortunately not a big
problem, but this needs fixing anyway.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 092ee12..affd1d5 100644 (file)
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -178,8 +178,12 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
 
 static void ixp23xx_irq_mask(unsigned int irq)
 {
-       volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+       volatile unsigned long *intr_reg;
 
+       if (irq >= 56)
+               irq += 8;
+
+       intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
        *intr_reg &= ~(1 << (irq % 32));
 }
 
@@ -199,17 +203,25 @@ static void ixp23xx_irq_ack(unsigned int irq)
  */
 static void ixp23xx_irq_level_unmask(unsigned int irq)
 {
-       volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+       volatile unsigned long *intr_reg;
 
        ixp23xx_irq_ack(irq);
 
+       if (irq >= 56)
+               irq += 8;
+
+       intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
        *intr_reg |= (1 << (irq % 32));
 }
 
 static void ixp23xx_irq_edge_unmask(unsigned int irq)
 {
-       volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+       volatile unsigned long *intr_reg;
+
+       if (irq >= 56)
+               irq += 8;
 
+       intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
        *intr_reg |= (1 << (irq % 32));
 }