Merge branch 'drm-intel-fixes' into drm-intel-next

diff --combined drivers/gpu/drm/i915/i915_debugfs.c
index ed62730,0a893f7..e266249
--- 1/drivers/gpu/drm/i915/i915_debugfs.c
--- 2/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@@ -865,7 -865,7 +865,7 @@@ static int i915_cur_delayinfo(struct se
                           MEMSTAT_VID_SHIFT);
                seq_printf(m, "Current P-state: %d\n",
                           (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 -      } else if (IS_GEN6(dev)) {
 +      } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
                u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
                u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
                u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@@ -1123,44 -1123,6 +1123,44 @@@ static int i915_emon_status(struct seq_
        return 0;
  }
  
 +static int i915_ring_freq_table(struct seq_file *m, void *unused)
 +{
 +      struct drm_info_node *node = (struct drm_info_node *) m->private;
 +      struct drm_device *dev = node->minor->dev;
 +      drm_i915_private_t *dev_priv = dev->dev_private;
 +      int ret;
 +      int gpu_freq, ia_freq;
 +
 +      if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
 +              seq_printf(m, "unsupported on this chipset\n");
 +              return 0;
 +      }
 +
 +      ret = mutex_lock_interruptible(&dev->struct_mutex);
 +      if (ret)
 +              return ret;
 +
 +      seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
 +
 +      for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
 +           gpu_freq++) {
 +              I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
 +              I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
 +                         GEN6_PCODE_READ_MIN_FREQ_TABLE);
 +              if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
 +                            GEN6_PCODE_READY) == 0, 10)) {
 +                      DRM_ERROR("pcode read of freq table timed out\n");
 +                      continue;
 +              }
 +              ia_freq = I915_READ(GEN6_PCODE_DATA);
 +              seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
 +      }
 +
 +      mutex_unlock(&dev->struct_mutex);
 +
 +      return 0;
 +}
 +
  static int i915_gfxec(struct seq_file *m, void *unused)
  {
        struct drm_info_node *node = (struct drm_info_node *) m->private;
@@@ -1245,13 -1207,17 +1245,17 @@@ static int i915_context_status(struct s
        if (ret)
                return ret;
  
-       seq_printf(m, "power context ");
-       describe_obj(m, dev_priv->pwrctx);
-       seq_printf(m, "\n");
+       if (dev_priv->pwrctx) {
+               seq_printf(m, "power context ");
+               describe_obj(m, dev_priv->pwrctx);
+               seq_printf(m, "\n");
+       }
  
-       seq_printf(m, "render context ");
-       describe_obj(m, dev_priv->renderctx);
-       seq_printf(m, "\n");
+       if (dev_priv->renderctx) {
+               seq_printf(m, "render context ");
+               describe_obj(m, dev_priv->renderctx);
+               seq_printf(m, "\n");
+       }
  
        mutex_unlock(&dev->mode_config.mutex);
  
@@@ -1464,7 -1430,6 +1468,7 @@@ static struct drm_info_list i915_debugf
        {"i915_inttoext_table", i915_inttoext_table, 0},
        {"i915_drpc_info", i915_drpc_info, 0},
        {"i915_emon_status", i915_emon_status, 0},
 +      {"i915_ring_freq_table", i915_ring_freq_table, 0},
        {"i915_gfxec", i915_gfxec, 0},
        {"i915_fbc_status", i915_fbc_status, 0},
        {"i915_sr_status", i915_sr_status, 0},

diff --combined drivers/gpu/drm/i915/i915_drv.h
index e0f9ca3,1c8bfb1..7a7a421
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -994,12 -994,9 +994,10 @@@ extern unsigned int i915_panel_use_ssc
  extern int i915_vbt_sdvo_panel_type;
  extern unsigned int i915_enable_rc6;
  extern unsigned int i915_enable_fbc;
 +extern bool i915_enable_hangcheck;
  
  extern int i915_suspend(struct drm_device *dev, pm_message_t state);
  extern int i915_resume(struct drm_device *dev);
- extern void i915_save_display(struct drm_device *dev);
- extern void i915_restore_display(struct drm_device *dev);
  extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  
@@@ -1194,7 -1191,7 +1192,7 @@@ void i915_gem_clflush_object(struct drm
  int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
                                            uint32_t read_domains,
                                            uint32_t write_domain);
 -int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
 +int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
  void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  void i915_gem_do_init(struct drm_device *dev,
@@@ -1213,8 -1210,7 +1211,8 @@@ int __must_chec
  i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
                                  bool write);
  int __must_check
 -i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
 +i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 +                                   u32 alignment,
                                     struct intel_ring_buffer *pipelined);
  int i915_gem_attach_phys_object(struct drm_device *dev,
                                struct drm_i915_gem_object *obj,
@@@ -1228,14 -1224,9 +1226,14 @@@ void i915_gem_release(struct drm_devic
  uint32_t
  i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
  
 +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 +                                  enum i915_cache_level cache_level);
 +
  /* i915_gem_gtt.c */
  void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
 +void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
 +                              enum i915_cache_level cache_level);
  void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  
  /* i915_gem_evict.c */

diff --combined drivers/gpu/drm/i915/i915_suspend.c
index 6fbd997,5257cfc..8cd1c8b
--- 1/drivers/gpu/drm/i915/i915_suspend.c
--- 2/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@@ -597,7 -597,7 +597,7 @@@ static void i915_restore_modeset_reg(st
        return;
  }
  
- void i915_save_display(struct drm_device *dev)
+ static void i915_save_display(struct drm_device *dev)
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
  
@@@ -678,7 -678,6 +678,6 @@@
        }
  
        /* VGA state */
-       mutex_lock(&dev->struct_mutex);
        dev_priv->saveVGA0 = I915_READ(VGA0);
        dev_priv->saveVGA1 = I915_READ(VGA1);
        dev_priv->saveVGA_PD = I915_READ(VGA_PD);
@@@ -688,10 -687,9 +687,9 @@@
                dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
  
        i915_save_vga(dev);
-       mutex_unlock(&dev->struct_mutex);
  }
  
- void i915_restore_display(struct drm_device *dev)
+ static void i915_restore_display(struct drm_device *dev)
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
  
@@@ -783,7 -781,6 +781,6 @@@
        else
                I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
  
-       mutex_lock(&dev->struct_mutex);
        I915_WRITE(VGA0, dev_priv->saveVGA0);
        I915_WRITE(VGA1, dev_priv->saveVGA1);
        I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@@ -791,7 -788,6 +788,6 @@@
        udelay(150);
  
        i915_restore_vga(dev);
-       mutex_unlock(&dev->struct_mutex);
  }
  
  int i915_save_state(struct drm_device *dev)
@@@ -801,6 -797,8 +797,8 @@@
  
        pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
  
+       mutex_lock(&dev->struct_mutex);
+ 
        /* Hardware status page */
        dev_priv->saveHWS = I915_READ(HWS_PGA);
  
@@@ -840,6 -838,8 +838,8 @@@
        for (i = 0; i < 3; i++)
                dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
  
+       mutex_unlock(&dev->struct_mutex);
+ 
        return 0;
  }
  
@@@ -850,6 -850,8 +850,8 @@@ int i915_restore_state(struct drm_devic
  
        pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
  
+       mutex_lock(&dev->struct_mutex);
+ 
        /* Hardware status page */
        I915_WRITE(HWS_PGA, dev_priv->saveHWS);
  
@@@ -867,6 -869,7 +869,7 @@@
                I915_WRITE(IER, dev_priv->saveIER);
                I915_WRITE(IMR, dev_priv->saveIMR);
        }
+       mutex_unlock(&dev->struct_mutex);
  
        intel_init_clock_gating(dev);
  
@@@ -875,11 -878,11 +878,13 @@@
                intel_init_emon(dev);
        }
  
 -      if (IS_GEN6(dev))
 +      if (IS_GEN6(dev)) {
                gen6_enable_rps(dev_priv);
 +              gen6_update_ring_freq(dev_priv);
 +      }
  
+       mutex_lock(&dev->struct_mutex);
+ 
        /* Cache mode state */
        I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
  
@@@ -893,6 -896,8 +898,8 @@@
        for (i = 0; i < 3; i++)
                I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
  
+       mutex_unlock(&dev->struct_mutex);
+ 
        intel_i2c_reset(dev);
  
        return 0;