configs: qemu-sbsa: Define GIC register base address

If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at
arch/arm/cpu/armv8/start.S.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h
index aff7816..669d0fe 100644 (file)
--- a/include/configs/qemu-sbsa.h
+++ b/include/configs/qemu-sbsa.h
@@ -86,4 +86,8 @@
 #define CFG_SYS_INIT_RAM_ADDR          SBSA_MEM_BASE_ADDR
 #define CFG_SYS_INIT_RAM_SIZE          0x1000000
 
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE                      SBSA_GIC_DIST_BASE_ADDR
+#define GICR_BASE                      SBSA_GIC_REDIST_BASE_ADDR
+
 #endif /* __CONFIG_H */