#include <asm/div64.h>
#include <mach/hardware.h>
+
+/*
+ * The EP93xx has two external crystal oscillators. To generate the
+ * required high-frequency clocks, the processor uses two phase-locked-
+ * loops (PLLs) to multiply the incoming external clock signal to much
+ * higher frequencies that are then divided down by programmable dividers
+ * to produce the needed clocks. The PLLs operate independently of one
+ * another.
+ */
+#define EP93XX_EXT_CLK_RATE 14745600
+#define EP93XX_EXT_RTC_RATE 32768
+
+
struct clk {
unsigned long rate;
int users;
+ int sw_locked;
u32 enable_reg;
u32 enable_mask;
+
+ unsigned long (*get_rate)(struct clk *clk);
};
-static struct clk clk_uart = {
- .rate = 14745600,
+
+static unsigned long get_uart_rate(struct clk *clk);
+
+
+static struct clk clk_uart1 = {
+ .sw_locked = 1,
+ .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG,
+ .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U1EN,
+ .get_rate = get_uart_rate,
+};
+static struct clk clk_uart2 = {
+ .sw_locked = 1,
+ .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG,
+ .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U2EN,
+ .get_rate = get_uart_rate,
+};
+static struct clk clk_uart3 = {
+ .sw_locked = 1,
+ .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG,
+ .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U3EN,
+ .get_rate = get_uart_rate,
};
static struct clk clk_pll1;
static struct clk clk_f;
{ .dev_id = dev, .con_id = con, .clk = ck }
static struct clk_lookup clocks[] = {
- INIT_CK("apb:uart1", NULL, &clk_uart),
- INIT_CK("apb:uart2", NULL, &clk_uart),
- INIT_CK("apb:uart3", NULL, &clk_uart),
+ INIT_CK("apb:uart1", NULL, &clk_uart1),
+ INIT_CK("apb:uart2", NULL, &clk_uart2),
+ INIT_CK("apb:uart3", NULL, &clk_uart3),
INIT_CK(NULL, "pll1", &clk_pll1),
INIT_CK(NULL, "fclk", &clk_f),
INIT_CK(NULL, "hclk", &clk_h),
u32 value;
value = __raw_readl(clk->enable_reg);
+ if (clk->sw_locked)
+ __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
__raw_writel(value | clk->enable_mask, clk->enable_reg);
}
u32 value;
value = __raw_readl(clk->enable_reg);
+ if (clk->sw_locked)
+ __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
}
}
EXPORT_SYMBOL(clk_disable);
+static unsigned long get_uart_rate(struct clk *clk)
+{
+ u32 value;
+
+ value = __raw_readl(EP93XX_SYSCON_CLOCK_CONTROL);
+ if (value & EP93XX_SYSCON_CLOCK_UARTBAUD)
+ return EP93XX_EXT_CLK_RATE;
+ else
+ return EP93XX_EXT_CLK_RATE / 2;
+}
+
unsigned long clk_get_rate(struct clk *clk)
{
+ if (clk->get_rate)
+ return clk->get_rate(clk);
+
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
unsigned long long rate;
int i;
- rate = 14745600;
+ rate = EP93XX_EXT_CLK_RATE;
rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
if (!(value & 0x00800000)) { /* PLL1 bypassed? */
- clk_pll1.rate = 14745600;
+ clk_pll1.rate = EP93XX_EXT_CLK_RATE;
} else {
clk_pll1.rate = calc_pll_rate(value);
}
value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
if (!(value & 0x00080000)) { /* PLL2 bypassed? */
- clk_pll2.rate = 14745600;
+ clk_pll2.rate = EP93XX_EXT_CLK_RATE;
} else if (value & 0x00040000) { /* PLL2 enabled? */
clk_pll2.rate = calc_pll_rate(value);
} else {
#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000
+#define EP93XX_SYSCON_DEVICE_CONFIG_U3EN (1<<24)
+#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE (1<<23)
+#define EP93XX_SYSCON_DEVICE_CONFIG_U2EN (1<<20)
+#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000)
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
- CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X),
- CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X),
- CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X),
- CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X),
+ CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X),
+ CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
+ CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
+ CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
- CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
+ CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
- CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
+ CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
CLK("omap_rng", "ick", &rng_ick, CK_343X),
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
- CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
- CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
- CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
- CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
- CLK(NULL, "dss_ick", &dss_ick, CK_343X),
+ CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
+ CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
+ CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
+ CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
+ CLK("omapfb", "ick", &dss_ick, CK_343X),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
static struct clk gpio1_dbck = {
.name = "gpio1_dbck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_dflt,
.parent = &wkup_32k_fck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
static struct clk gpio6_dbck = {
.name = "gpio6_dbck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_dflt,
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
static struct clk gpio5_dbck = {
.name = "gpio5_dbck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_dflt,
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
static struct clk gpio4_dbck = {
.name = "gpio4_dbck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_dflt,
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
static struct clk gpio3_dbck = {
.name = "gpio3_dbck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_dflt,
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
static struct clk gpio2_dbck = {
.name = "gpio2_dbck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_dflt,
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
platform_device_register(&omap2_mcspi1);
platform_device_register(&omap2_mcspi2);
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
- platform_device_register(&omap2_mcspi3);
+ if (cpu_is_omap2430() || cpu_is_omap343x())
+ platform_device_register(&omap2_mcspi3);
#endif
#ifdef CONFIG_ARCH_OMAP3
- platform_device_register(&omap2_mcspi4);
+ if (cpu_is_omap343x())
+ platform_device_register(&omap2_mcspi4);
#endif
}
/* PM_PREPWSTST_CAM specific bits */
/* PM_PWSTCTRL_USBHOST specific bits */
-#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
/* RM_RSTST_PER specific bits */
unsigned sysclk_ps;
int status;
- if (!refclk_psec || sysclk_ps == 0)
+ if (!refclk_psec || fclk_ps == 0)
return -ENODEV;
sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <mach/i2c.h>
+#include <mach/regs-uart.h>
#include <mach/viper.h>
#include <asm/setup.h>
s3c_device_nand.dev.platform_data = &bast_nand_info;
- s3c_i2c0_set_platdata(&bast_i2c_info);
-
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
sysdev_class_register(&bast_pm_sysclass);
sysdev_register(&bast_pm_sysdev);
+ s3c_i2c0_set_platdata(&bast_i2c_info);
s3c24xx_fb_set_platdata(&bast_fb_info);
platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
extern unsigned int DoubleCPDO(struct roundingData *roundData,
const unsigned int opcode, FPREG * rFd);
+/* extneded_cpdo.c */
+extern unsigned int ExtendedCPDO(struct roundingData *roundData,
+ const unsigned int opcode, FPREG * rFd);
+
#endif
#include "fpmodule.inl"
#include "softfloat.h"
-#ifdef CONFIG_FPE_NWFPE_XP
-extern flag floatx80_is_nan(floatx80);
-#endif
-
unsigned int PerformFLT(const unsigned int opcode);
unsigned int PerformFIX(const unsigned int opcode);
char floatx80_lt_quiet( floatx80, floatx80 );
char floatx80_is_signaling_nan( floatx80 );
+extern flag floatx80_is_nan(floatx80);
+
#endif
static inline flag extractFloat32Sign(float32 a)
config_invalid = 1;
return;
}
- if (rg.paddr)
+ if (rg.paddr) {
reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT);
- reserved += rg.size;
+ reserved += rg.size;
+ }
omapfb_config.mem_desc.region[i] = rg;
configured_regions++;
}
return 0;
if (cpu_is_omap24xx() && gpio < 128)
return 0;
- if (cpu_is_omap34xx() && gpio < 160)
+ if (cpu_is_omap34xx() && gpio < 192)
return 0;
return -1;
}
int s3c24xx_register_clock(struct clk *clk)
{
- clk->owner = THIS_MODULE;
-
if (clk->enable == NULL)
clk->enable = clk_null_enable;
EXPORT_SYMBOL(s3c2410_dma_getposition);
-static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
+static inline struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
{
return container_of(dev, struct s3c2410_dma_chan, dev);
}
#if 1
#define gpio_dbg(x...) do { } while(0)
#else
-#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
+#define gpio_dbg(x...) printk(KERN_DEBUG x)
#endif
/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
-#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
-#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
-#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
-#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
-#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
-
-#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
-#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
-#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
-#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
+#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
+#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
+#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
+#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
+#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
+#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
+#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
+#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
+#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
+#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)
static int get_dss_clocks(void)
{
- if (IS_ERR((dispc.dss_ick = clk_get(dispc.fbdev->dev, "dss_ick")))) {
- dev_err(dispc.fbdev->dev, "can't get dss_ick\n");
+ dispc.dss_ick = clk_get(dispc.fbdev->dev, "ick");
+ if (IS_ERR(dispc.dss_ick)) {
+ dev_err(dispc.fbdev->dev, "can't get ick\n");
return PTR_ERR(dispc.dss_ick);
}
- if (IS_ERR((dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck")))) {
+ dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck");
+ if (IS_ERR(dispc.dss1_fck)) {
dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
clk_put(dispc.dss_ick);
return PTR_ERR(dispc.dss1_fck);
}
- if (IS_ERR((dispc.dss_54m_fck =
- clk_get(dispc.fbdev->dev, "dss_54m_fck")))) {
- dev_err(dispc.fbdev->dev, "can't get dss_54m_fck\n");
+ dispc.dss_54m_fck = clk_get(dispc.fbdev->dev, "tv_fck");
+ if (IS_ERR(dispc.dss_54m_fck)) {
+ dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
clk_put(dispc.dss_ick);
clk_put(dispc.dss1_fck);
return PTR_ERR(dispc.dss_54m_fck);
static int rfbi_get_clocks(void)
{
- if (IS_ERR((rfbi.dss_ick = clk_get(rfbi.fbdev->dev, "dss_ick")))) {
- dev_err(rfbi.fbdev->dev, "can't get dss_ick\n");
+ rfbi.dss_ick = clk_get(rfbi.fbdev->dev, "ick");
+ if (IS_ERR(rfbi.dss_ick)) {
+ dev_err(rfbi.fbdev->dev, "can't get ick\n");
return PTR_ERR(rfbi.dss_ick);
}
- if (IS_ERR((rfbi.dss1_fck = clk_get(rfbi.fbdev->dev, "dss1_fck")))) {
+ rfbi.dss1_fck = clk_get(rfbi.fbdev->dev, "dss1_fck");
+ if (IS_ERR(rfbi.dss1_fck)) {
dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
clk_put(rfbi.dss_ick);
return PTR_ERR(rfbi.dss1_fck);
git.openpandora.org / pandora-kernel.git / commitdiff