--- /dev/null
+diff -uNr u-boot-1.1.2/.pc/.version u-boot-emetec-1.1.2/.pc/.version\r
+--- u-boot-1.1.2/.pc/.version 2007-04-20 00:01:06.000000000 +0300\r
++++ u-boot-emetec-1.1.2/.pc/.version 1970-01-01 02:00:00.000000000 +0200\r
+@@ -1 +0,0 @@\r
+-2\r
+diff -uNr u-boot-1.1.2/.pc/applied-patches u-boot-emetec-1.1.2/.pc/applied-patches\r
+--- u-boot-1.1.2/.pc/applied-patches 2007-04-20 00:01:06.000000000 +0300\r
++++ u-boot-emetec-1.1.2/.pc/applied-patches 1970-01-01 02:00:00.000000000 +0200\r
+@@ -1 +0,0 @@\r
+-arm_flags.patch\r
+diff -uNr u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk u-boot-emetec-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk\r
+--- u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 2003-05-23 15:36:21.000000000 +0300\r
++++ u-boot-emetec-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 1970-01-01 02:00:00.000000000 +0200\r
+@@ -1,28 +0,0 @@\r
+-#\r
+-# (C) Copyright 2002\r
+-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>\r
+-# Marius Groeger <mgroeger@sysgo.de>\r
+-#\r
+-# See file CREDITS for list of people who contributed to this\r
+-# project.\r
+-#\r
+-# This program is free software; you can redistribute it and/or\r
+-# modify it under the terms of the GNU General Public License as\r
+-# published by the Free Software Foundation; either version 2 of\r
+-# the License, or (at your option) any later version.\r
+-#\r
+-# This program is distributed in the hope that it will be useful,\r
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+-# GNU General Public License for more details.\r
+-#\r
+-# You should have received a copy of the GNU General Public License\r
+-# along with this program; if not, write to the Free Software\r
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
+-# MA 02111-1307 USA\r
+-#\r
+-\r
+-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \\r
+- -mshort-load-bytes -msoft-float\r
+-\r
+-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100\r
+diff -uNr u-boot-1.1.2/MAKEALL u-boot-emetec-1.1.2/MAKEALL\r
+--- u-boot-1.1.2/MAKEALL 2004-12-31 11:32:48.000000000 +0200\r
++++ u-boot-emetec-1.1.2/MAKEALL 2005-03-11 22:23:47.000000000 +0200\r
+@@ -69,7 +69,7 @@\r
+ ml300 OCOTEA OCRTC ORSG \\r
+ PCI405 PIP405 PLU405 PMC405 \\r
+ PPChameleonEVB VOH405 W7OLMC W7OLMG \\r
+- WALNUT405 WUH405 XPEDITE1K \\r
++ WALNUT405 WUH405 XPEDITE1K EMETEC405 \\r
+ "\r
+ \r
+ #########################################################################\r
+diff -uNr u-boot-1.1.2/Makefile u-boot-emetec-1.1.2/Makefile\r
+--- u-boot-1.1.2/Makefile 2004-12-19 11:58:11.000000000 +0200\r
++++ u-boot-emetec-1.1.2/Makefile 2005-03-14 22:43:56.000000000 +0200\r
+@@ -54,7 +54,7 @@\r
+ CROSS_COMPILE =\r
+ else\r
+ ifeq ($(ARCH),ppc)\r
+-CROSS_COMPILE = ppc_8xx-\r
++CROSS_COMPILE = ppc_4xx-\r
+ endif\r
+ ifeq ($(ARCH),arm)\r
+ CROSS_COMPILE = arm-linux-\r
+@@ -127,7 +127,6 @@\r
+ # The "tools" are needed early, so put this first\r
+ # Don't include stuff already done in $(LIBS)\r
+ SUBDIRS = tools \\r
+- examples \\r
+ post \\r
+ post/cpu\r
+ .PHONY : $(SUBDIRS)\r
+@@ -838,6 +837,9 @@\r
+ \r
+ VOM405_config: unconfig\r
+ @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd\r
++ \r
++EMETEC405_config: unconfig\r
++ @./mkconfig $(@:_config=) ppc ppc4xx emetec405\r
+ \r
+ W7OLMC_config \\r
+ W7OLMG_config: unconfig\r
+diff -uNr u-boot-1.1.2/board/emetec405/Makefile u-boot-emetec-1.1.2/board/emetec405/Makefile\r
+--- u-boot-1.1.2/board/emetec405/Makefile 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/board/emetec405/Makefile 2005-04-26 22:34:53.000000000 +0300\r
+@@ -0,0 +1,46 @@\r
++#\r
++# (C) Copyright 2000\r
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.\r
++#\r
++# See file CREDITS for list of people who contributed to this\r
++# project.\r
++#\r
++# This program is free software; you can redistribute it and/or\r
++# modify it under the terms of the GNU General Public License as\r
++# published by the Free Software Foundation; either version 2 of\r
++# the License, or (at your option) any later version.\r
++#\r
++# This program is distributed in the hope that it will be useful,\r
++# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++# GNU General Public License for more details.\r
++#\r
++# You should have received a copy of the GNU General Public License\r
++# along with this program; if not, write to the Free Software\r
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++# MA 02111-1307 USA\r
++#\r
++\r
++include $(TOPDIR)/config.mk\r
++\r
++LIB = lib$(BOARD).a\r
++\r
++OBJS = $(BOARD).o flash.o\r
++\r
++$(LIB): $(OBJS) $(SOBJS)\r
++ $(AR) crv $@ $(OBJS)\r
++\r
++clean:\r
++ rm -f $(SOBJS) $(OBJS)\r
++\r
++distclean: clean\r
++ rm -f $(LIB) core *.bak .depend\r
++\r
++#########################################################################\r
++\r
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)\r
++ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@\r
++\r
++sinclude .depend\r
++\r
++#########################################################################\r
+diff -uNr u-boot-1.1.2/board/emetec405/config.mk u-boot-emetec-1.1.2/board/emetec405/config.mk\r
+--- u-boot-1.1.2/board/emetec405/config.mk 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/board/emetec405/config.mk 2005-03-11 22:26:43.000000000 +0200\r
+@@ -0,0 +1,28 @@\r
++#\r
++# (C) Copyright 2000\r
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.\r
++#\r
++# See file CREDITS for list of people who contributed to this\r
++# project.\r
++#\r
++# This program is free software; you can redistribute it and/or\r
++# modify it under the terms of the GNU General Public License as\r
++# published by the Free Software Foundation; either version 2 of\r
++# the License, or (at your option) any later version.\r
++#\r
++# This program is distributed in the hope that it will be useful,\r
++# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++# GNU General Public License for more details.\r
++#\r
++# You should have received a copy of the GNU General Public License\r
++# along with this program; if not, write to the Free Software\r
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++# MA 02111-1307 USA\r
++#\r
++\r
++#\r
++# emetec EMETEC405 boards\r
++#\r
++\r
++TEXT_BASE = 0xFFFC0000\r
+diff -uNr u-boot-1.1.2/board/emetec405/emetec405.c u-boot-emetec-1.1.2/board/emetec405/emetec405.c\r
+--- u-boot-1.1.2/board/emetec405/emetec405.c 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/board/emetec405/emetec405.c 2005-04-26 23:02:01.000000000 +0300\r
+@@ -0,0 +1,106 @@\r
++/*\r
++ * (C) Copyright 2001-2003\r
++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation; either version 2 of\r
++ * the License, or (at your option) any later version.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++\r
++#include <common.h>\r
++#include <asm/processor.h>\r
++#include <command.h>\r
++#include <malloc.h>\r
++\r
++\r
++int board_early_init_f (void)\r
++{\r
++ /*-------------------------------------------------------------------------+\r
++ | Interrupt controller setup for the Walnut board.\r
++ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive\r
++ | IRQ 16 405GP internally generated; active low; level sensitive\r
++ | IRQ 17-24 RESERVED\r
++ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive\r
++ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive\r
++ | IRQ 27 (EXT IRQ 2) Not Used\r
++ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive\r
++ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive\r
++ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive\r
++ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive\r
++ | Note for Walnut board:\r
++ | An interrupt taken for the FPGA (IRQ 25) indicates that either\r
++ | the Mouse, Keyboard, IRDA, or External Expansion caused the\r
++ | interrupt. The FPGA must be read to determine which device\r
++ | caused the interrupt. The default setting of the FPGA clears\r
++ |\r
++ +-------------------------------------------------------------------------*/\r
++\r
++ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */\r
++ mtdcr (uicer, 0x00000000); /* disable all ints */\r
++ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */\r
++ mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */\r
++ mtdcr (uictr, 0x10000000); /* set int trigger levels */\r
++ mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */\r
++ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */\r
++\r
++ return 0;\r
++}\r
++\r
++\r
++int misc_init_f (void)\r
++{\r
++ return 0; /* dummy implementation */\r
++}\r
++\r
++\r
++int misc_init_r (void)\r
++{\r
++ return 0; /* dummy implementation */\r
++}\r
++\r
++\r
++/*\r
++ * Check Board Identity:\r
++ */\r
++int checkboard (void)\r
++{\r
++ unsigned char str[64];\r
++\r
++ puts ("Board: MAGICBOX\n");\r
++\r
++ return 0;\r
++}\r
++\r
++\r
++long int initdram (int board_type)\r
++{\r
++ unsigned long val;\r
++\r
++ mtdcr(memcfga, mem_mb0cf);\r
++ val = mfdcr(memcfgd);\r
++ \r
++ return (4*1024*1024 << ((val & 0x000e0000) >> 17));\r
++}\r
++\r
++\r
++int testdram (void)\r
++{\r
++ printf ("test: 32 MB - ok\n");\r
++\r
++ return (0);\r
++}\r
++\r
+diff -uNr u-boot-1.1.2/board/emetec405/flash.c u-boot-emetec-1.1.2/board/emetec405/flash.c\r
+--- u-boot-1.1.2/board/emetec405/flash.c 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/board/emetec405/flash.c 2005-05-25 10:14:13.000000000 +0300\r
+@@ -0,0 +1,544 @@\r
++/*\r
++ * (C) Copyright 2000\r
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation; either version 2 of\r
++ * the License, or (at your option) any later version.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++#include <common.h>\r
++#include <ppc4xx.h>\r
++#include <asm/processor.h>\r
++\r
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Functions\r
++ */\r
++static ulong flash_get_size (vu_long * addr, flash_info_t * info);\r
++static void flash_get_offsets (ulong base, flash_info_t * info);\r
++\r
++/*-----------------------------------------------------------------------\r
++ */\r
++unsigned long flash_init (void)\r
++{\r
++ unsigned long size_b0;\r
++ int i;\r
++ uint pbcr;\r
++ unsigned long base_b0;\r
++ int size_val = 0;\r
++\r
++ /* Init: no FLASHes known */\r
++ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {\r
++ flash_info[i].flash_id = FLASH_UNKNOWN;\r
++ }\r
++\r
++ /* Static FLASH Bank configuration here - FIXME XXX */\r
++\r
++ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);\r
++\r
++ if (flash_info[0].flash_id == FLASH_UNKNOWN) {\r
++ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",\r
++ size_b0, size_b0<<20);\r
++ }\r
++\r
++ /* Setup offsets */\r
++ flash_get_offsets (-size_b0, &flash_info[0]);\r
++\r
++ /* Re-do sizing to get full correct info */\r
++ mtdcr(ebccfga, pb0cr);\r
++ pbcr = mfdcr(ebccfgd);\r
++ mtdcr(ebccfga, pb0cr);\r
++ base_b0 = -size_b0;\r
++ switch (size_b0) {\r
++ case 1 << 20:\r
++ size_val = 0;\r
++ break;\r
++ case 2 << 20:\r
++ size_val = 1;\r
++ break;\r
++ case 4 << 20:\r
++ size_val = 2;\r
++ break;\r
++ case 8 << 20:\r
++ size_val = 3;\r
++ break;\r
++ case 16 << 20:\r
++ size_val = 4;\r
++ break;\r
++ }\r
++ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);\r
++ mtdcr(ebccfgd, pbcr);\r
++\r
++ /* Monitor protection ON by default */\r
++ (void)flash_protect(FLAG_PROTECT_SET,\r
++ -CFG_MONITOR_LEN,\r
++ 0xffffffff,\r
++ &flash_info[0]);\r
++\r
++ flash_info[0].size = size_b0;\r
++\r
++ return (size_b0);\r
++}\r
++\r
++/*-----------------------------------------------------------------------\r
++ */\r
++static void flash_get_offsets (ulong base, flash_info_t *info)\r
++{\r
++ int i;\r
++ short n;\r
++ \r
++ base += info->size;\r
++ i = info->sector_count;\r
++ \r
++ switch (info->flash_id & FLASH_TYPEMASK) \r
++ { \r
++ case FLASH_STMW320DT :\r
++ /* 1 x 16k boot sector */\r
++ base -= 16 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ /* 2 x 8k boot sectors */\r
++ for (n=0; n<2; ++n) {\r
++ base -= 8 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ }\r
++ /* 1 x 32k boot sector */\r
++ base -= 32 << 10;\r
++ --i;\r
++ info->start[i] = base; \r
++ break;\r
++ \r
++ case FLASH_STMW640DT :\r
++ /* 8 x 8k boot sectors */\r
++ for (n=0; n<8; ++n) {\r
++ base -= 8 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ }\r
++ break;\r
++ };\r
++ /* 64k regular sectors */\r
++ while (i > 0) {\r
++ base -= 64 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ }\r
++}\r
++\r
++/*-----------------------------------------------------------------------\r
++ */\r
++static ulong flash_get_size (vu_long *addr, flash_info_t *info)\r
++{\r
++ short i;\r
++ short n;\r
++ CFG_FLASH_WORD_SIZE value;\r
++ ulong base = (ulong)addr;\r
++ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;\r
++\r
++ /* Write auto select command: read Manufacturer ID */\r
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;\r
++ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;\r
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;\r
++\r
++ value = addr2[CFG_FLASH_READ0];\r
++\r
++ switch (value) {\r
++ case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:\r
++ info->flash_id = FLASH_MAN_SST;\r
++ break;\r
++ case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:\r
++ info->flash_id = FLASH_MAN_STM;\r
++ break;\r
++ default:\r
++ info->flash_id = FLASH_UNKNOWN;\r
++ info->sector_count = 0;\r
++ info->size = 0;\r
++ return (0);\r
++ }\r
++\r
++ value = addr2[CFG_FLASH_READ1]; /* device ID */\r
++\r
++ switch (value) {\r
++ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:\r
++ info->flash_id += FLASH_STMW320DT;\r
++ info->sector_count = 67;\r
++ info->size = 0x00400000; \r
++ \r
++ /* set up sector start address table for FLASH_STMW320DT */\r
++ /* set sector offsets for top boot block type */\r
++ base += info->size;\r
++ i = info->sector_count;\r
++ /* 1 x 16k boot sector */\r
++ base -= 16 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ /* 2 x 8k boot sectors */\r
++ for (n=0; n<2; ++n) {\r
++ base -= 8 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ };\r
++ /* 1 x 32k boot sector */\r
++ base -= 32 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ \r
++ /* 64k regular sectors */\r
++ while (i > 0) \r
++ { \r
++ base -= 64 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ };\r
++ break; /* => 4 MB */\r
++ \r
++ case (CFG_FLASH_WORD_SIZE)STM_ID_29W640DT:\r
++ info->flash_id += FLASH_STMW640DT;\r
++ info->sector_count = 135;\r
++ info->size = 0x00800000; \r
++ \r
++ /* set up sector start address table for FLASH_STMW640DT */\r
++ /* set sector offsets for top boot block type */\r
++ base += info->size;\r
++ i = info->sector_count;\r
++ /* 8 x 8k boot sectors */\r
++ for (n=0; n<8; ++n) {\r
++ base -= 8 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ };\r
++ \r
++ /* 64k regular sectors */\r
++ while (i > 0) \r
++ { \r
++ base -= 64 << 10;\r
++ --i;\r
++ info->start[i] = base;\r
++ };\r
++ \r
++ break; /* => 8 MB */\r
++ default:\r
++ info->flash_id = FLASH_UNKNOWN;\r
++ return (0); /* => no or unknown flash */\r
++ }\r
++\r
++ /* check for protected sectors */\r
++ for (i = 0; i < info->sector_count; i++) {\r
++ /* read sector protection at sector address, (A7 .. A0) = 0x02 */\r
++ /* D0 = 1 if protected */\r
++ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);\r
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)\r
++ info->protect[i] = 0;\r
++ else\r
++ info->protect[i] = addr2[CFG_FLASH_READ2] & 1;\r
++ }\r
++\r
++ /*\r
++ * Prevent writes to uninitialized FLASH.\r
++ */\r
++ if (info->flash_id != FLASH_UNKNOWN) {\r
++ addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];\r
++ *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */\r
++ }\r
++\r
++ return (info->size);\r
++}\r
++\r
++/*-----------------------------------------------------------------------\r
++ */\r
++void flash_print_info (flash_info_t *info)\r
++{\r
++ int i;\r
++ int k;\r
++ int size;\r
++ int erased;\r
++ volatile unsigned long *flash;\r
++\r
++ switch (info->flash_id & FLASH_TYPEMASK)\r
++ {\r
++ case FLASH_STMW320DT :\r
++ printf ("ST M29W320DT (32 M, top sector)\n");\r
++ break;\r
++ case FLASH_STMW640DT :\r
++ printf ("ST M29W640DT (64 M, top sector)\n");\r
++ break;\r
++ default :\r
++ printf ("Missing or unknown FLASH type\n");\r
++ return;\r
++ };\r
++ printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);\r
++ \r
++ printf (" Sector Start Addresses:");\r
++ for (i=0; i<info->sector_count; ++i) {\r
++ /*\r
++ * Check if whole sector is erased\r
++ */\r
++ if (i != (info->sector_count-1))\r
++ size = info->start[i+1] - info->start[i];\r
++ else\r
++ size = info->start[0] + info->size - info->start[i];\r
++ erased = 1;\r
++ flash = (volatile unsigned long *)info->start[i];\r
++ size = size >> 2; /* divide by 4 for longword access */\r
++ for (k=0; k<size; k++)\r
++ {\r
++ if (*flash++ != 0xffffffff)\r
++ {\r
++ erased = 0;\r
++ break;\r
++ }\r
++ }\r
++\r
++ if ((i % 5) == 0)\r
++ printf ("\n ");\r
++ printf (" %08lX%s%s",\r
++ info->start[i],\r
++ erased ? " E" : " ",\r
++ info->protect[i] ? "RO " : " "\r
++ );\r
++ }\r
++ printf ("\n");\r
++ return;\r
++}\r
++\r
++/*-----------------------------------------------------------------------\r
++ */\r
++\r
++int flash_erase (flash_info_t *info, int s_first, int s_last)\r
++{\r
++ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);\r
++ volatile CFG_FLASH_WORD_SIZE *addr2;\r
++ int flag, prot, sect, l_sect;\r
++ ulong start, now, last;\r
++ int i;\r
++\r
++ if ((s_first < 0) || (s_first > s_last)) {\r
++ if (info->flash_id == FLASH_UNKNOWN) {\r
++ printf ("- missing\n");\r
++ } else {\r
++ printf ("- no sectors to erase\n");\r
++ }\r
++ return 1;\r
++ }\r
++\r
++ if (info->flash_id == FLASH_UNKNOWN) {\r
++ printf ("Can't erase unknown flash type - aborted\n");\r
++ return 1;\r
++ }\r
++\r
++ prot = 0;\r
++ for (sect=s_first; sect<=s_last; ++sect) {\r
++ if (info->protect[sect]) {\r
++ prot++;\r
++ }\r
++ }\r
++\r
++ if (prot) {\r
++ printf ("- Warning: %d protected sectors will not be erased!\n",\r
++ prot);\r
++ } else {\r
++ printf ("\n");\r
++ }\r
++\r
++ l_sect = -1;\r
++\r
++ /* Disable interrupts which might cause a timeout here */\r
++ flag = disable_interrupts();\r
++\r
++ /* Start erase on unprotected sectors */\r
++ for (sect = s_first; sect<=s_last; sect++) {\r
++ if (info->protect[sect] == 0) { /* not protected */\r
++ addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);\r
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {\r
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;\r
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;\r
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;\r
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;\r
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;\r
++ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */\r
++ for (i=0; i<50; i++)\r
++ udelay(1000); /* wait 1 ms */\r
++ } else {\r
++ if (sect == s_first) {\r
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;\r
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;\r
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;\r
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;\r
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;\r
++ }\r
++ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */\r
++ }\r
++ l_sect = sect;\r
++ }\r
++ }\r
++\r
++ /* re-enable interrupts if necessary */\r
++ if (flag)\r
++ enable_interrupts();\r
++\r
++ /* wait at least 80us - let's wait 1 ms */\r
++ udelay (1000);\r
++\r
++ /*\r
++ * We wait for the last triggered sector\r
++ */\r
++ if (l_sect < 0)\r
++ goto DONE;\r
++\r
++ start = get_timer (0);\r
++ last = start;\r
++ addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);\r
++ while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {\r
++ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {\r
++ printf ("Timeout\n");\r
++ return 1;\r
++ }\r
++ /* show that we're waiting */\r
++ if ((now - last) > 1000) { /* every second */\r
++ putc ('.');\r
++ last = now;\r
++ }\r
++ }\r
++\r
++DONE:\r
++ /* reset to read mode */\r
++ addr = (CFG_FLASH_WORD_SIZE *)info->start[0];\r
++ addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */\r
++\r
++ printf (" done\n");\r
++ return 0;\r
++}\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Copy memory to flash, returns:\r
++ * 0 - OK\r
++ * 1 - write timeout\r
++ * 2 - Flash not erased\r
++ */\r
++\r
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)\r
++{\r
++ ulong cp, wp, data;\r
++ int i, l, rc;\r
++\r
++ wp = (addr & ~3); /* get lower word aligned address */\r
++\r
++ /*\r
++ * handle unaligned start bytes\r
++ */\r
++ if ((l = addr - wp) != 0) {\r
++ data = 0;\r
++ for (i=0, cp=wp; i<l; ++i, ++cp) {\r
++ data = (data << 8) | (*(uchar *)cp);\r
++ }\r
++ for (; i<4 && cnt>0; ++i) {\r
++ data = (data << 8) | *src++;\r
++ --cnt;\r
++ ++cp;\r
++ }\r
++ for (; cnt==0 && i<4; ++i, ++cp) {\r
++ data = (data << 8) | (*(uchar *)cp);\r
++ }\r
++\r
++ if ((rc = write_word(info, wp, data)) != 0) {\r
++ return (rc);\r
++ }\r
++ wp += 4;\r
++ }\r
++\r
++ /*\r
++ * handle word aligned part\r
++ */\r
++ while (cnt >= 4) {\r
++ data = 0;\r
++ for (i=0; i<4; ++i) {\r
++ data = (data << 8) | *src++;\r
++ }\r
++ if ((rc = write_word(info, wp, data)) != 0) {\r
++ return (rc);\r
++ }\r
++ wp += 4;\r
++ cnt -= 4;\r
++ }\r
++\r
++ if (cnt == 0) {\r
++ return (0);\r
++ }\r
++\r
++ /*\r
++ * handle unaligned tail bytes\r
++ */\r
++ data = 0;\r
++ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {\r
++ data = (data << 8) | *src++;\r
++ --cnt;\r
++ }\r
++ for (; i<4; ++i, ++cp) {\r
++ data = (data << 8) | (*(uchar *)cp);\r
++ }\r
++\r
++ return (write_word(info, wp, data));\r
++}\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Write a word to Flash, returns:\r
++ * 0 - OK\r
++ * 1 - write timeout\r
++ * 2 - Flash not erased\r
++ */\r
++static int write_word (flash_info_t *info, ulong dest, ulong data)\r
++{\r
++ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);\r
++ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;\r
++ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;\r
++ ulong start;\r
++ int flag;\r
++ int i;\r
++\r
++ /* Check if Flash is (sufficiently) erased */\r
++ if ((*((volatile ulong *)dest) & data) != data) {\r
++ return (2);\r
++ }\r
++ /* Disable interrupts which might cause a timeout here */\r
++ flag = disable_interrupts();\r
++\r
++ for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)\r
++ {\r
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;\r
++ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;\r
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;\r
++\r
++ dest2[i] = data2[i];\r
++\r
++ /* re-enable interrupts if necessary */\r
++ if (flag)\r
++ enable_interrupts();\r
++\r
++ /* data polling for D7 */\r
++ start = get_timer (0);\r
++ while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=\r
++ (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {\r
++ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {\r
++ return (1);\r
++ }\r
++ }\r
++ }\r
++\r
++ return (0);\r
++}\r
+diff -uNr u-boot-1.1.2/board/emetec405/pllmr.c u-boot-emetec-1.1.2/board/emetec405/pllmr.c\r
+--- u-boot-1.1.2/board/emetec405/pllmr.c 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/board/emetec405/pllmr.c 2005-03-14 22:32:04.000000000 +0200\r
+@@ -0,0 +1,19 @@\r
++#define PLL_CPUDIV_1 0x00000000\r
++#define PLL_PLBDIV_2 0x00010000\r
++#define PLL_OPBDIV_2 0x00001000\r
++#define PLL_EXTBUSDIV_3 0x00000100\r
++#define PLL_MALDIV_1 0x00000000\r
++#define PLL_PCIDIV_4 0x00000003\r
++\r
++#define PLL_FBKDIV_8 0x00800000\r
++#define PLL_FWDDIVA_4 0x00040000\r
++#define PLL_FWDDIVB_4 0x00004000\r
++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */\r
++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */\r
++\r
++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \\r
++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \\r
++ PLL_MALDIV_1 | PLL_PCIDIV_4)\r
++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \\r
++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \\r
++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)\r
+diff -uNr u-boot-1.1.2/board/emetec405/u-boot.lds u-boot-emetec-1.1.2/board/emetec405/u-boot.lds\r
+--- u-boot-1.1.2/board/emetec405/u-boot.lds 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/board/emetec405/u-boot.lds 2003-09-12 11:41:39.000000000 +0300\r
+@@ -0,0 +1,147 @@\r
++/*\r
++ * (C) Copyright 2000\r
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation; either version 2 of\r
++ * the License, or (at your option) any later version.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++\r
++OUTPUT_ARCH(powerpc)\r
++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);\r
++/* Do we need any of these for elf?\r
++ __DYNAMIC = 0; */\r
++SECTIONS\r
++{\r
++ .resetvec 0xFFFFFFFC :\r
++ {\r
++ *(.resetvec)\r
++ } = 0xffff\r
++\r
++ /* Read-only sections, merged into text segment: */\r
++ . = + SIZEOF_HEADERS;\r
++ .interp : { *(.interp) }\r
++ .hash : { *(.hash) }\r
++ .dynsym : { *(.dynsym) }\r
++ .dynstr : { *(.dynstr) }\r
++ .rel.text : { *(.rel.text) }\r
++ .rela.text : { *(.rela.text) }\r
++ .rel.data : { *(.rel.data) }\r
++ .rela.data : { *(.rela.data) }\r
++ .rel.rodata : { *(.rel.rodata) }\r
++ .rela.rodata : { *(.rela.rodata) }\r
++ .rel.got : { *(.rel.got) }\r
++ .rela.got : { *(.rela.got) }\r
++ .rel.ctors : { *(.rel.ctors) }\r
++ .rela.ctors : { *(.rela.ctors) }\r
++ .rel.dtors : { *(.rel.dtors) }\r
++ .rela.dtors : { *(.rela.dtors) }\r
++ .rel.bss : { *(.rel.bss) }\r
++ .rela.bss : { *(.rela.bss) }\r
++ .rel.plt : { *(.rel.plt) }\r
++ .rela.plt : { *(.rela.plt) }\r
++ .init : { *(.init) }\r
++ .plt : { *(.plt) }\r
++ .text :\r
++ {\r
++ /* WARNING - the following is hand-optimized to fit within */\r
++ /* the sector layout of our flash chips! XXX FIXME XXX */\r
++\r
++ cpu/ppc4xx/start.o (.text)\r
++ cpu/ppc4xx/traps.o (.text)\r
++ cpu/ppc4xx/interrupts.o (.text)\r
++ cpu/ppc4xx/serial.o (.text)\r
++ cpu/ppc4xx/cpu_init.o (.text)\r
++ cpu/ppc4xx/speed.o (.text)\r
++ cpu/ppc4xx/405gp_enet.o (.text)\r
++ common/dlmalloc.o (.text)\r
++ lib_generic/crc32.o (.text)\r
++ lib_ppc/extable.o (.text)\r
++ lib_generic/zlib.o (.text)\r
++\r
++/* . = env_offset;*/\r
++/* common/environment.o(.text)*/\r
++\r
++ *(.text)\r
++ *(.fixup)\r
++ *(.got1)\r
++ }\r
++ _etext = .;\r
++ PROVIDE (etext = .);\r
++ .rodata :\r
++ {\r
++ *(.rodata)\r
++ *(.rodata1)\r
++ *(.rodata.str1.4)\r
++ }\r
++ .fini : { *(.fini) } =0\r
++ .ctors : { *(.ctors) }\r
++ .dtors : { *(.dtors) }\r
++\r
++ /* Read-write section, merged into data segment: */\r
++ . = (. + 0x00FF) & 0xFFFFFF00;\r
++ _erotext = .;\r
++ PROVIDE (erotext = .);\r
++ .reloc :\r
++ {\r
++ *(.got)\r
++ _GOT2_TABLE_ = .;\r
++ *(.got2)\r
++ _FIXUP_TABLE_ = .;\r
++ *(.fixup)\r
++ }\r
++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;\r
++ __fixup_entries = (. - _FIXUP_TABLE_)>>2;\r
++\r
++ .data :\r
++ {\r
++ *(.data)\r
++ *(.data1)\r
++ *(.sdata)\r
++ *(.sdata2)\r
++ *(.dynamic)\r
++ CONSTRUCTORS\r
++ }\r
++ _edata = .;\r
++ PROVIDE (edata = .);\r
++\r
++ __u_boot_cmd_start = .;\r
++ .u_boot_cmd : { *(.u_boot_cmd) }\r
++ __u_boot_cmd_end = .;\r
++\r
++ __start___ex_table = .;\r
++ __ex_table : { *(__ex_table) }\r
++ __stop___ex_table = .;\r
++\r
++ . = ALIGN(256);\r
++ __init_begin = .;\r
++ .text.init : { *(.text.init) }\r
++ .data.init : { *(.data.init) }\r
++ . = ALIGN(256);\r
++ __init_end = .;\r
++\r
++ __bss_start = .;\r
++ .bss :\r
++ {\r
++ *(.sbss) *(.scommon)\r
++ *(.dynbss)\r
++ *(.bss)\r
++ *(COMMON)\r
++ }\r
++ _end = . ;\r
++ PROVIDE (end = .);\r
++}\r
+diff -uNr u-boot-1.1.2/copy.sh u-boot-emetec-1.1.2/copy.sh\r
+--- u-boot-1.1.2/copy.sh 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/copy.sh 2005-03-17 23:26:42.000000000 +0200\r
+@@ -0,0 +1,2 @@\r
++cp u-boot.bin /home/admin/uboot/uboot_v6.bin\r
++cp u-boot.srec /home/admin/uboot/uboot_v6.srec\r
+diff -uNr u-boot-1.1.2/cpu/ppc4xx/405gp_enet.c u-boot-emetec-1.1.2/cpu/ppc4xx/405gp_enet.c\r
+--- u-boot-1.1.2/cpu/ppc4xx/405gp_enet.c 2004-07-02 17:36:35.000000000 +0300\r
++++ u-boot-emetec-1.1.2/cpu/ppc4xx/405gp_enet.c 2005-05-06 18:07:02.000000000 +0300\r
+@@ -133,7 +133,7 @@\r
+ /*-----------------------------------------------------------------------------+\r
+ * Prototypes and externals.\r
+ *-----------------------------------------------------------------------------*/\r
+-static void enet_rcv (struct eth_device *dev, unsigned long malisr);\r
++static void enet_rcv (struct eth_device *dev, unsigned long malisr);\r
+ \r
+ int enetInt (struct eth_device *dev);\r
+ static void mal_err (struct eth_device *dev, unsigned long isr,\r
+@@ -190,11 +190,15 @@\r
+ unsigned short reg_short;\r
+ \r
+ EMAC_405_HW_PST hw_p = dev->priv;\r
++ \r
++ puts ("Test 1\n");\r
+ /* before doing anything, figure out if we have a MAC address */\r
+ /* if not, bail */\r
+ if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)\r
+ return -1;\r
+ \r
++ puts ("Test 2\n");\r
++ \r
+ msr = mfmsr ();\r
+ mtmsr (msr & ~(MSR_EE)); /* disable interrupts */\r
+ \r
+@@ -1023,6 +1027,8 @@\r
+ #else\r
+ emac0_dev = dev;\r
+ #endif\r
++ // print device name\r
++ printf("%s\n", dev->name);\r
+ \r
+ } /* end for each supported device */\r
+ \r
+diff -uNr u-boot-1.1.2/cpu/pxa/config.mk u-boot-emetec-1.1.2/cpu/pxa/config.mk\r
+--- u-boot-1.1.2/cpu/pxa/config.mk 2007-04-20 00:01:06.000000000 +0300\r
++++ u-boot-emetec-1.1.2/cpu/pxa/config.mk 2003-05-23 15:36:21.000000000 +0300\r
+@@ -23,6 +23,6 @@\r
+ #\r
+ \r
+ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \\r
+- -msoft-float\r
++ -mshort-load-bytes -msoft-float\r
+ \r
+ PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100\r
+diff -uNr u-boot-1.1.2/include/configs/EMETEC405.h u-boot-emetec-1.1.2/include/configs/EMETEC405.h\r
+--- u-boot-1.1.2/include/configs/EMETEC405.h 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/include/configs/EMETEC405.h 2005-05-25 10:08:39.000000000 +0300\r
+@@ -0,0 +1,349 @@\r
++/*\r
++ * (C) Copyright 2001-2003\r
++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation; either version 2 of\r
++ * the License, or (at your option) any later version.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++\r
++/*\r
++ * board/config.h - configuration options, board specific\r
++ */\r
++\r
++#ifndef __CONFIG_H\r
++#define __CONFIG_H\r
++\r
++#define FLASH_8MB 1\r
++/*\r
++ * High Level Configuration Options\r
++ * (easy to change)\r
++ */\r
++\r
++#define CONFIG_405EP 1 /* This is a PPC405 CPU */\r
++#define CONFIG_4xx 1 /* ...member of PPC4xx family */\r
++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */\r
++\r
++#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */\r
++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */\r
++\r
++#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */\r
++\r
++#define CONFIG_BAUDRATE 115200\r
++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */\r
++\r
++#undef CONFIG_BOOTARGS\r
++#undef CONFIG_BOOTCOMMAND\r
++#define CONFIG_EXTRA_ENV_SETTINGS \\r
++ "ramargs=setenv bootargs console=ttyS0,115200 " \\r
++ "root=/dev/ram rw\0" \\r
++ "flash_mem=run ramargs;" \\r
++ "bootm $(kernel_addr) $(ramdisk_addr)\0" \\r
++ "kernel_addr=ffC00000\0" \\r
++ "ramdisk_addr=ffCE0000\0" \\r
++ ""\r
++#define CONFIG_BOOTCOMMAND "run flash_mem"\r
++\r
++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */\r
++\r
++#define CONFIG_MII 1 /* MII PHY management */\r
++#define CONFIG_PHY_ADDR 0 /* PHY address */\r
++\r
++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \\r
++ CFG_CMD_NET | \\r
++ CFG_CMD_DHCP | \\r
++ CFG_CMD_IRQ | \\r
++ CFG_CMD_ELF | \\r
++ CFG_CMD_I2C | \\r
++ CFG_CMD_PING | \\r
++ CFG_CMD_EEPROM )\r
++\r
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */\r
++#include <cmd_confdefs.h>\r
++\r
++#undef CONFIG_WATCHDOG /* watchdog disabled */\r
++\r
++#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */\r
++\r
++/*\r
++ * Miscellaneous configurable options\r
++ */\r
++#define CFG_LONGHELP /* undef to save memory */\r
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */\r
++\r
++#undef CFG_HUSH_PARSER /* use "hush" command parser */\r
++#ifdef CFG_HUSH_PARSER\r
++#define CFG_PROMPT_HUSH_PS2 "> "\r
++#endif\r
++\r
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)\r
++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */\r
++#else\r
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */\r
++#endif\r
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */\r
++#define CFG_MAXARGS 16 /* max number of command args */\r
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */\r
++\r
++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */\r
++\r
++#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/\r
++\r
++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */\r
++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */\r
++\r
++#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */\r
++#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */\r
++#define CFG_BASE_BAUD 691200\r
++\r
++/* The following table includes the supported baudrates */\r
++#define CFG_BAUDRATE_TABLE \\r
++ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \\r
++ 57600, 115200, 230400, 460800, 921600 }\r
++\r
++#define CFG_LOAD_ADDR 0x100000 /* default load address */\r
++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */\r
++\r
++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */\r
++\r
++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */\r
++\r
++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */\r
++\r
++#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */\r
++\r
++/* Ethernet stuff */\r
++#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */\r
++#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE\r
++\r
++#define CONFIG_IPADDR 192.168.0.50\r
++#define CONFIG_NETMASK 255.255.255.0\r
++#define CONFIG_SERVERIP 192.168.0.1\r
++\r
++/*-----------------------------------------------------------------------\r
++ * PCI stuff\r
++ *-----------------------------------------------------------------------\r
++ */\r
++#define PCI_HOST_ADAPTER 0 // configure as pci adapter\r
++#define PCI_HOST_FORCE 1 // configure as pci host\r
++#define PCI_HOST_AUTO 2 // detected via arbiter enable\r
++\r
++#define CONFIG_PCI // include pci support\r
++#define CONFIG_PCI_HOST PCI_HOST_FORCE // select pci host function\r
++#define CONFIG_PCI_PNP // do pci plug-and-play\r
++\r
++\r
++#define CFG_PCI_SUBSYS_VENDORID 0x0000 // PCI Vendor ID: IBM\r
++#define CFG_PCI_SUBSYS_DEVICEID 0x0000 // PCI Device ID: 405GP\r
++#define CFG_PCI_PTM1LA 0x00000000 // point to sdram\r
++#define CFG_PCI_PTM1MS 0x80000001 // 2GB, enable hard-wired to 1\r
++#define CFG_PCI_PTM1PCI 0x00000000 // Host: use this pci address\r
++#define CFG_PCI_PTM2LA 0x00000000 // disabled\r
++#define CFG_PCI_PTM2MS 0x00000000 // disabled\r
++#define CFG_PCI_PTM2PCI 0x00000000 // Host: use this pci address\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Start addresses for the final memory configuration\r
++ * (Set up by the startup code)\r
++ * Please note that CFG_SDRAM_BASE _must_ start at 0\r
++ */\r
++ \r
++/*\r
++ * Flash configuration (8,16 or 32 MB)\r
++ * TEXT base always at 0xFFF00000\r
++ * ENV_ADDR always at 0xFFF40000\r
++ * FLASH_BASE at 0xFE000000 for 32 MB\r
++ * 0xFF000000 for 16 MB\r
++ * 0xFF800000 for 8 MB\r
++ * 0xFFC00000 for 4 MB\r
++ */\r
++ \r
++#define CFG_SDRAM_BASE 0x00000000\r
++#define CFG_FLASH_BASE 0xFFFC0000\r
++#define CFG_MONITOR_BASE CFG_FLASH_BASE\r
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */\r
++#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */\r
++\r
++/*\r
++ * For booting Linux, the board info and command line data\r
++ * have to be in the first 8 MB of memory, since this is\r
++ * the maximum mapped by the Linux kernel during initialization.\r
++ */\r
++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */\r
++/*-----------------------------------------------------------------------\r
++ * FLASH organization\r
++ */\r
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */\r
++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */\r
++\r
++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */\r
++#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */\r
++\r
++#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */\r
++#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */\r
++#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */\r
++/*\r
++ * The following defines are added for buggy IOP480 byte interface.\r
++ * All other boards should use the standard values (CPCI405 etc.)\r
++ */\r
++#define CFG_FLASH_READ0 0x0000 /* 0 is standard */\r
++#define CFG_FLASH_READ1 0x0001 /* 1 is standard */\r
++#define CFG_FLASH_READ2 0x0002 /* 2 is standard */\r
++\r
++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */\r
++\r
++/*\r
++#define CFG_ENV_IS_IN_FLASH 1\r
++//Address and size of Primary Environment Sector\r
++#define CFG_ENV_ADDR 0xFFFFA000\r
++#define CFG_ENV_SIZE 0x2000\r
++*/\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Environment Variable setup\r
++ */\r
++#define CFG_ENV_IS_IN_EEPROM 1 // use EEPROM for environment vars\r
++#define CFG_ENV_OFFSET 0x100 // environment starts at the beginning of the EEPROM\r
++#define CFG_ENV_SIZE 0x700 // 2048 bytes may be used for env vars\r
++\r
++/*-----------------------------------------------------------------------\r
++ * I2C EEPROM (CAT24WC16) for environment\r
++ */\r
++#define CONFIG_HARD_I2C // I2c with hardware support\r
++#define CFG_I2C_SPEED 400000 // I2C speed and slave address\r
++#define CFG_I2C_SLAVE 0x7F\r
++\r
++#define CFG_I2C_EEPROM_ADDR 0x50 // EEPROM CAT28WC08\r
++#define CFG_I2C_EEPROM_ADDR_LEN 1 // Bytes of address\r
++\r
++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07\r
++#define CFG_EEPROM_PAGE_WRITE_BITS 4 // The Catalyst CAT24WC08 has\r
++ // 16 byte page write mode using\r
++ // last 4 bits of the address\r
++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 // and takes up to 10 msec\r
++#define CFG_EEPROM_PAGE_WRITE_ENABLE\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Cache Configuration\r
++ */\r
++#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */\r
++ /* have only 8kB, 16kB is save here */\r
++#define CFG_CACHELINE_SIZE 32 /* ... */\r
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)\r
++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */\r
++#endif\r
++\r
++/*\r
++ * Init Memory Controller:\r
++ *\r
++ * BR0/1 and OR0/1 (FLASH)\r
++ */\r
++\r
++#if FLASH_8MB == 1\r
++#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */\r
++#else\r
++#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */\r
++#endif\r
++\r
++/*-----------------------------------------------------------------------\r
++ * External Bus Controller (EBC) Setup\r
++ */\r
++\r
++/* Memory Bank 0 (Flash Bank 0) initialization */\r
++#if FLASH_8MB == 1\r
++#define CFG_EBC_PB0AP 0x92015480\r
++#define CFG_EBC_PB0CR 0xFFC5B000 /* BAS=0xFFC,BS=8MB,BU=R/W,BW=16bit */\r
++#else\r
++#define CFG_EBC_PB0AP 0x92015480\r
++#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */\r
++#endif\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Definitions for initial stack pointer and data area (in data cache)\r
++ */\r
++/* use on chip memory ( OCM ) for temperary stack until sdram is tested */\r
++#define CFG_TEMP_STACK_OCM 1\r
++\r
++/* On Chip Memory location */\r
++#define CFG_OCM_DATA_ADDR 0xF8000000\r
++#define CFG_OCM_DATA_SIZE 0x1000\r
++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */\r
++#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */\r
++\r
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */\r
++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)\r
++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Definitions for GPIO setup (PPC405EP specific)\r
++ *\r
++ * GPIO0[0] - External Bus Controller BLAST output\r
++ * GPIO0[1-9] - Instruction trace outputs -> GPIO\r
++ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs\r
++ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO\r
++ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs\r
++ * GPIO0[24-27] - UART0 control signal inputs/outputs\r
++ * GPIO0[28-29] - UART1 data signal input/output\r
++ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs\r
++ */\r
++#define CFG_GPIO0_OSRH 0x40000550\r
++#define CFG_GPIO0_OSRL 0x00000110\r
++#define CFG_GPIO0_ISR1H 0x00000000\r
++#define CFG_GPIO0_ISR1L 0x15555445\r
++#define CFG_GPIO0_TSRH 0x00000000\r
++#define CFG_GPIO0_TSRL 0x00000000\r
++#define CFG_GPIO0_TCR 0xF7FE0014\r
++\r
++/*\r
++ * Internal Definitions\r
++ *\r
++ * Boot Flags\r
++ */\r
++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */\r
++#define BOOTFLAG_WARM 0x02 /* Software reboot */\r
++\r
++#define PLL_CPUDIV_1 0x00000000\r
++#define PLL_PLBDIV_2 0x00010000\r
++#define PLL_OPBDIV_2 0x00001000\r
++\r
++#define PLL_EXTBUSDIV_4 0x00000200\r
++\r
++#define PLL_MALDIV_1 0x00000000\r
++#define PLL_PCIDIV_2 0x00000001\r
++#define PLL_PCIDIV_4 0x00000003\r
++\r
++#define PLL_FBKDIV_8 0x00800000\r
++\r
++#define PLL_FWDDIVA_4 0x00040000\r
++#define PLL_FWDDIVB_4 0x00004000\r
++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */\r
++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */\r
++\r
++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \\r
++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \\r
++ PLL_MALDIV_1 | PLL_PCIDIV_4)\r
++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \\r
++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \\r
++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)\r
++/*\r
++ * Default speed selection (cpu_plb_opb_ebc) in mhz.\r
++ * This value will be set if iic boot eprom is disabled.\r
++ */\r
++#define PLLMR0_DEFAULT PLLMR0_200_100_50_25\r
++#define PLLMR1_DEFAULT PLLMR1_200_100_50_25\r
++\r
++#endif /* __CONFIG_H */\r
+diff -uNr u-boot-1.1.2/include/configs/EMETEC405.h.old u-boot-emetec-1.1.2/include/configs/EMETEC405.h.old\r
+--- u-boot-1.1.2/include/configs/EMETEC405.h.old 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/include/configs/EMETEC405.h.old 2005-03-17 23:00:33.000000000 +0200\r
+@@ -0,0 +1,349 @@\r
++/*\r
++ * (C) Copyright 2001-2003\r
++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com\r
++ *\r
++ * See file CREDITS for list of people who contributed to this\r
++ * project.\r
++ *\r
++ * This program is free software; you can redistribute it and/or\r
++ * modify it under the terms of the GNU General Public License as\r
++ * published by the Free Software Foundation; either version 2 of\r
++ * the License, or (at your option) any later version.\r
++ *\r
++ * This program is distributed in the hope that it will be useful,\r
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
++ * GNU General Public License for more details.\r
++ *\r
++ * You should have received a copy of the GNU General Public License\r
++ * along with this program; if not, write to the Free Software\r
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
++ * MA 02111-1307 USA\r
++ */\r
++\r
++/*\r
++ * board/config.h - configuration options, board specific\r
++ */\r
++\r
++#ifndef __CONFIG_H\r
++#define __CONFIG_H\r
++\r
++/*\r
++ * High Level Configuration Options\r
++ * (easy to change)\r
++ */\r
++\r
++#define CONFIG_405EP 1 /* This is a PPC405 CPU */\r
++#define CONFIG_4xx 1 /* ...member of PPC4xx family */\r
++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */\r
++\r
++#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */\r
++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */\r
++\r
++#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */\r
++\r
++#define CONFIG_BAUDRATE 115200\r
++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */\r
++\r
++#undef CONFIG_BOOTARGS\r
++#undef CONFIG_BOOTCOMMAND\r
++\r
++#define CONFIG_PREBOOT /* enable preboot variable */\r
++\r
++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */\r
++\r
++#define CONFIG_MII 1 /* MII PHY management */\r
++#define CONFIG_PHY_ADDR 0 /* PHY address */\r
++#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */\r
++\r
++/*\r
++#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ // 66 MHz OPB clock\r
++*/\r
++\r
++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \\r
++ CFG_CMD_DHCP | \\r
++ CFG_CMD_IRQ | \\r
++ CFG_CMD_ELF | \\r
++ CFG_CMD_I2C | \\r
++ CFG_CMD_MII | \\r
++ CFG_CMD_PING | \\r
++ CFG_CMD_EEPROM )\r
++\r
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */\r
++#include <cmd_confdefs.h>\r
++\r
++#undef CONFIG_WATCHDOG /* watchdog disabled */\r
++\r
++#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */\r
++\r
++/*\r
++ * Miscellaneous configurable options\r
++ */\r
++#define CFG_LONGHELP /* undef to save memory */\r
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */\r
++\r
++#undef CFG_HUSH_PARSER /* use "hush" command parser */\r
++#ifdef CFG_HUSH_PARSER\r
++#define CFG_PROMPT_HUSH_PS2 "> "\r
++#endif\r
++\r
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)\r
++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */\r
++#else\r
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */\r
++#endif\r
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */\r
++#define CFG_MAXARGS 16 /* max number of command args */\r
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */\r
++\r
++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */\r
++\r
++#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/\r
++\r
++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */\r
++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */\r
++\r
++#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */\r
++#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */\r
++#define CFG_BASE_BAUD 691200\r
++#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */\r
++\r
++/* The following table includes the supported baudrates */\r
++#define CFG_BAUDRATE_TABLE \\r
++ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \\r
++ 57600, 115200, 230400, 460800, 921600 }\r
++\r
++#define CFG_LOAD_ADDR 0x100000 /* default load address */\r
++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */\r
++\r
++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */\r
++\r
++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */\r
++\r
++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */\r
++\r
++#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */\r
++\r
++/* Ethernet stuff */\r
++#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */\r
++#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE\r
++#define CONFIG_HAS_ETH1\r
++#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD\r
++\r
++#define CONFIG_IPADDR 192.168.0.50\r
++#define CONFIG_IP1ADDR 192.168.0.51\r
++#define CONFIG_NETMASK 255.255.255.0\r
++#define CONFIG_SERVERIP 192.168.0.1\r
++\r
++/*-----------------------------------------------------------------------\r
++ * PCI stuff\r
++ *-----------------------------------------------------------------------\r
++ */\r
++#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */\r
++#define PCI_HOST_FORCE 1 /* configure as pci host */\r
++#define PCI_HOST_AUTO 2 /* detected via arbiter enable */\r
++\r
++#undef CONFIG_PCI /* include pci support */\r
++#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */\r
++#undef CONFIG_PCI_PNP /* do pci plug-and-play */\r
++ /* resource configuration */\r
++\r
++#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */\r
++\r
++#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */\r
++#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */\r
++#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/\r
++#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */\r
++#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */\r
++#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */\r
++#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */\r
++#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */\r
++#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Start addresses for the final memory configuration\r
++ * (Set up by the startup code)\r
++ * Please note that CFG_SDRAM_BASE _must_ start at 0\r
++ */\r
++#define CFG_SDRAM_BASE 0x00000000\r
++#define CFG_FLASH_BASE 0xFFFC0000\r
++#define CFG_MONITOR_BASE CFG_FLASH_BASE\r
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */\r
++#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */\r
++\r
++/*\r
++ * For booting Linux, the board info and command line data\r
++ * have to be in the first 8 MB of memory, since this is\r
++ * the maximum mapped by the Linux kernel during initialization.\r
++ */\r
++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */\r
++/*-----------------------------------------------------------------------\r
++ * FLASH organization\r
++ */\r
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */\r
++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */\r
++\r
++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */\r
++#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */\r
++\r
++#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */\r
++#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */\r
++#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */\r
++/*\r
++ * The following defines are added for buggy IOP480 byte interface.\r
++ * All other boards should use the standard values (CPCI405 etc.)\r
++ */\r
++#define CFG_FLASH_READ0 0x0000 /* 0 is standard */\r
++#define CFG_FLASH_READ1 0x0001 /* 1 is standard */\r
++#define CFG_FLASH_READ2 0x0002 /* 2 is standard */\r
++\r
++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */\r
++\r
++#if 0 /* test-only */\r
++#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */\r
++#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */\r
++#endif\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Environment Variable setup\r
++ */\r
++#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */\r
++#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */\r
++#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/\r
++ /* total size of a CAT24WC16 is 2048 bytes */\r
++\r
++#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */\r
++#define CFG_NVRAM_SIZE 242 /* NVRAM size */\r
++\r
++/*-----------------------------------------------------------------------\r
++ * I2C EEPROM (CAT24WC16) for environment\r
++ */\r
++#define CONFIG_HARD_I2C /* I2c with hardware support */\r
++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */\r
++#define CFG_I2C_SLAVE 0x7F\r
++\r
++#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */\r
++#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */\r
++/* mask of address bits that overflow into the "EEPROM chip address" */\r
++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07\r
++#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */\r
++ /* 16 byte page write mode using*/\r
++ /* last 4 bits of the address */\r
++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */\r
++#define CFG_EEPROM_PAGE_WRITE_ENABLE\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Cache Configuration\r
++ */\r
++#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */\r
++ /* have only 8kB, 16kB is save here */\r
++#define CFG_CACHELINE_SIZE 32 /* ... */\r
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)\r
++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */\r
++#endif\r
++\r
++/*\r
++ * Init Memory Controller:\r
++ *\r
++ * BR0/1 and OR0/1 (FLASH)\r
++ */\r
++\r
++#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */\r
++\r
++/*-----------------------------------------------------------------------\r
++ * External Bus Controller (EBC) Setup\r
++ */\r
++\r
++/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */\r
++#define CFG_EBC_PB0AP 0x92015480\r
++#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */\r
++\r
++#define DUART0_BA 0xF0000000 /* DUART Base Address */\r
++#define DUART1_BA 0xF0000008 /* DUART Base Address */\r
++#define DUART2_BA 0xF0000010 /* DUART Base Address */\r
++#define DUART3_BA 0xF0000018 /* DUART Base Address */\r
++\r
++/*-----------------------------------------------------------------------\r
++ * FPGA stuff\r
++ */\r
++#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */\r
++#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/\r
++\r
++/* FPGA program pin configuration */\r
++#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */\r
++#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */\r
++#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */\r
++#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */\r
++#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Definitions for initial stack pointer and data area (in data cache)\r
++ */\r
++/* use on chip memory ( OCM ) for temperary stack until sdram is tested */\r
++#define CFG_TEMP_STACK_OCM 1\r
++\r
++/* On Chip Memory location */\r
++#define CFG_OCM_DATA_ADDR 0xF8000000\r
++#define CFG_OCM_DATA_SIZE 0x1000\r
++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */\r
++#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */\r
++\r
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */\r
++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)\r
++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET\r
++\r
++/*-----------------------------------------------------------------------\r
++ * Definitions for GPIO setup (PPC405EP specific)\r
++ *\r
++ * GPIO0[0] - External Bus Controller BLAST output\r
++ * GPIO0[1-9] - Instruction trace outputs -> GPIO\r
++ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs\r
++ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO\r
++ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs\r
++ * GPIO0[24-27] - UART0 control signal inputs/outputs\r
++ * GPIO0[28-29] - UART1 data signal input/output\r
++ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs\r
++ */\r
++#define CFG_GPIO0_OSRH 0x40000550\r
++#define CFG_GPIO0_OSRL 0x00000110\r
++#define CFG_GPIO0_ISR1H 0x00000000\r
++#define CFG_GPIO0_ISR1L 0x15555445\r
++#define CFG_GPIO0_TSRH 0x00000000\r
++#define CFG_GPIO0_TSRL 0x00000000\r
++#define CFG_GPIO0_TCR 0xF7FE0014\r
++\r
++/*\r
++ * Internal Definitions\r
++ *\r
++ * Boot Flags\r
++ */\r
++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */\r
++#define BOOTFLAG_WARM 0x02 /* Software reboot */\r
++\r
++#define PLL_CPUDIV_1 0x00000000\r
++#define PLL_PLBDIV_2 0x00010000\r
++#define PLL_OPBDIV_2 0x00001000\r
++#define PLL_EXTBUSDIV_3 0x00000100\r
++#define PLL_MALDIV_1 0x00000000\r
++#define PLL_PCIDIV_4 0x00000003\r
++\r
++#define PLL_FBKDIV_8 0x00800000\r
++#define PLL_FWDDIVA_4 0x00040000\r
++#define PLL_FWDDIVB_4 0x00004000\r
++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */\r
++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */\r
++\r
++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \\r
++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \\r
++ PLL_MALDIV_1 | PLL_PCIDIV_4)\r
++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \\r
++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \\r
++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)\r
++/*\r
++ * Default speed selection (cpu_plb_opb_ebc) in mhz.\r
++ * This value will be set if iic boot eprom is disabled.\r
++ */\r
++#define PLLMR0_DEFAULT PLLMR0_200_100_50_25\r
++#define PLLMR1_DEFAULT PLLMR1_200_100_50_25\r
++\r
++#endif /* __CONFIG_H */\r
+diff -uNr u-boot-1.1.2/include/configs/HUB405.h u-boot-emetec-1.1.2/include/configs/HUB405.h\r
+--- u-boot-1.1.2/include/configs/HUB405.h 2004-12-31 11:32:53.000000000 +0200\r
++++ u-boot-emetec-1.1.2/include/configs/HUB405.h 2005-03-11 22:19:12.000000000 +0200\r
+@@ -35,7 +35,7 @@\r
+ \r
+ #define CONFIG_405EP 1 /* This is a PPC405 CPU */\r
+ #define CONFIG_4xx 1 /* ...member of PPC4xx family */\r
+-#define CONFIG_HUB405 1 /* ...on a HUB405 board */\r
++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */\r
+ \r
+ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */\r
+ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */\r
+diff -uNr u-boot-1.1.2/include/flash.h u-boot-emetec-1.1.2/include/flash.h\r
+--- u-boot-1.1.2/include/flash.h 2004-12-16 20:01:48.000000000 +0200\r
++++ u-boot-emetec-1.1.2/include/flash.h 2005-05-25 10:04:56.000000000 +0300\r
+@@ -229,7 +229,11 @@\r
+ \r
+ #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */\r
+ #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */\r
+-#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */\r
++#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect)*/\r
++\r
++#define STM_ID_29W640DT 0x22DE22DE /* M29W640DT ID (64 M, top boot sector) */\r
++#define STM_ID_29W640DB 0x22DF22DF /* M29W640DB ID (64 M, bottom boot sect)*/\r
++\r
+ #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */\r
+ \r
+ #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */\r
+@@ -328,6 +332,8 @@\r
+ #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */\r
+ #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */\r
+ #define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/\r
++#define FLASH_STMW640DT 0x0054 /* STM M29W640DT (64 M, top boot sector) */\r
++#define FLASH_STMW640DB 0x0055 /* STM M29W640DB (64 M, bottom boot sect)*/\r
+ #define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/\r
+ #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */\r
+ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/\r
+diff -uNr u-boot-1.1.2/include/net.h u-boot-emetec-1.1.2/include/net.h\r
+--- u-boot-1.1.2/include/net.h 2004-10-10 00:56:21.000000000 +0300\r
++++ u-boot-emetec-1.1.2/include/net.h 2005-04-27 23:16:40.000000000 +0300\r
+@@ -331,9 +331,9 @@\r
+ #define NETLOOP_SUCCESS 3\r
+ #define NETLOOP_FAIL 4\r
+ \r
+-#ifdef CONFIG_NET_MULTI\r
++/* #ifdef CONFIG_NET_MULTI */\r
+ extern int NetRestartWrap; /* Tried all network devices */\r
+-#endif\r
++/* #endif */\r
+ \r
+ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS } proto_t;\r
+ \r
+diff -uNr u-boot-1.1.2/lib_ppc/board.c u-boot-emetec-1.1.2/lib_ppc/board.c\r
+--- u-boot-1.1.2/lib_ppc/board.c 2004-12-31 11:32:54.000000000 +0200\r
++++ u-boot-emetec-1.1.2/lib_ppc/board.c 2005-04-27 23:03:33.000000000 +0300\r
+@@ -970,7 +970,8 @@\r
+ nand_init(); /* go init the NAND */\r
+ #endif\r
+ \r
+-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)\r
++\r
++#if (CONFIG_COMMANDS & CFG_CMD_NET) /* && defined(CONFIG_NET_MULTI) */\r
+ WATCHDOG_RESET ();\r
+ puts ("Net: ");\r
+ eth_initialize (bd);\r
+diff -uNr u-boot-1.1.2/loadftp.sh u-boot-emetec-1.1.2/loadftp.sh\r
+--- u-boot-1.1.2/loadftp.sh 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/loadftp.sh 2005-04-25 21:30:54.000000000 +0300\r
+@@ -0,0 +1 @@\r
++cp u-boot.bin /home/ftp/uboot.bin\r
+diff -uNr u-boot-1.1.2/loadwww.sh u-boot-emetec-1.1.2/loadwww.sh\r
+--- u-boot-1.1.2/loadwww.sh 1970-01-01 02:00:00.000000000 +0200\r
++++ u-boot-emetec-1.1.2/loadwww.sh 2005-03-12 13:06:19.000000000 +0200\r
+@@ -0,0 +1,2 @@\r
++#!/bin/bash\r
++rsync -vzr --rsh='ssh -l admin -p 5522' /home/admin/uboot/ admin@mhaber.net:/home/admin/uboot\r
+diff -uNr u-boot-1.1.2/net/eth.c u-boot-emetec-1.1.2/net/eth.c\r
+--- u-boot-1.1.2/net/eth.c 2004-12-16 19:49:38.000000000 +0200\r
++++ u-boot-emetec-1.1.2/net/eth.c 2005-05-06 18:04:08.000000000 +0300\r
+@@ -25,7 +25,7 @@\r
+ #include <command.h>\r
+ #include <net.h>\r
+ \r
+-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)\r
++#if (CONFIG_COMMANDS & CFG_CMD_NET) /* && defined(CONFIG_NET_MULTI) */\r
+ \r
+ #ifdef CFG_GT_6426x\r
+ extern int gt6426x_eth_initialize(bd_t *bis);\r
+@@ -126,10 +126,13 @@\r
+ #ifdef CONFIG_DB64460\r
+ mv6446x_eth_initialize(bis);\r
+ #endif\r
++\r
+ #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \\r
+ ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) )\r
+ ppc_4xx_eth_initialize(bis);\r
++ eth_number=1;\r
+ #endif\r
++\r
+ #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)\r
+ ppc_440x_eth_initialize(bis);\r
+ #endif\r
+@@ -197,6 +200,7 @@\r
+ rtl8169_initialize(bis);\r
+ #endif\r
+ \r
++#if defined(CONFIG_NET_MULTI)\r
+ if (!eth_devices) {\r
+ puts ("No ethernet found.\n");\r
+ } else {\r
+@@ -248,7 +252,6 @@\r
+ dev = dev->next;\r
+ } while(dev != eth_devices);\r
+ \r
+-#ifdef CONFIG_NET_MULTI\r
+ /* update current ethernet name */\r
+ if (eth_current) {\r
+ char *act = getenv("ethact");\r
+@@ -256,14 +259,14 @@\r
+ setenv("ethact", eth_current->name);\r
+ } else\r
+ setenv("ethact", NULL);\r
+-#endif\r
+-\r
+ putc ('\n');\r
+ }\r
++#endif\r
+ \r
+ return eth_number;\r
+ }\r
+ \r
++#ifdef CONFIG_NET_MULTI\r
+ void eth_set_enetaddr(int num, char *addr) {\r
+ struct eth_device *dev;\r
+ unsigned char enetaddr[6];\r
+@@ -362,21 +365,20 @@\r
+ \r
+ eth_current = eth_current->next;\r
+ \r
+-#ifdef CONFIG_NET_MULTI\r
++//#ifdef CONFIG_NET_MULTI\r
+ /* update current ethernet name */\r
+ {\r
+ char *act = getenv("ethact");\r
+ if (act == NULL || strcmp(act, eth_current->name) != 0)\r
+ setenv("ethact", eth_current->name);\r
+ }\r
+-#endif\r
++//#endif\r
+ \r
+ if (first_failed == eth_current) {\r
+ NetRestartWrap = 1;\r
+ }\r
+ }\r
+ \r
+-#ifdef CONFIG_NET_MULTI\r
+ void eth_set_current(void)\r
+ {\r
+ char *act;\r
+@@ -397,10 +399,11 @@\r
+ \r
+ setenv("ethact", eth_current->name);\r
+ }\r
+-#endif\r
+ \r
+ char *eth_get_name (void)\r
+ {\r
+ return (eth_current ? eth_current->name : "unknown");\r
+ }\r
+ #endif\r
++\r
++#endif\r
+diff -uNr u-boot-1.1.2/net/net.c u-boot-emetec-1.1.2/net/net.c\r
+--- u-boot-1.1.2/net/net.c 2004-10-12 01:51:14.000000000 +0300\r
++++ u-boot-emetec-1.1.2/net/net.c 2005-04-27 23:34:20.000000000 +0300\r
+@@ -126,11 +126,11 @@\r
+ { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc };\r
+ #endif\r
+ int NetState; /* Network loop state */\r
+-#ifdef CONFIG_NET_MULTI\r
++/* #ifdef CONFIG_NET_MULTI */\r
+ int NetRestartWrap = 0; /* Tried all network devices */\r
+ static int NetRestarted = 0; /* Network loop restarted */\r
+ static int NetDevExists = 0; /* At least one device configured */\r
+-#endif\r
++/* #endif */\r
+ \r
+ /* XXX in both little & big endian machines 0xFFFF == ntohs(-1) */\r
+ ushort NetOurVLAN = 0xFFFF; /* default is without VLAN */\r
+diff -uNr u-boot-1.1.2/patches/arm_flags.patch u-boot-emetec-1.1.2/patches/arm_flags.patch\r
+--- u-boot-1.1.2/patches/arm_flags.patch 2007-04-20 00:01:06.000000000 +0300\r
++++ u-boot-emetec-1.1.2/patches/arm_flags.patch 1970-01-01 02:00:00.000000000 +0200\r
+@@ -1,15 +0,0 @@\r
+-\r
+-#\r
+-# Patch managed by http://www.holgerschurig.de/patcher.html\r
+-#\r
+-\r
+---- u-boot-1.1.2/cpu/pxa/config.mk~armflags\r
+-+++ u-boot-1.1.2/cpu/pxa/config.mk\r
+-@@ -23,6 +23,6 @@\r
+- #\r
+- \r
+- PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \\r
+-- -mshort-load-bytes -msoft-float\r
+-+ -msoft-float\r
+- \r
+- PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100\r
+diff -uNr u-boot-1.1.2/patches/series u-boot-emetec-1.1.2/patches/series\r
+--- u-boot-1.1.2/patches/series 2007-04-20 00:01:06.000000000 +0300\r
++++ u-boot-emetec-1.1.2/patches/series 1970-01-01 02:00:00.000000000 +0200\r
+@@ -1 +0,0 @@\r
+-arm_flags.patch -p1\r
+diff -uNr u-boot-1.1.2/lib_ppc/board.c new-uboot-1.1.2/lib_ppc/board.c\r
+--- u-boot-1.1.2/lib_ppc/board.c 2005-04-27 23:03:33.000000000 +0300\r
++++ new-uboot-1.1.2/lib_ppc/board.c 2007-04-20 00:55:16.000000000 +0300\r
+@@ -347,6 +347,7 @@\r
+ \r
+ bd_t *bd;\r
+ ulong len, addr, addr_sp;\r
++ ulong *s;\r
+ gd_t *id;\r
+ init_fnc_t **init_fnc_ptr;\r
+ #ifdef CONFIG_PRAM\r
+@@ -466,8 +467,10 @@\r
+ */\r
+ addr_sp -= 16;\r
+ addr_sp &= ~0xF;\r
+- *((ulong *) addr_sp)-- = 0;\r
+- *((ulong *) addr_sp)-- = 0;\r
++ s = (ulong *)addr_sp;\r
++ *s-- = 0;\r
++ *s-- = 0;\r
++ addr_sp = (ulong)s;\r
+ debug ("Stack Pointer at: %08lx\n", addr_sp);\r
+ \r
+ /*\r
+diff -uNr u-boot-1.1.2/net/net.c new-uboot-1.1.2/net/net.c\r
+--- u-boot-1.1.2/net/net.c 2005-04-27 23:34:20.000000000 +0300\r
++++ new-uboot-1.1.2/net/net.c 2007-04-20 01:00:26.000000000 +0300\r
+@@ -1491,14 +1491,17 @@\r
+ unsigned\r
+ NetCksum(uchar * ptr, int len)\r
+ {\r
+- ulong xsum;\r
+ \r
+- xsum = 0;\r
+- while (len-- > 0)\r
+- xsum += *((ushort *)ptr)++;\r
+- xsum = (xsum & 0xffff) + (xsum >> 16);\r
+- xsum = (xsum & 0xffff) + (xsum >> 16);\r
+- return (xsum & 0xffff);\r
++ ulong xsum;\r
++ ushort *p = (ushort *)ptr;\r
++\r
++ xsum = 0;\r
++ while (len-- > 0)\r
++ xsum += *p++;\r
++ xsum = (xsum & 0xffff) + (xsum >> 16);\r
++ xsum = (xsum & 0xffff) + (xsum >> 16);\r
++ return (xsum & 0xffff);\r
++\r
+ }\r
+ \r
+ int\r
+diff -uNr u-boot-1.1.2/net/tftp.c new-uboot-1.1.2/net/tftp.c\r
+--- u-boot-1.1.2/net/tftp.c 2004-04-16 00:48:55.000000000 +0300\r
++++ new-uboot-1.1.2/net/tftp.c 2005-12-16 18:39:27.000000000 +0200\r
+@@ -58,7 +58,7 @@\r
+ static char *tftp_filename;\r
+ \r
+ #ifdef CFG_DIRECT_FLASH_TFTP\r
+-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];\r
++extern flash_info_t flash_info[];\r
+ #endif\r
+ \r
+ static __inline__ void\r
+@@ -78,7 +78,7 @@\r
+ }\r
+ \r
+ if (rc) { /* Flash is destination for this packet */\r
+- rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);\r
++ rc = flash_write ((char *)src, (ulong)(load_addr+offset), len);\r
+ if (rc) {\r
+ flash_perror (rc);\r
+ NetState = NETLOOP_FAIL;\r
+@@ -106,6 +106,7 @@\r
+ volatile uchar * pkt;\r
+ volatile uchar * xp;\r
+ int len = 0;\r
++ volatile ushort *s;\r
+ \r
+ /*\r
+ * We will always be sending some sort of packet, so\r
+@@ -117,7 +118,9 @@\r
+ \r
+ case STATE_RRQ:\r
+ xp = pkt;\r
+- *((ushort *)pkt)++ = htons(TFTP_RRQ);\r
++ s = (ushort *)pkt;\r
++ *s++ = htons(TFTP_RRQ);\r
++ pkt = (uchar *)s;\r
+ strcpy ((char *)pkt, tftp_filename);\r
+ pkt += strlen(tftp_filename) + 1;\r
+ strcpy ((char *)pkt, "octet");\r
+@@ -135,15 +138,19 @@\r
+ case STATE_DATA:\r
+ case STATE_OACK:\r
+ xp = pkt;\r
+- *((ushort *)pkt)++ = htons(TFTP_ACK);\r
+- *((ushort *)pkt)++ = htons(TftpBlock);\r
++ s = (ushort *)pkt;\r
++ *s++ = htons(TFTP_ACK);\r
++ *s++ = htons(TftpBlock);\r
++ pkt = (uchar *)s;\r
+ len = pkt - xp;\r
+ break;\r
+ \r
+ case STATE_TOO_LARGE:\r
+ xp = pkt;\r
+- *((ushort *)pkt)++ = htons(TFTP_ERROR);\r
+- *((ushort *)pkt)++ = htons(3);\r
++ s = (ushort *)pkt;\r
++ *s++ = htons(TFTP_ERROR);\r
++ *s++ = htons(3);\r
++ pkt = (uchar *)s;\r
+ strcpy ((char *)pkt, "File too large");\r
+ pkt += 14 /*strlen("File too large")*/ + 1;\r
+ len = pkt - xp;\r
+@@ -151,8 +158,10 @@\r
+ \r
+ case STATE_BAD_MAGIC:\r
+ xp = pkt;\r
+- *((ushort *)pkt)++ = htons(TFTP_ERROR);\r
+- *((ushort *)pkt)++ = htons(2);\r
++ s = (ushort *)pkt;\r
++ *s++ = htons(TFTP_ERROR);\r
++ *s++ = htons(2);\r
++ pkt = (uchar *)s;\r
+ strcpy ((char *)pkt, "File has bad magic");\r
+ pkt += 18 /*strlen("File has bad magic")*/ + 1;\r
+ len = pkt - xp;\r
+@@ -167,6 +176,7 @@\r
+ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)\r
+ {\r
+ ushort proto;\r
++ ushort *s;\r
+ \r
+ if (dest != TftpOurPort) {\r
+ return;\r
+@@ -180,7 +190,9 @@\r
+ }\r
+ len -= 2;\r
+ /* warning: don't use increment (++) in ntohs() macros!! */\r
+- proto = *((ushort *)pkt)++;\r
++ s = (ushort *)pkt;\r
++ proto = *s++;\r
++ pkt = (uchar *)s;\r
+ switch (ntohs(proto)) {\r
+ \r
+ case TFTP_RRQ:\r
+@@ -301,14 +313,16 @@\r
+ void\r
+ TftpStart (void)\r
+ {\r
+- if (BootFile[0] == '\0') {\r
+- IPaddr_t OurIP = ntohl(NetOurIP);\r
++#ifdef CONFIG_TFTP_PORT\r
++ char *ep; /* Environment pointer */\r
++#endif\r
+ \r
++ if (BootFile[0] == '\0') {\r
+ sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",\r
+- OurIP & 0xFF,\r
+- (OurIP >> 8) & 0xFF,\r
+- (OurIP >> 16) & 0xFF,\r
+- (OurIP >> 24) & 0xFF );\r
++ NetOurIP & 0xFF,\r
++ (NetOurIP >> 8) & 0xFF,\r
++ (NetOurIP >> 16) & 0xFF,\r
++ (NetOurIP >> 24) & 0xFF );\r
+ tftp_filename = default_filename;\r
+ \r
+ printf ("*** Warning: no boot file name; using '%s'\n",\r
+@@ -354,7 +368,16 @@\r
+ TftpServerPort = WELL_KNOWN_PORT;\r
+ TftpTimeoutCount = 0;\r
+ TftpState = STATE_RRQ;\r
++ /* Use a pseudo-random port unless a specific port is set */\r
+ TftpOurPort = 1024 + (get_timer(0) % 3072);\r
++#ifdef CONFIG_TFTP_PORT\r
++ if ((ep = getenv("tftpdstp")) != NULL) {\r
++ TftpServerPort = simple_strtol(ep, NULL, 10);\r
++ }\r
++ if ((ep = getenv("tftpsrcp")) != NULL) {\r
++ TftpOurPort= simple_strtol(ep, NULL, 10);\r
++ }\r
++#endif\r
+ TftpBlock = 0;\r
+ \r
+ /* zero out server ether in case the server ip has changed */\r
+diff -uNr u-boot-1.1.2/board/emetec405/flash.c new-uboot-1.1.2/board/emetec405/flash.c\r
+--- u-boot-1.1.2/board/emetec405/flash.c 2007-04-20 00:40:26.000000000 +0300\r
++++ new-uboot-1.1.2/board/emetec405/flash.c 2007-04-20 00:41:11.000000000 +0300\r
+@@ -31,6 +31,7 @@\r
+ */\r
+ static ulong flash_get_size (vu_long * addr, flash_info_t * info);\r
+ static void flash_get_offsets (ulong base, flash_info_t * info);\r
++static int write_word (flash_info_t *info, ulong dest, ulong data);\r
+ \r
+ /*-----------------------------------------------------------------------\r
+ */\r
git.openpandora.org / openembedded.git / commitdiff