select ARM_AMBA
select ARM_VIC
select GENERIC_GPIO
++ ++++++++++ select HAVE_GPIO_LIB
help
This enables support for the Cirrus EP93xx series of CPUs.
help
Support for Freescale MXC/iMX-based family of processors
-------- ----config ARCH_ORION
++++++++ ++++config ARCH_ORION5X
bool "Marvell Orion"
depends on MMU
select PCI
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
++++++++ ++++ select PLAT_ORION
help
-------- ---- Support for Marvell Orion System on Chip family.
++++++++ ++++ Support for the following Marvell Orion 5x series SoCs:
++++++++ ++++ Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
bool "SA1100-based"
select ISA
select ARCH_DISCONTIGMEM_ENABLE
++++++++++++ select ARCH_SPARSEMEM_ENABLE
++++++++++++ select ARCH_SELECT_MEMORY_MODEL
select ARCH_MTD_XIP
select GENERIC_GPIO
select GENERIC_TIME
++++++++++ ++ select GENERIC_CLOCKEVENTS
++++++++++ ++ select TICK_ONESHOT
select HAVE_IDE
++++++++++ ++ select HAVE_GPIO_LIB
help
Support for StrongARM 11x0 based boards.
source "arch/arm/mach-omap2/Kconfig"
-------- ----source "arch/arm/mach-orion/Kconfig"
++++++++ ++++source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
config PLAT_IOP
bool
++++++++ ++++config PLAT_ORION
++++++++ ++++ bool
++++++++ ++++
source arch/arm/mm/Kconfig
config IWMMXT
config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
------------ depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
++++++++++++ depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
config LOCAL_TIMERS
bool "Use local timer interrupts"
------------ depends on SMP && REALVIEW_EB_ARM11MP
++++++++++++ depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
default y
help
Enable support for local timers on SMP platforms, rather then the
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
++++++++++++ config ARCH_SPARSEMEM_ENABLE
++++++++++++ bool
++++++++++++
++++++++++++ config ARCH_SELECT_MEMORY_MODEL
++++++++++++ bool
++++++++++++
config NODES_SHIFT
int
default "4" if ARCH_LH7A40X
@ The abort handler must return the aborted address in r0, and
@ the fault status register in r1. r9 must be preserved.
@
------------#ifdef MULTI_ABORT
++++++++++++#ifdef MULTI_DABORT
ldr r4, .LCprocfns
mov lr, pc
------------ ldr pc, [r4]
++++++++++++ ldr pc, [r4, #PROCESSOR_DABT_FUNC]
#else
------------ bl CPU_ABORT_HANDLER
++++++++++++ bl CPU_DABORT_HANDLER
#endif
@
irq_handler
#ifdef CONFIG_PREEMPT
+++++ +++++++ str r8, [tsk, #TI_PREEMPT] @ restore preempt count
ldr r0, [tsk, #TI_FLAGS] @ get flags
+++++ +++++++ teq r8, #0 @ if preempt count != 0
+++++ +++++++ movne r0, #0 @ force flags to 0
tst r0, #_TIF_NEED_RESCHED
blne svc_preempt
----- -------preempt_return:
----- ------- ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
----- ------- str r8, [tsk, #TI_PREEMPT] @ restore preempt count
----- ------- teq r0, r7
----- ------- strne r0, [r0, -r0] @ bug()
#endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr_cxsf, r0
#ifdef CONFIG_PREEMPT
svc_preempt:
----- ------- teq r8, #0 @ was preempt count = 0
----- ------- ldreq r6, .LCirq_stat
----- ------- movne pc, lr @ no
----- ------- ldr r0, [r6, #4] @ local_irq_count
----- ------- ldr r1, [r6, #8] @ local_bh_count
----- ------- adds r0, r0, r1
----- ------- movne pc, lr
----- ------- mov r7, #0 @ preempt_schedule_irq
----- ------- str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
+++++ +++++++ mov r8, lr
1: bl preempt_schedule_irq @ irq en/disable is done inside
ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
tst r0, #_TIF_NEED_RESCHED
----- ------- beq preempt_return @ go again
+++++ +++++++ moveq pc, r8 @ go again
b 1b
#endif
mrs r9, cpsr
tst r3, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT
------------ msr cpsr_c, r9
@
@ set args, then call main handler
@ r0 - address of faulting instruction
@ r1 - pointer to registers on stack
@
------------ mov r0, r2 @ address (pc)
++++++++++++#ifdef MULTI_PABORT
++++++++++++ mov r0, r2 @ pass address of aborted instruction.
++++++++++++ ldr r4, .LCprocfns
++++++++++++ mov lr, pc
++++++++++++ ldr pc, [r4, #PROCESSOR_PABT_FUNC]
++++++++++++#else
++++++++++++ CPU_PABORT_HANDLER(r0, r2)
++++++++++++#endif
++++++++++++ msr cpsr_c, r9 @ Maybe enable interrupts
mov r1, sp @ regs
bl do_PrefetchAbort @ call abort handler
.align 5
.LCcralign:
.word cr_alignment
------------#ifdef MULTI_ABORT
++++++++++++#ifdef MULTI_DABORT
.LCprocfns:
.word processor
#endif
.LCfp:
.word fp_enter
----- -------#ifdef CONFIG_PREEMPT
----- -------.LCirq_stat:
----- ------- .word irq_stat
----- -------#endif
/*
* User mode handlers
@ The abort handler must return the aborted address in r0, and
@ the fault status register in r1.
@
------------#ifdef MULTI_ABORT
++++++++++++#ifdef MULTI_DABORT
ldr r4, .LCprocfns
mov lr, pc
------------ ldr pc, [r4]
++++++++++++ ldr pc, [r4, #PROCESSOR_DABT_FUNC]
#else
------------ bl CPU_ABORT_HANDLER
++++++++++++ bl CPU_DABORT_HANDLER
#endif
@
__und_usr:
usr_entry
------------ tst r3, #PSR_T_BIT @ Thumb mode?
------------ bne __und_usr_unknown @ ignore FP
------------ sub r4, r2, #4
------------
@
@ fall through to the emulation code, which returns using r9 if
@ it has emulated the instruction, or the more conventional lr
@
adr r9, ret_from_exception
adr lr, __und_usr_unknown
------------1: ldrt r0, [r4]
++++++++++++ tst r3, #PSR_T_BIT @ Thumb mode?
++++++++++++ subeq r4, r2, #4 @ ARM instr at LR - 4
++++++++++++ subne r4, r2, #2 @ Thumb instr at LR - 2
++++++++++++1: ldreqt r0, [r4]
++++++++++++ beq call_fpe
++++++++++++ @ Thumb instruction
++++++++++++#if __LINUX_ARM_ARCH__ >= 7
++++++++++++2: ldrht r5, [r4], #2
++++++++++++ and r0, r5, #0xf800 @ mask bits 111x x... .... ....
++++++++++++ cmp r0, #0xe800 @ 32bit instruction if xx != 0
++++++++++++ blo __und_usr_unknown
++++++++++++3: ldrht r0, [r4]
++++++++++++ add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
++++++++++++ orr r0, r0, r5, lsl #16
++++++++++++#else
++++++++++++ b __und_usr_unknown
++++++++++++#endif
++++++++++++
@
@ fallthrough to call_fpe
@
* The out of line fixup for the ldrt above.
*/
.section .fixup, "ax"
------------2: mov pc, r9
++++++++++++4: mov pc, r9
.previous
.section __ex_table,"a"
------------ .long 1b, 2b
++++++++++++ .long 1b, 4b
++++++++++++#if __LINUX_ARM_ARCH__ >= 7
++++++++++++ .long 2b, 4b
++++++++++++ .long 3b, 4b
++++++++++++#endif
.previous
/*
* r10 = this threads thread_info structure.
* lr = unrecognised instruction return address
*/
++++++++++++ @
++++++++++++ @ Fall-through from Thumb-2 __und_usr
++++++++++++ @
++++++++++++#ifdef CONFIG_NEON
++++++++++++ adr r6, .LCneon_thumb_opcodes
++++++++++++ b 2f
++++++++++++#endif
call_fpe:
#ifdef CONFIG_NEON
------------ adr r6, .LCneon_opcodes
++++++++++++ adr r6, .LCneon_arm_opcodes
2:
ldr r7, [r6], #4 @ mask value
cmp r7, #0 @ end mask?
1:
#endif
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
++++++++++++ tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
and r8, r0, #0x0f000000 @ mask out op-code bits
teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
#ifdef CONFIG_NEON
.align 6
------------.LCneon_opcodes:
++++++++++++.LCneon_arm_opcodes:
.word 0xfe000000 @ mask
.word 0xf2000000 @ opcode
.word 0xff100000 @ mask
.word 0xf4000000 @ opcode
++++++++++++ .word 0x00000000 @ mask
++++++++++++ .word 0x00000000 @ opcode
++++++++++++
++++++++++++.LCneon_thumb_opcodes:
++++++++++++ .word 0xef000000 @ mask
++++++++++++ .word 0xef000000 @ opcode
++++++++++++
++++++++++++ .word 0xff100000 @ mask
++++++++++++ .word 0xf9000000 @ opcode
++++++++++++
.word 0x00000000 @ mask
.word 0x00000000 @ opcode
#endif
__pabt_usr:
usr_entry
++++++++++++#ifdef MULTI_PABORT
++++++++++++ mov r0, r2 @ pass address of aborted instruction.
++++++++++++ ldr r4, .LCprocfns
++++++++++++ mov lr, pc
++++++++++++ ldr pc, [r4, #PROCESSOR_PABT_FUNC]
++++++++++++#else
++++++++++++ CPU_PABORT_HANDLER(r0, r2)
++++++++++++#endif
enable_irq @ Enable interrupts
------------ mov r0, r2 @ address (pc)
mov r1, sp @ regs
bl do_PrefetchAbort @ call abort handler
/* fall through */
select CPU_CP15_MMU
select CPU_COPY_V3 if MMU
select CPU_TLB_V3 if MMU
++++++++++++ select CPU_PABRT_NOIFAR
help
The ARM610 is the successor to the ARM3 processor
and was produced by VLSI Technology Inc.
select CPU_CP15_MMU
select CPU_COPY_V3 if MMU
select CPU_TLB_V3 if MMU
++++++++++++ select CPU_PABRT_NOIFAR
help
A 32-bit RISC microprocessor based on the ARM7 processor core
designed by Advanced RISC Machines Ltd. The ARM710 is the
default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
select CPU_32v4T
select CPU_ABRT_LV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
select CPU_32v4T
select CPU_ABRT_EV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if ARCH_LH7A40X || ARCH_KS8695
select CPU_32v4T
select CPU_ABRT_EV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if ARCH_OMAP15XX
select CPU_32v4T
select CPU_ABRT_EV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
select CPU_32v5
select CPU_ABRT_EV5TJ
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU # can probably do better
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU # can probably do better
select CPU_32v3 if ARCH_RPC
select CPU_32v4 if !ARCH_RPC
select CPU_ABRT_EV4
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y
select CPU_32v4
select CPU_ABRT_EV4
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y
select CPU_32v5
select CPU_ABRT_EV5T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_TLB_V4WBI if MMU
# Feroceon
config CPU_FEROCEON
bool
-------- ---- depends on ARCH_ORION
++++++++ ++++ depends on ARCH_ORION5X
default y
select CPU_32v5
select CPU_ABRT_EV5T
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"
------------ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
++++++++++++ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
default y if ARCH_MX3
default y if ARCH_MSM7X00A
select CPU_32v6
select CPU_ABRT_EV6
++++++++++++ select CPU_PABRT_NOIFAR
select CPU_CACHE_V6
select CPU_CACHE_VIPT
select CPU_CP15_MMU
# ARMv7
config CPU_V7
bool "Support ARM V7 processor"
------------ depends on ARCH_INTEGRATOR
++++++++++++ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
select CPU_32v6K
select CPU_32v7
select CPU_ABRT_EV7
++++++++++++ select CPU_PABRT_IFAR
select CPU_CACHE_V7
select CPU_CACHE_VIPT
select CPU_CP15_MMU
config CPU_ABRT_EV7
bool
++++++++++++config CPU_PABRT_IFAR
++++++++++++ bool
++++++++++++
++++++++++++config CPU_PABRT_NOIFAR
++++++++++++ bool
++++++++++++
# The cache model
config CPU_CACHE_V3
bool
If you don't know what this all is, saying Y is a safe choice.
++++++++++++config ARM_THUMBEE
++++++++++++ bool "Enable ThumbEE CPU extension"
++++++++++++ depends on CPU_V7
++++++++++++ help
++++++++++++ Say Y here if you have a CPU with the ThumbEE extension and code to
++++++++++++ make use of it. Say N for code that can run on CPUs without ThumbEE.
++++++++++++
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on ARCH_SUPPORTS_BIG_ENDIAN
default n
config CACHE_L2X0
------------ bool
++++++++++++ bool "Enable the L2x0 outer cache controller"
++++++++++++ depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
++++++++++++ default y
select OUTER_CACHE
++++++++++++ help
++++++++++++ This option enables the L2x0 PrimeCell.
git.openpandora.org / pandora-kernel.git / commitdiff