- BUILD_DIR=build
- HOSTCC="cc"
- HOSTCXX="c++"
+ - QEMU_VERSION="v3.1.0"
before_script:
# install toolchains based on TOOLCHAIN} variable
wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
fi
+ - if [[ "${TOOLCHAIN}" == "nds32" ]]; then
+ wget https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz &&
+ tar -C /tmp -xf nds32le-linux-glibc-v3-upstream.tar.gz &&
+ echo -e "\n[toolchain-prefix]\nnds32 = /tmp/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman;
+ fi
- if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
tar -C /tmp -xf x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
git clone git://git.qemu.org/qemu.git /tmp/qemu;
pushd /tmp/qemu;
git submodule update --init dtc &&
- git checkout v3.0.0 &&
+ git checkout ${QEMU_VERSION} &&
./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
make -j4 all install;
popd;
- name: "buildman arm11 arm7 arm920t arm946es"
env:
- BUILDMAN="arm11 arm7 arm920t arm946es"
- - name: "buildman arm926ejs (non-freescale,siemens,atmel,kirkwood,spear)"
+ - name: "buildman arm926ejs (non-NXP,siemens,atmel,kirkwood,spear)"
env:
- JOB="arm926ejs"
BUILDMAN="arm926ejs -x freescale,siemens,atmel,kirkwood,spear"
- name: "buildman boundary engicam toradex"
env:
- BUILDMAN="boundary engicam toradex"
- - name: "buildman Freescale ARM32"
+ - name: "buildman NXP ARM32"
env:
- BUILDMAN="freescale -x powerpc,m68k,aarch64"
- - name: "buildman Freescale AArch64 LS10xx"
+ - name: "buildman NXP AArch64 LS101x"
+ env:
+ - BUILDMAN="freescale&aarch64&ls101"
+ - name: "buildman NXP AArch64 LS104x"
env:
- - BUILDMAN="freescale&aarch64&&ls1"
- - name: "buildman Freescale AArch64 LS20xx"
+ - BUILDMAN="freescale&aarch64&ls104"
+ - name: "buildman NXP AArch64 LS108x"
env:
- - BUILDMAN="freescale&aarch64&&ls2"
- - name: "buildman i.MX6 (non-Freescale)"
+ - BUILDMAN="freescale&aarch64&ls108"
+ - name: "buildman NXP AArch64 LS20xx"
+ env:
+ - BUILDMAN="freescale&aarch64&&ls20"
+ - name: "buildman i.MX6 (non-NXP)"
env:
- BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
- - name: "buildman i.MX (non-Freescale,i.MX6,toradex)"
+ - name: "buildman i.MX (non-NXP,i.MX6,toradex)"
env:
- BUILDMAN="mx -x freescale,mx6,toradex"
- name: "buildman k2"
env:
- BUILDMAN="riscv"
TOOLCHAIN="riscv"
+ - name: "buildman nds32"
+ env:
+ - BUILDMAN="nds32"
+ TOOLCHAIN="nds32"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
- TEST_PY_BD="vexpress_ca15_tc2"
TEST_PY_ID="--id qemu"
QEMU_TARGET="arm-softmmu"
+ QEMU_VERSION="v3.0.0"
BUILDMAN="^vexpress_ca15_tc2$"
- name: "test/py vexpress_ca9x4"
env:
QEMU_TARGET="arm-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^zynq_zc702$"
+ - name: "test/py xilinx_versal_virt"
+ env:
+ - TEST_PY_BD="xilinx_versal_virt"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="aarch64-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^xilinx_versal_virt$"
- name: "test/py xtfpga"
env:
- TEST_PY_BD="xtfpga"
help
Say Y here to support 64bit physical memory address.
This can be used not only for 64bit SoCs, but also for
- large physical address extention on 32bit SoCs.
+ large physical address extension on 32bit SoCs.
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
F: drivers/mmc/bcmstb_sdhci.c
F: drivers/spi/bcmstb_spi.c
+ARM/CZ.NIC TURRIS MOX SUPPORT
+M: Marek Behun <marek.behun@nic.cz>
+S: Maintained
+F: arch/arm/dts/armada-3720-turris-mox.dts
+F: board/CZ.NIC/
+F: configs/turris_*_defconfig
+F: include/configs/turris_*.h
+
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <fabio.estevam@nxp.com>
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
T: git git://git.denx.de/u-boot-microblaze.git
-F: arch/arm/cpu/armv8/zynqmp/
+F: arch/arm/mach-zynqmp/
F: drivers/clk/clk_zynqmp.c
F: drivers/fpga/zynqpl.c
F: drivers/gpio/zynq_gpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
+F: drivers/net/ocelot_switch.c
MIPS JZ4780
M: Ezequiel Garcia <ezequiel@collabora.com>
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_mkfitimage = MKIMAGE $@
-cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@\
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_cat = CAT $@
forwarded through a router.
(Environment variable "netmask")
-- Multicast TFTP Mode:
- CONFIG_MCAST_TFTP
-
- Defines whether you want to support multicast TFTP as per
- rfc-2090; for example to work with atftp. Lets lots of targets
- tftp down the same boot image concurrently. Note: the Ethernet
- driver in use must provide a function: mcast() to join/leave a
- multicast group.
-
- BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY
config TARGET_AXS101
bool "Support Synopsys Designware SDP board AXS101"
+ select BOUNCE_BUFFER if CMD_NAND
config TARGET_AXS103
bool "Support Synopsys Designware SDP board AXS103"
+ select BOUNCE_BUFFER if CMD_NAND
config TARGET_EMSDP
bool "Synopsys EM Software Development Platform"
select ARM64
select CLK
select DM
+ select DM_ETH if NET
+ select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
select CLK
select CPU_V7R
select DM
+ select DM_ETH if NET
+ select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
imply CMD_DM
select ARM64
select CLK
select DM
+ select DM_ETH if NET
+ select DM_MMC if MMC
select DM_SERIAL
+ select DM_SPI if SPI
+ select DM_SPI_FLASH if DM_SPI
select DM_USB if USB
select OF_CONTROL
select SPL_BOARD_INIT if SPL
source "arch/arm/mach-zynq/Kconfig"
+source "arch/arm/mach-zynqmp/Kconfig"
+
source "arch/arm/mach-versal/Kconfig"
source "arch/arm/mach-zynqmp-r5/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
-source "arch/arm/cpu/armv8/zynqmp/Kconfig"
-
source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/mach-imx/Kconfig"
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
+machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_S32V234) += s32v234/
-obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
+ select ARM_ERRATA_855873 if !TFABOOT
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
- select SYS_FSL_ERRATUM_A009803
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_A010165
- select SYS_FSL_ERRATUM_A008511
- select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+ select SYS_FSL_ERRATUM_A010165 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
- select SYS_FSL_ERRATUM_A008336
- select SYS_FSL_ERRATUM_A008511
- select SYS_FSL_ERRATUM_A008514
+ select SYS_FSL_ERRATUM_A008336 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008514 if !TFABOOT
select SYS_FSL_ERRATUM_A008585
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009635
- select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
- select SYS_FSL_ERRATUM_A009803
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+ select SYS_FSL_ERRATUM_A010165 if !TFABOOT
select SYS_FSL_ERRATUM_A009203
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
break;
case RCW_SRC_EMMC_VAL:
/* RCW SRC EMMC */
- src = BOOT_SOURCE_SD_MMC2;
+ src = BOOT_SOURCE_SD_MMC;
break;
case RCW_SRC_I2C1_VAL:
/* RCW SRC I2C1 Extended */
memcpy((char *)tmp, p, len);
val = fdt32_to_cpu(tmp[0][6]);
- if (rev > REV1_0) {
+ if (rev == REV1_0) {
tmp[1][6] = cpu_to_fdt32(val + 1);
tmp[2][6] = cpu_to_fdt32(val + 2);
tmp[3][6] = cpu_to_fdt32(val + 3);
#endif
#ifdef CONFIG_TFABOOT
-#define MAX_BOOTCMD_SIZE 256
+#define MAX_BOOTCMD_SIZE 512
int fsl_setenv_bootcmd(void)
{
fsl_setenv_bootcmd();
fsl_setenv_mcinitcmd();
}
+
+ /*
+ * If the boot mode is secure, default environment is not present then
+ * setenv command needs to be run by default
+ */
+#ifdef CONFIG_CHAIN_OF_TRUST
+ if ((fsl_check_boot_mode_secure() == 1)) {
+ fsl_setenv_bootcmd();
+ fsl_setenv_mcinitcmd();
+ }
+#endif
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
armada-xp-theadorable.dtb \
- armada-38x-controlcenterdc.dtb
+ armada-38x-controlcenterdc.dtb \
+ armada-385-atl-x530.dtb \
+ armada-385-atl-x530DP.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
-// SPDX-License-Identifier: GPL-2.0+
/*
* pdu001.dts
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/ {
model = "EETS,PDU001";
- compatible = "eets,pdu001", "ti,am33xx";
+ compatible = "ti,am33xx";
chosen {
stdout-path = &uart3;
clock-frequency = <100000>;
board_24aa025e48: board_24aa025e48@50 {
- compatible = "microchip,24aa025e48";
+ compatible = "atmel,24c02";
reg = <0x50>;
};
backplane_24aa025e48: backplane_24aa025e48@53 {
- compatible = "microchip,24aa025e48";
+ compatible = "atmel,24c02";
reg = <0x53>;
};
ti,pindir-d0-out-d1-in;
status = "okay";
- cfaf240320a032t {
- compatible = "orise,otm3225a";
+ display-controller@0 {
+ compatible = "orisetech,otm3225a";
reg = <0>;
spi-max-frequency = <1000000>;
// SPI mode 3
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
};
&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <0>;
+ phy-handle = <ðphy0>;
phy-mode = "mii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <1>;
+ phy-handle = <ðphy1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};
aliases {
ethernet0 = ð0;
+ ethernet1 = ð1;
i2c0 = &i2c0;
spi0 = &spi0;
};
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ startup-delay-us = <2000000>;
shutdown-delay-us = <1000000>;
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
eth_phy1: ethernet-phy@1 {
reg = <1>;
};
phy1 {
phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-speed = <PHY_SPEED_5G>;
};
phy2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
+
+ rtc@6f {
+ compatible = "microchip,mcp7941x";
+ reg = <0x6f>;
+ };
};
&sdhci1 {
spi-max-frequency = <20000000>;
m25p,fast-read;
};
+
+ moxtet@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cznic,moxtet";
+ reg = <1>;
+ reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ spi-cpha;
+ };
};
&uart0 {
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
};
};
- pcie-controller {
+ pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+&spi1 {
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "armada-385-atl-x530.dtsi"
+#include "armada-385-atl-x530-u-boot.dtsi"
+
+/ {
+ model = "Allied Telesis x530";
+ compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
+
+ nand-protect {
+ compatible = "atl,nand-protect";
+ protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb-enable {
+ compatible = "atl,usb-enable";
+ enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ boot-board {
+ compatible = "atl,boot-board";
+ present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ phy-reset {
+ compatible = "atl,phy-reset";
+ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
+ <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-enable {
+ compatible = "atl,led-enable";
+ enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_7seg {
+ compatible = "atl,of-led-7seg";
+ segment-gpios = <
+ &led_7seg_gpio 0 0
+ &led_7seg_gpio 1 0
+ &led_7seg_gpio 2 0
+ &led_7seg_gpio 3 0
+ &led_7seg_gpio 4 0
+ &led_7seg_gpio 5 0
+ &led_7seg_gpio 6 0
+ &led_7seg_gpio 7 0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-385.dtsi"
+
+/ {
+ model = "Allied Telesis x530";
+ compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi1 = &spi1;
+ i2c0 = &i2c0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+ pcie-mem-aperture = <0xa0000000 0x40000000>;
+ };
+
+ eco-button-interrupt {
+ compatible = "atl,eco-button-interrupt";
+ eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ board-reset {
+ compatible = "atl,phy_reset";
+ /* Physical board layout of reset pin is active-low but for the
+ * current driver we have to set it to active-high here.
+ */
+ phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
+ <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ phy-int {
+ compatible = "linux,uio-pdrv-genirq";
+ interrupt-parent = <&gpio0>;
+ interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
+ };
+
+ led-enable {
+ compatible = "atl,led-enable";
+ led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ };
+
+ led_7seg {
+ compatible = "atl,of-led-7seg";
+ segment-gpios = <
+ &led_7seg_gpio 0 0
+ &led_7seg_gpio 1 0
+ &led_7seg_gpio 2 0
+ &led_7seg_gpio 3 0
+ &led_7seg_gpio 4 0
+ &led_7seg_gpio 5 0
+ &led_7seg_gpio 6 0
+ &led_7seg_gpio 7 0>;
+ };
+
+ poe {
+ compatible = "atl,periph-poe";
+ poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&devbus_cs1 {
+ compatible = "marvell,mvebu-devbus";
+ status = "okay";
+
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ nvs@0 {
+ status = "okay";
+
+ compatible = "mtd-ram";
+ reg = <0 0x00080000>;
+ bank-width = <1>;
+ label = "nvs";
+ };
+};
+
+&gpio0 {
+ poe-disable {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "poe-disable";
+ };
+};
+
+&gpio1 {
+ poe-mezz-reset {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "poe-mezz-reset";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ mux@71 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,pca9544";
+ reg = <0x71>;
+ i2c-mux-idle-disconnect;
+
+ i2c@0 { /* POE devices MUX */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ rng@3b {
+ compatible = "maxim,ds2476";
+ reg = <0x3b>;
+ };
+
+ hwmon@2e {
+ compatible = "adi,adt7476";
+ reg = <0x2e>;
+ };
+
+ hwmon@2d {
+ compatible = "adi,adt7476";
+ reg = <0x2d>;
+ };
+
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ rtc@68 {
+ compatible = "dallas,ds1340";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ led_7seg_gpio: gpio@20 {
+ compatible = "nxp,pca9554";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+
+ sfpgpio: gpio@27 { /* I2C to GPIO */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x27>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sfpmux: mux@77 { /* SFP I2C MUX */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,pca9544";
+ reg = <0x77>;
+ i2c-mux-idle-disconnect;
+ };
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00140000 0x00e80000>;
+ label = "unused";
+ };
+ partition@idprom {
+ reg = <0x00fc0000 0x00040000>;
+ label = "idprom";
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <25000000>;
+};
+
+&nand_controller { /* 256 MB */
+ status = "okay";
+ num-cs = <1>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "armada-385-atl-x530.dtsi"
+#include "armada-385-atl-x530-u-boot.dtsi"
+#include "armada-385-atl-x530DP.dtsi"
+
+/ {
+ model = "Allied Telesis x530DP";
+ compatible = "alliedtelesis,x530DP", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
+
+ nand-protect {
+ compatible = "atl,nand-protect";
+ protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb-enable {
+ compatible = "atl,usb-enable";
+ enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ boot-board {
+ compatible = "atl,boot-board";
+ present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ phy-reset {
+ compatible = "atl,phy-reset";
+ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
+ <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-enable {
+ compatible = "atl,led-enable";
+ enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_7seg {
+ compatible = "atl,of-led-7seg";
+ segment-gpios = <
+ &led_7seg_gpio 0 0
+ &led_7seg_gpio 1 0
+ &led_7seg_gpio 2 0
+ &led_7seg_gpio 3 0
+ &led_7seg_gpio 4 0
+ &led_7seg_gpio 5 0
+ &led_7seg_gpio 6 0
+ &led_7seg_gpio 7 0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+&i2c0 {
+ mux@71 {
+ compatible = "nxp,pca9548";
+
+ i2c@1 {
+ hwmon@2c {
+ compatible = "ti,lm87";
+ reg = <0x2c>;
+ };
+
+ hwmon@2d {
+ compatible = "ti,lm87";
+ reg = <0x2d>;
+ };
+
+ hwmon@2e {
+ pwm-polarity = <1>;
+ };
+ };
+
+ psu_a_adapter: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ psu_b_adapter: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ misc_gpio: gpio@26 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x26>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ psu_bank2 {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "psu-bank2";
+ };
+ };
+ };
+ };
+};
+
+/ {
+ psu_slot_a {
+ compatible = "atl,dts-overlay-gpio-psu-slot";
+ slot-name = "PSU Bay A";
+ board-index = <1>;
+ present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>;
+ output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&misc_gpio>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
+ overlay = <&psu_a_overlay>;
+ };
+
+ psu_slot_b {
+ compatible = "atl,dts-overlay-gpio-psu-slot";
+ slot-name = "PSU Bay B";
+ board-index = <2>;
+ present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>;
+ output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&misc_gpio>;
+ interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
+ overlay = <&psu_b_overlay>;
+ };
+
+ fan_slot_a {
+ compatible = "atl,fan05-slot";
+ slot-name = "Fan Bay A";
+ board-index = <3>;
+ present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>;
+ fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&misc_gpio>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ overlay = <&fan_a_overlay>;
+ };
+};
+
+/ {
+ psu_a_overlay: psu_a {
+ fragment@0 {
+ target = <&psu_a_adapter>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ psu@51 {
+ compatible = "atl,atl-pwr-gen2";
+ reg = <0x51>;
+ board-index = <1>;
+ };
+ };
+ };
+ };
+};
+
+/ {
+ psu_b_overlay: psu_b {
+ fragment@0 {
+ target = <&psu_b_adapter>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ psu@51 {
+ compatible = "atl,atl-pwr-gen2";
+ reg = <0x51>;
+ board-index = <2>;
+ };
+ };
+ };
+ };
+};
+
+/ {
+ fan_a_overlay:fan_a {
+ fragment@1 {
+ target-path = "/";
+ __overlay__ {
+ fan@1 {
+ compatible = "atl,fan05";
+ board-index = <3>;
+ module-id-gpios =
+ <&misc_gpio 4 GPIO_ACTIVE_HIGH>,
+ <&misc_gpio 5 GPIO_ACTIVE_HIGH>,
+ <&misc_gpio 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+ };
+};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
};
soc {
- internal-regs {
- pinctrl@18000 {
- compatible = "marvell,mv88f6820-pinctrl";
- };
- };
-
- pcie-controller {
+ pciec: pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
* configured in x4 by the bootloader, then
* pcie@4,0 is not available.
*/
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
};
/* x1 port */
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
};
/* x1 port */
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
* x1 port only available when pcie@1,0 is
* configured as a x1 port
*/
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
};
};
};
+
+&pinctrl {
+ compatible = "marvell,mv88f6820-pinctrl";
+};
status = "okay";
};
- spi1: spi@10680 {
- /*
- * CS0: W25Q32
- * CS1:
- * CS2: mikrobus
- */
- pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- usb0: usb3@f8000 {
+ usb3@f8000 {
/* CON7, USB-A port on back of device */
status = "okay";
};
};
};
+&spi1 {
+ /*
+ * Add SPI CS pins for clearfog:
+ * CS0: W25Q32
+ * CS1:
+ * CS2: mikrobus
+ */
+ pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
/*
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
MPP18: gpio ? (pca9655 int?)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 388 SoC.
*
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- *
* The main difference with the Armada 385 is that the 388 can handle two more
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
* property and the name of the SoC, and add the second SATA host which control
model = "Marvell Armada 388 family SoC";
compatible = "marvell,armada388", "marvell,armada385",
"marvell,armada380";
-
soc {
internal-regs {
- pinctrl@18000 {
- compatible = "marvell,mv88f6828-pinctrl";
- };
-
sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
};
};
};
+
+&pinctrl {
+ compatible = "marvell,mv88f6828-pinctrl";
+};
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
- spi0: spi@10600 {
- status = "okay";
- sc16is741: sc16is741@0 {
- compatible = "nxp,sc16is741";
- reg = <0>;
- clocks = <&sc16isclk>;
- spi-max-frequency = <4000000>;
- interrupt-parent = <&gpio0>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
- spi1: spi@10680 {
- status = "okay";
- u-boot,dm-pre-reloc;
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q016a", "spi-flash";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
- };
- spi-flash@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a11", "spi-flash";
- reg = <1>; /* Chip select 1 */
- spi-max-frequency = <108000000>;
- u-boot,dm-pre-reloc;
- };
- };
-
I2C0: i2c@11000 {
status = "okay";
clock-frequency = <1000000>;
};
};
};
+
+&spi0 {
+ status = "okay";
+ sc16is741: sc16is741@0 {
+ compatible = "nxp,sc16is741";
+ reg = <0>;
+ clocks = <&sc16isclk>;
+ spi-max-frequency = <4000000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q016a", "spi-flash";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+ spi-flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "spi-flash";
+ reg = <1>; /* Chip select 1 */
+ spi-max-frequency = <108000000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
- devbus-bootcs {
+ devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
status = "disabled";
};
- devbus-cs0 {
+ devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
status = "disabled";
};
- devbus-cs1 {
+ devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
status = "disabled";
};
- devbus-cs2 {
+ devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
status = "disabled";
};
- devbus-cs3 {
+ devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <0>;
+ arm,double-linefill = <0>;
+ prefetch-data = <1>;
};
scu@c000 {
reg = <0xc000 0x58>;
};
+ timer@c200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xc200 0x20>;
+ interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+ clocks = <&coreclk 2>;
+ };
+
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
<0xc100 0x100>;
};
- spi0: spi@10600 {
- compatible = "marvell,armada-380-spi",
- "marvell,orion-spi";
- reg = <0x10600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- spi1: spi@10680 {
- compatible = "marvell,armada-380-spi",
- "marvell,orion-spi";
- reg = <0x10680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
i2c0: i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
+ compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@11100 {
- compatible = "marvell,mv64xxx-i2c";
+ compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
marvell,function = "i2c0";
};
- nand_pins: nand-pins {
- marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
- "mpp38", "mpp28", "mpp40", "mpp42",
- "mpp35", "mpp36", "mpp25", "mpp30",
- "mpp32";
- marvell,function = "dev";
- };
-
- nand_rb: nand-rb {
- marvell,pins = "mpp41";
- marvell,function = "nand";
- };
-
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
marvell,function = "spi1";
};
+ nand_pins: nand-pins {
+ marvell,pins = "mpp22", "mpp34", "mpp23",
+ "mpp33", "mpp38", "mpp28",
+ "mpp40", "mpp42", "mpp35",
+ "mpp36", "mpp25", "mpp30",
+ "mpp32";
+ marvell,function = "dev";
+ };
+
+ nand_rb: nand-rb {
+ marvell,pins = "mpp41";
+ marvell,function = "nand";
+ };
+
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";
};
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
- reg = <0x20000 0x100>, <0x20180 0x20>;
+ reg = <0x20000 0x100>, <0x20180 0x20>,
+ <0x20250 0x8>;
};
mpic: interrupt-controller@20a00 {
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
- timer@20300 {
+ timer: timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
clock-names = "nbclk", "fixed";
};
- watchdog@20300 {
+ watchdog: watchdog@20300 {
compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
- cpurst@20800 {
+ cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
reg = <0x20d20 0x6c>;
};
- coherency-fabric@21010 {
+ coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
};
- pmsu@22000 {
+ pmsu: pmsu@22000 {
compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>;
};
+ /*
+ * As a special exception to the "order by
+ * register address" rule, the eth0 node is
+ * placed here to ensure that it gets
+ * registered as the first interface, since
+ * the network subsystem doesn't allow naming
+ * interfaces using DT aliases. Without this,
+ * the ordering of interfaces is different
+ * from the one used in U-Boot and the
+ * labeling of interfaces on the boards, which
+ * is very confusing for users.
+ */
+ eth0: ethernet@70000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0x70000 0x4000>;
+ interrupts-extended = <&mpic 8>;
+ clocks = <&gateclk 4>;
+ tx-csum-limit = <9800>;
+ status = "disabled";
+ };
+
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
status = "disabled";
};
- usb@58000 {
+ usb0: usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- xor@60800 {
- compatible = "marvell,orion-xor";
+ xor0: xor@60800 {
+ compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
};
};
- xor@60900 {
- compatible = "marvell,orion-xor";
+ xor1: xor@60900 {
+ compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
};
};
- eth0: ethernet@70000 {
- compatible = "marvell,armada-370-neta";
- reg = <0x70000 0x4000>;
- interrupts-extended = <&mpic 8>;
- clocks = <&gateclk 4>;
- status = "disabled";
- };
-
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gateclk 4>;
};
- rtc@a3800 {
+ cesa: crypto@90000 {
+ compatible = "marvell,armada-38x-crypto";
+ reg = <0x90000 0x10000>;
+ reg-names = "regs";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 23>, <&gateclk 21>,
+ <&gateclk 14>, <&gateclk 16>;
+ clock-names = "cesa0", "cesa1",
+ "cesaz0", "cesaz1";
+ marvell,crypto-srams = <&crypto_sram0>,
+ <&crypto_sram1>;
+ marvell,crypto-sram-size = <0x800>;
+ };
+
+ rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
- sata@a8000 {
+ ahci0: sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sata@e0000 {
+ bm: bm@c8000 {
+ compatible = "marvell,armada-380-neta-bm";
+ reg = <0xc8000 0xac>;
+ clocks = <&gateclk 13>;
+ internal-mem = <&bm_bppi>;
+ status = "disabled";
+ };
+
+ ahci1: sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "nand";
};
- thermal@e8078 {
+ thermal: thermal@e8078 {
compatible = "marvell,armada380-thermal";
- reg = <0xe4078 0x4>, <0xe4074 0x4>;
+ reg = <0xe4078 0x4>, <0xe4070 0x8>;
status = "okay";
};
- flash@d0000 {
+ nand_controller: nand-controller@d0000 {
compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
status = "disabled";
};
- sdhci@d8000 {
+ sdhci: sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
status = "disabled";
};
- usb3@f0000 {
+ usb3_0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usb3@f8000 {
+ usb3_1: usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
+
+ crypto_sram0: sa-sram0 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
+ clocks = <&gateclk 23>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
+ };
+
+ crypto_sram1: sa-sram1 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
+ clocks = <&gateclk 21>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
+ };
+
+ bm_bppi: bm-bppi {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
+ ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gateclk 13>;
+ no-memory-wc;
+ status = "disabled";
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,armada-380-spi",
+ "marvell,orion-spi";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@10680 {
+ compatible = "marvell,armada-380-spi",
+ "marvell,orion-spi";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
};
clocks {
- /* 2 GHz fixed main PLL */
+ /* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ psci-area@4000000 {
+ reg = <0x0 0x4000000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
ap806 {
#address-cells = <2>;
#size-cells = <2>;
serial@78b0000 {
u-boot,dm-pre-reloc;
- };
};
+ };
};
reg = <1>;
};
};
+
+&sata {
+ status = "okay";
+};
model = "LS1021A IOT Board";
aliases {
- enet2_rgmii_phy = &rgmii_phy1;
- enet0_sgmii_phy = &sgmii_phy2;
- enet1_sgmii_phy = &sgmii_phy0;
+ enet2-rgmii-phy = &rgmii_phy1;
+ enet0-sgmii-phy = &sgmii_phy2;
+ enet1-sgmii-phy = &sgmii_phy0;
spi0 = &qspi;
spi1 = &dspi1;
};
model = "LS1021A QDS Board";
aliases {
- enet0_rgmii_phy = &rgmii_phy1;
- enet1_rgmii_phy = &rgmii_phy2;
- enet2_rgmii_phy = &rgmii_phy3;
- enet0_sgmii_phy = &sgmii_phy1c;
- enet1_sgmii_phy = &sgmii_phy1d;
+ enet0-rgmii-phy = &rgmii_phy1;
+ enet1-rgmii-phy = &rgmii_phy2;
+ enet2-rgmii-phy = &rgmii_phy3;
+ enet0-sgmii-phy = &sgmii_phy1c;
+ enet1-sgmii-phy = &sgmii_phy1d;
spi0 = &qspi;
spi1 = &dspi0;
};
model = "LS1021A TWR Board";
aliases {
- enet2_rgmii_phy = &rgmii_phy1;
- enet0_sgmii_phy = &sgmii_phy2;
- enet1_sgmii_phy = &sgmii_phy0;
+ enet2-rgmii-phy = &rgmii_phy1;
+ enet0-sgmii-phy = &sgmii_phy2;
+ enet1-sgmii-phy = &sgmii_phy0;
spi0 = &qspi;
spi1 = &dspi1;
};
compatible = "topic,miamiplus", "xlnx,zynq-7000";
};
+/* The miamiplus contains a speedgrade-2 device and runs at 800MHz */
+&cpu0 {
+ operating-points = <
+ /* kHz uV */
+ 800000 1000000
+ 400000 1000000
+ >;
+};
+
&qspi {
is-dual = <1>;
};
/* dma-coherent; */
};
- sdhci0: sdhci@ff160000 {
+ sdhci0: mmc@ff160000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
nvmem-cell-names = "soc_revision";
};
- sdhci1: sdhci@ff170000 {
+ sdhci1: mmc@ff170000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
CONFIG_SYS_FSL_ESDHC_ADDR)
#define SET_QDMA_ICID(compat, streamid) \
- SET_SCFG_ICID(compat, streamid, dma_icid,\
+ SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+ QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+ QDMA_BASE_ADDR), \
+ SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+ QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
QDMA_BASE_ADDR)
#define SET_EDMA_ICID(streamid) \
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG 0x20a80
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
+/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
+#define SVR_LS1043A_P23 0x879202
+#define SVR_LS1023A_P23 0x87920A
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
#define SVR_LS1048A 0x870320
support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and
RPi 3 due to different peripheral address maps.
- This option creates a build targetting the ARM1176 ISA.
+ This option creates a build targeting the ARM1176 ISA.
select BCM2835
config TARGET_RPI_0_W
This is required for U-Boot to operate correctly, even if you only
care about the HDMI/usbkbd console.
- This option creates a build targetting the ARMv7/AArch32 ISA.
+ This option creates a build targeting the ARMv7/AArch32 ISA.
select BCM2835
config TARGET_RPI_2
arm_loader: emmc clock depends on core clock See:
https://github.com/raspberrypi/firmware/issues/572".
- This option creates a build targetting the ARMv7/AArch32 ISA.
+ This option creates a build targeting the ARMv7/AArch32 ISA.
select BCM2836
config TARGET_RPI_3_32B
required for U-Boot to operate correctly, even if you only care
about the HDMI/usbkbd console.
- This option creates a build targetting the ARMv7/AArch32 ISA.
+ This option creates a build targeting the ARMv7/AArch32 ISA.
select BCM2837_32B
config TARGET_RPI_3
duplicated here. The VC FW enhancement is tracked in
https://github.com/raspberrypi/firmware/issues/579.
- This option creates a build targetting the ARMv8/AArch64 ISA.
+ This option creates a build targeting the ARMv8/AArch64 ISA.
select BCM2837_64B
endchoice
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
- * (This file is derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
+ * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
*
*/
bool "Support CONTROLCENTERDC"
select 88F6820
+config TARGET_X530
+ bool "Support Allied Telesis x530"
+ select 88F6820
+
endchoice
config SYS_BOARD
default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
+ default "x530" if TARGET_X530
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
+ default "x530" if TARGET_X530
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
+ default "alliedtelesis" if TARGET_X530
config SYS_SOC
default "mvebu"
}
}
-int dram_init_banksize(void)
+__weak int dram_init_banksize(void)
{
if (CONFIG_IS_ENABLED(ARMADA_8K))
a8k_dram_init_banksize();
return 0;
}
-int dram_init(void)
+__weak int dram_init(void)
{
if (CONFIG_IS_ENABLED(ARMADA_8K)) {
gd->ram_size = a8k_dram_scan_ap_sz();
static const char *apq8016_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- if (selector < 130) {
+ if (selector < 122) {
snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
return pin_name;
} else {
- return msm_pinctrl_pins[selector - 130];
+ return msm_pinctrl_pins[selector - 122];
}
}
}
struct msm_pinctrl_data apq8016_data = {
- .pin_count = 140,
+ .pin_count = 133,
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = apq8016_get_function_name,
.get_function_mux = apq8016_get_function_mux,
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
- * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
+ * (This file derived from arch/arm/mach-zynqmp/cpu.c)
*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*/
will be used for board configuration.
config SYS_MALLOC_F_LEN
- default 0x600
+ default 0x800
config SYS_MALLOC_LEN
default 0x1400000
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
-#define ZYNQ_GEM_BASEADDR0 0xE000B000
-#define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
return regs.regs[0];
}
-#if defined(CONFIG_CLK_ZYNQMP)
-unsigned int zynqmp_pmufw_version(void)
+unsigned int __maybe_unused zynqmp_pmufw_version(void)
{
int ret;
u32 ret_payload[PAYLOAD_ARG_CNT];
return pm_api_version;
}
-#endif
static int zynqmp_mmio_rawwrite(const u32 address,
const u32 mask,
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define ZYNQ_GEM_BASEADDR0 0xFF0B0000
-#define ZYNQ_GEM_BASEADDR1 0xFF0C0000
-#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
-#define ZYNQ_GEM_BASEADDR3 0xFF0E0000
-
#define ZYNQ_I2C_BASEADDR0 0xFF020000
#define ZYNQ_I2C_BASEADDR1 0xFF030000
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
+dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
+dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb
targets += $(dtb-y)
status = "disabled";
};
+ switch@1010000 {
+ pinctrl-0 = <&miim1_pins>;
+ pinctrl-names = "default";
+
+ compatible = "mscc,vsc7514-switch";
+ reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
+ <0x1030000 0x10000>, /* VTSS_TO_REW */
+ <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
+ <0x10d0000 0x10000>, /* VTSS_TO_HSIO */
+ <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
+ <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
+ <0x1200000 0x100>, /* VTSS_TO_DEV_2 */
+ <0x1210000 0x100>, /* VTSS_TO_DEV_3 */
+ <0x1220000 0x100>, /* VTSS_TO_DEV_4 */
+ <0x1230000 0x100>, /* VTSS_TO_DEV_5 */
+ <0x1240000 0x100>, /* VTSS_TO_DEV_6 */
+ <0x1250000 0x100>, /* VTSS_TO_DEV_7 */
+ <0x1260000 0x100>, /* VTSS_TO_DEV_8 */
+ <0x1270000 0x100>, /* NA */
+ <0x1280000 0x100>, /* NA */
+ <0x1800000 0x80000>, /* VTSS_TO_QSYS */
+ <0x1880000 0x10000>; /* VTSS_TO_ANA */
+ reg-names = "sys", "rew", "qs", "hsio", "port0",
+ "port1", "port2", "port3", "port4", "port5",
+ "port6", "port7", "port8", "port9",
+ "port10", "qsys", "ana";
+ interrupts = <21 22>;
+ interrupt-names = "xtr", "inj";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ };
+ };
+ };
+
+ mdio0: mdio@107009c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+ interrupts = <14>;
+ status = "disabled";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+
reset@1070008 {
compatible = "mscc,ocelot-chip-reset";
reg = <0x1070008 0x4>;
function = "si";
};
+ miim1_pins: miim1-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "miim1";
+ };
+
spi_cs2_pin: spi-cs2-pin {
pins = "GPIO_9";
function = "si";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,serval";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,serval-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,serval-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset@1070008 {
+ compatible = "mscc,serval-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl@1070034 {
+ compatible = "mscc,serval-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
+ function = "sio";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_13", "GPIO_14";
+ function = "uart2";
+ };
+ };
+
+ spi0: spi-bitbang {
+ compatible = "mscc,luton-bb-spi";
+ status = "okay";
+ reg = <0x50 0x4>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sgpio: gpio@10700b4 {
+ compatible = "mscc,luton-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700b4 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&sgpio 0 0 64>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,servalt";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,servalt-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,servalt-icpu-intr";
+ reg = <0x70 0x74>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset@1010008 {
+ compatible = "mscc,servalt-chip-reset";
+ reg = <0x1010008 0x4>;
+ };
+
+ gpio: pinctrl@1010034 {
+ compatible = "mscc,servalt-pinctrl";
+ reg = <0x1010034 0x90>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 36>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sio";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_6", "GPIO_7";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_20", "GPIO_21";
+ function = "uart2";
+ };
+ };
+
+ spi0: spi-bitbang {
+ compatible = "mscc,luton-bb-spi";
+ status = "okay";
+ reg = <0x50 0x4>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sgpio: gpio@1010120 {
+ compatible = "mscc,ocelot-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio_pins>;
+ pinctrl-names = "default";
+ reg = <0x1010120 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&sgpio 0 0 128>;
+ };
+ };
+};
status = "okay";
mscc,sgpio-ports = <0x00FFFFFF>;
};
+
+&mdio0 {
+ status = "okay";
+};
+
+&port0 {
+ phy-handle = <&phy0>;
+};
+
+&port1 {
+ phy-handle = <&phy1>;
+};
+
+&port2 {
+ phy-handle = <&phy2>;
+};
+
+&port3 {
+ phy-handle = <&phy3>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,serval.dtsi"
+
+/ {
+ model = "Serval PCB105 Reference Board";
+ compatible = "mscc,serval-pcb105", "mscc,serval";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb105:green:status";
+ gpios = <&sgpio 43 1>; /* p11.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb105:red:status";
+ gpios = <&sgpio 11 1>; /* p11.0 */
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+&sgpio {
+ status = "okay";
+ sgpio-ports = <0x00FFFFFF>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,serval.dtsi"
+
+/ {
+ model = "Serval PCB106 Reference Board";
+ compatible = "mscc,serval-pcb106", "mscc,serval";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb106:green:status";
+ gpios = <&sgpio 43 1>; /* p11.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb106:red:status";
+ gpios = <&sgpio 11 1>; /* p11.0 */
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+&sgpio {
+ status = "okay";
+ sgpio-ports = <0x00FFFFFF>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,servalt.dtsi"
+
+/ {
+ model = "ServalT PCB116 Reference Board";
+ compatible = "mscc,servalt-pcb116", "mscc,servalt";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb116:green:status";
+ gpios = <&sgpio 70 0>; /* p6.2 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb116:red:status";
+ gpios = <&sgpio 102 0>; /* p6.3 */
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+&sgpio {
+ status = "okay";
+ sgpio-ports = <0x0000fe7f>;
+};
help
This supports MSCC Jaguar2 family of SOCs.
+config SOC_SERVALT
+ bool "Servalt SOC Family"
+ select SOC_VCOREIII
+ select MSCC_BB_SPI
+ help
+ This supports MSCC Servalt family of SOCs.
+
+config SOC_SERVAL
+ bool "Serval SOC Family"
+ select SOC_VCOREIII
+ select MSCC_BB_SPI
+ help
+ This supports MSCC Serval family of SOCs.
+
endchoice
config SYS_CONFIG_NAME
source "board/mscc/jr2/Kconfig"
+source "board/mscc/servalt/Kconfig"
+
+source "board/mscc/serval/Kconfig"
endmenu
obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
obj-$(CONFIG_SOC_OCELOT) += gpio.o
+obj-$(CONFIG_SOC_SERVAL) += gpio.o
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#else
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
-#ifdef CONFIG_SOC_JR2
+#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
ret = hal_vcoreiii_train_bytelane(0);
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
#include <mach/jr2/jr2_devcpu_gcb.h>
#include <mach/jr2/jr2_devcpu_gcb_miim_regs.h>
#include <mach/jr2/jr2_icpu_cfg.h>
+#elif defined(CONFIG_SOC_SERVALT)
+#include <mach/servalt/servalt.h>
+#include <mach/servalt/servalt_devcpu_gcb.h>
+#include <mach/servalt/servalt_devcpu_gcb_miim_regs.h>
+#include <mach/servalt/servalt_icpu_cfg.h>
+#elif defined(CONFIG_SOC_SERVAL)
+#include <mach/serval/serval.h>
+#include <mach/serval/serval_devcpu_gcb.h>
+#include <mach/serval/serval_devcpu_gcb_miim_regs.h>
+#include <mach/serval/serval_icpu_cfg.h>
#else
#error Unsupported platform
#endif
#define VC3_MPAR_CL 6
#define VC3_MPAR_tWTR 4
#define VC3_MPAR_tRC 16
-#define VC3_MPR_tFAW 16
+#define VC3_MPAR_tFAW 16
#define VC3_MPAR_tRP 5
#define VC3_MPAR_tRRD 4
#define VC3_MPAR_tRCD 5
#endif
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MIPS_VCOREIII_MEMORY_16BIT 1
#endif
ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MSCC_MEMPARM_PERIOD \
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
PAUSE();
}
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
static inline void sleep_100ns(u32 val)
panic("DDR init failed\n");
}
-#else /* JR2 */
+#else /* JR2 || ServalT || Serval */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* Ensure the memory controller physical iface is forced reset */
panic("DDR init failed\n");
}
-#endif
+#endif /* JR2 || ServalT || Serval */
/*
* DDR memory sanity checking done, possibly enable ECC.
/* Wait for ZCAL to clear */
while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
;
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT)
/* Check no ZCAL_ERR */
if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT)
& ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG);
writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
#else /* Luton */
clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL);
writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL);
-#if defined(CONFIG_SOC_OCELOT)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
/* Termination setup - enable ODT */
writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
/* Assert ODT0 for any write */
BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
/* Release Reset from DDR */
+#if defined(CONFIG_SOC_OCELOT)
hal_vcoreiii_ddr_reset_release();
+#endif
writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
-#elif defined(CONFIG_SOC_JR2)
+#elif defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
#else /* Luton */
/* Settle...? */
sleep_100ns(10000);
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
/* Establish data contents in DDR RAM for training */
__raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Serval Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_H_
+#define _MSCC_SERVAL_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN1_SIZE 0x00200000
+#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
+#define MSCC_IO_ORIGIN2_SIZE 0x01000000
+#define BASE_CFG ((void __iomem *)0x70000000)
+#define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_DEVCPU_GCB_H_
+#define _MSCC_SERVAL_DEVCPU_GCB_H_
+
+#define CHIP_ID 0x0
+
+#define PERF_GPR 0x4
+
+#define PERF_SOFT_RST 0x8
+
+#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
+#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+
+#define GPIO_ALT(x) (0x54 + 4 * (x))
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
+#define _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0x5c + (gi * 36))
+#define MIIM_MII_CMD(gi) (0x64 + (gi * 36))
+#define MIIM_MII_DATA(gi) (0x68 + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
+#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVAL_ICPU_CFG_H_
+#define _MSCC_SERVAL_ICPU_CFG_H_
+
+#define ICPU_GPR(x) (0x4 * (x))
+#define ICPU_GPR_RSZ 0x8
+
+#define ICPU_RESET 0x20
+
+#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
+#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
+#define ICPU_RESET_CORE_RST_FORCE BIT(1)
+#define ICPU_RESET_MEM_RST_FORCE BIT(0)
+
+#define ICPU_GENERAL_CTRL 0x24
+
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(11)
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(10)
+#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(9)
+#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
+#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(7)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(6)
+#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(5)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(4)
+#define ICPU_GENERAL_CTRL_IF_SI_MST_ENA BIT(3)
+#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
+#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
+#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
+
+#define ICPU_SPI_MST_CFG 0x3c
+
+#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
+#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
+#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
+
+#define ICPU_SW_MODE 0x50
+
+#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
+#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
+#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
+#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
+#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
+#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
+#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
+#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
+
+#define ICPU_INTR_ENA 0x84
+
+#define ICPU_DST_INTR_MAP(x) (0x94 + 0x4 * (x))
+#define ICPU_DST_INTR_MAP_RSZ 0x4
+
+#define ICPU_TIMER_TICK_DIV 0xe0
+
+#define ICPU_TIMER_VALUE(x) (0xe4 + 0x4 * (x))
+#define ICPU_TIMER_VALUE_RSZ 0x2
+
+#define ICPU_TIMER_CTRL(x) (0xfc + 0x4 * (x))
+#define ICPU_TIMER_CTRL_RSZ 0x2
+
+#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
+#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
+#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
+#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
+
+#define ICPU_MEMCTRL_CTRL 0x108
+
+#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
+#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
+#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
+#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
+
+#define ICPU_MEMCTRL_CFG 0x10c
+
+#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
+#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
+#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
+#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
+#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
+#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_STAT 0x110
+
+#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
+#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
+#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
+#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
+
+#define ICPU_MEMCTRL_REF_PERIOD 0x114
+
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_ZQCAL 0x118
+
+#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
+#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
+
+#define ICPU_MEMCTRL_TIMING0 0x11c
+
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING1 0x120
+
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING2 0x124
+
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING3 0x128
+
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING4 0x12c
+
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
+
+#define ICPU_MEMCTRL_MR0_VAL 0x130
+
+#define ICPU_MEMCTRL_MR1_VAL 0x134
+
+#define ICPU_MEMCTRL_MR2_VAL 0x138
+
+#define ICPU_MEMCTRL_MR3_VAL 0x13c
+
+#define ICPU_MEMCTRL_TERMRES_CTRL 0x140
+
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DFT 0x144
+
+#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
+#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
+#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
+#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
+#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
+#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DQS_DLY(x) (0x148 + 0x4 * (x))
+#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x2
+
+#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
+
+#define ICPU_MEMCTRL_DQS_AUTO 0x150
+#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x2
+
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
+
+#define ICPU_MEMPHY_CFG 0x158
+
+#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
+#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
+#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
+#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
+#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
+#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
+#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
+#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
+#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
+#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
+#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
+
+#define ICPU_MEMPHY_ZCAL 0x180
+
+#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
+
+#define ICPU_MEMPHY_ZCAL_STAT 0x184
+
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Servalt Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVALT_H_
+#define _MSCC_SERVALT_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN1_SIZE 0x00200000
+#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
+#define MSCC_IO_ORIGIN2_SIZE 0x01000000
+#define BASE_CFG ((void __iomem *)0x70000000)
+#define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVALT_DEVCPU_GCB_H_
+#define _MSCC_SERVALT_DEVCPU_GCB_H_
+
+#define PERF_GPR 0x4
+
+#define PERF_SOFT_RST 0x8
+
+#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
+#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+
+#define GPIO_GPIO_ALT(x) (0x74 + 4 * (x))
+#define GPIO_GPIO_ALT1(x) (0x7c + 4 * (x))
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_
+#define _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36))
+#define MIIM_MII_CMD(gi) (0xcc + (gi * 36))
+#define MIIM_MII_DATA(gi) (0xd0 + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
+#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_SERVALT_ICPU_CFG_H_
+#define _MSCC_SERVALT_ICPU_CFG_H_
+
+#define ICPU_GPR(x) (0x4 * (x))
+#define ICPU_GPR_RSZ 0x8
+
+#define ICPU_RESET 0x20
+
+#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
+#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
+#define ICPU_RESET_CORE_RST_FORCE BIT(1)
+#define ICPU_RESET_MEM_RST_FORCE BIT(0)
+
+#define ICPU_GENERAL_CTRL 0x24
+
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
+#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
+#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
+#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
+#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8)
+#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6)
+#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
+#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
+#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
+#define ICPU_GENERAL_CTRL_SIMC_SSP_ENA BIT(3)
+#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
+#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
+#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
+
+#define ICPU_SPI_MST_CFG 0x3c
+
+#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
+#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
+#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
+#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
+
+#define ICPU_SW_MODE 0x50
+
+#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
+#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
+#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
+#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
+#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
+#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
+#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
+#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
+
+#define ICPU_INTR_ENA 0x88
+
+#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
+#define ICPU_DST_INTR_MAP_RSZ 0x4
+
+#define ICPU_TIMER_TICK_DIV 0xe8
+
+#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x))
+#define ICPU_TIMER_VALUE_RSZ 0x2
+
+#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x))
+#define ICPU_TIMER_CTRL_RSZ 0x2
+
+#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
+#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
+#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
+#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
+
+#define ICPU_MEMCTRL_CTRL 0x110
+
+#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
+#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
+#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
+#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
+
+#define ICPU_MEMCTRL_CFG 0x114
+
+#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
+#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
+#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
+#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
+#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
+#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_STAT 0x118
+
+#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
+#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
+#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
+#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
+
+#define ICPU_MEMCTRL_REF_PERIOD 0x11c
+
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_ZQCAL 0x120
+
+#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
+#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
+
+#define ICPU_MEMCTRL_TIMING0 0x124
+
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING1 0x128
+
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING2 0x12c
+
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING3 0x130
+
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING4 0x134
+
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
+#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
+
+#define ICPU_MEMCTRL_MR0_VAL 0x138
+
+#define ICPU_MEMCTRL_MR1_VAL 0x13c
+
+#define ICPU_MEMCTRL_MR2_VAL 0x140
+
+#define ICPU_MEMCTRL_MR3_VAL 0x144
+
+#define ICPU_MEMCTRL_TERMRES_CTRL 0x148
+
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DFT 0x14c
+
+#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
+#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
+#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
+#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
+#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
+#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
+#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x))
+#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x2
+
+#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
+
+#define ICPU_MEMCTRL_DQS_AUTO (0x158 + 0x4 * (x))
+#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x2
+
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
+#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
+
+#define ICPU_MEMPHY_CFG 0x160
+
+#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
+#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
+#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
+#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
+#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
+#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
+#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
+#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
+#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
+#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
+#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
+
+#define ICPU_MEMPHY_ZCAL 0x188
+
+#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
+
+#define ICPU_MEMPHY_ZCAL_STAT 0x18c
+
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
+
+#endif
void _machine_restart(void)
{
-#if defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
/* Set owner */
reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
ICPU_RESET_CORE_RST_CPU_ONLY |
ICPU_RESET_CORE_RST_FORCE,
BASE_CFG + ICPU_RESET);
-#else
+#elif defined(CONFIG_SOC_SERVAL)
+ register unsigned long i;
+
+ /* Prevent VCore-III from being reset with a global reset */
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+
+ /* Do global reset */
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ for (i = 0; i < 1000; i++)
+ ;
+
+ /* Power down DDR for clean DDR re-training */
+ writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) |
+ ICPU_MEMCTRL_CTRL_PWR_DOWN,
+ BASE_CFG + ICPU_MEMCTRL_CTRL);
+
+ while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
+ ICPU_MEMCTRL_STAT_PWR_DOWN_ACK))
+ ;
+
+ /* Reset VCore-III, only. */
+ writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET);
+#else /* Luton || Ocelot */
register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
CONFIG_STANDALONE_LOAD_ADDR = 0x300000
LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/nds32.lds
-PLATFORM_RELFLAGS += -fno-common -mrelax
+PLATFORM_RELFLAGS += -fno-common -mrelax -mno-ext-fpu-dp -mfloat-abi=soft
PLATFORM_RELFLAGS += -gdwarf-2
-PLATFORM_CPPFLAGS += -D__nds32__ -G0 -ffixed-10 -fpie
+PLATFORM_CPPFLAGS += -D__nds32__ -ffixed-10 -fpie -mcmodel=large
-LDFLAGS_u-boot = --gc-sections --relax -pie
+LDFLAGS_u-boot = --gc-sections --relax -pie --mabi=AABI
};
mmc0: mmc@f0e00000 {
- compatible = "andestech,atsdc010";
+ compatible = "andestech,atfsdc010";
max-frequency = <100000000>;
fifo-depth = <0x10>;
reg = <0xf0e00000 0x1000>;
};
mmc0: mmc@98e00000 {
- compatible = "andestech,atsdc010";
+ compatible = "andestech,atfsdc010";
max-frequency = <30000000>;
fifo-depth = <0x10>;
reg = <0x98e00000 0x1000>;
# Copyright 2004 Freescale Semiconductor, Inc.
PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float
+PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables
/*------------------------------------------------------*/
GET_GOT /* initialize GOT access */
+ /* Needed for -msingle-pic-base */
+ bl _GLOBAL_OFFSET_TABLE_@local-4
+ mflr r30
/* r3: IMMR */
lis r3, CONFIG_SYS_IMMR@h
# Xianghua Xiao, X.Xiao@motorola.com
PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string
+PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables
# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
# see "[PATCH,rs6000] make -mno-spe work as expected" on
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
+ /* Needed for -msingle-pic-base */
+ bl _GLOBAL_OFFSET_TABLE_@local-4
+ mflr r30
/* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
mr r3, r24
hex
default 0xe400
help
- ACPI Power Managment 1 (PM1) i/o-mapped base address.
+ ACPI Power Management 1 (PM1) i/o-mapped base address.
This device is defined in ACPI specification, with 16 bytes in size.
endif
hex
default 0x1000
help
- ACPI Power Managment 1 (PM1) i/o-mapped base address.
+ ACPI Power Management 1 (PM1) i/o-mapped base address.
This device is defined in ACPI specification, with 16 bytes in size.
config ACPI_PBLK_BASE
#
# Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
-obj-y := turris_mox.o
+obj-y := turris_mox.o mox_sp.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define RWTM_CMD_PARAM(i) (size_t)(0xd00b0000 + (i) * 4)
+#define RWTM_CMD 0xd00b0040
+#define RWTM_CMD_RETSTATUS 0xd00b0080
+#define RWTM_CMD_STATUS(i) (size_t)(0xd00b0084 + (i) * 4)
+
+#define RWTM_HOST_INT_RESET 0xd00b00c8
+#define RWTM_HOST_INT_MASK 0xd00b00cc
+#define SP_CMD_COMPLETE BIT(0)
+
+#define MBOX_STS_SUCCESS (0x0 << 30)
+#define MBOX_STS_FAIL (0x1 << 30)
+#define MBOX_STS_BADCMD (0x2 << 30)
+#define MBOX_STS_LATER (0x3 << 30)
+#define MBOX_STS_ERROR(s) ((s) & (3 << 30))
+#define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff)
+#define MBOX_STS_CMD(s) ((s) & 0x3ff)
+
+enum mbox_cmd {
+ MBOX_CMD_GET_RANDOM = 1,
+ MBOX_CMD_BOARD_INFO,
+ MBOX_CMD_ECDSA_PUB_KEY,
+ MBOX_CMD_HASH,
+ MBOX_CMD_SIGN,
+ MBOX_CMD_VERIFY,
+
+ MBOX_CMD_OTP_READ,
+ MBOX_CMD_OTP_WRITE
+};
+
+static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout)
+{
+ const int tries = 50;
+ int i;
+ u32 status;
+
+ clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE);
+
+ writel(cmd, RWTM_CMD);
+
+ for (i = 0; i < tries; ++i) {
+ mdelay(10);
+ if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE)
+ break;
+ }
+
+ if (i == tries) {
+ /* if timed out, don't read status */
+ setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i < nout; ++i)
+ out[i] = readl(RWTM_CMD_STATUS(i));
+ status = readl(RWTM_CMD_RETSTATUS);
+
+ setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+
+ if (MBOX_STS_CMD(status) != cmd)
+ return -EIO;
+ else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL)
+ return -(int)MBOX_STS_VALUE(status);
+ else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS)
+ return -EIO;
+ else
+ return MBOX_STS_VALUE(status);
+}
+
+const char *mox_sp_get_ecdsa_public_key(void)
+{
+ static char public_key[135];
+ u32 out[16];
+ int res;
+
+ if (public_key[0])
+ return public_key;
+
+ res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16);
+ if (res < 0)
+ return NULL;
+
+ sprintf(public_key,
+ "%06x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x",
+ (u32)res, out[0], out[1], out[2], out[3], out[4], out[5],
+ out[6], out[7], out[8], out[9], out[10], out[11], out[12],
+ out[13], out[14], out[15]);
+
+ return public_key;
+}
+
+static inline void res_to_mac(u8 *mac, u32 t1, u32 t2)
+{
+ mac[0] = t1 >> 8;
+ mac[1] = t1;
+ mac[2] = t2 >> 24;
+ mac[3] = t2 >> 16;
+ mac[4] = t2 >> 8;
+ mac[5] = t2;
+}
+
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram)
+{
+ u32 out[8];
+ int res;
+
+ res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8);
+ if (res < 0)
+ return res;
+
+ if (sn) {
+ *sn = out[1];
+ *sn <<= 32;
+ *sn |= out[0];
+ }
+
+ if (bv)
+ *bv = out[2];
+
+ if (ram)
+ *ram = out[3];
+
+ if (mac1)
+ res_to_mac(mac1, out[4], out[5]);
+
+ if (mac2)
+ res_to_mac(mac2, out[6], out[7]);
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#ifndef _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
+#define _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
+
+#include <common.h>
+
+const char *mox_sp_get_ecdsa_public_key(void);
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv,
+ int *ram);
+
+#endif /* _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ */
*/
#include <common.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <spi.h>
+#include <mvebu/comphy.h>
+#include <miiphy.h>
#include <linux/string.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
+#include <environment.h>
#ifdef CONFIG_WDT_ARMADA_37XX
#include <wdt.h>
#endif
+#include "mox_sp.h"
+
#define MAX_MOX_MODULES 10
#define MOX_MODULE_SFP 0x1
DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void)
+{
+ gd->ram_base = 0;
+ gd->ram_size = (phys_size_t)get_ram_size(0, 0x40000000);
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = (phys_addr_t)0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
#if defined(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
return 0;
}
-int last_stage_init(void)
+static int mox_do_spi(u8 *in, u8 *out, size_t size)
{
struct spi_slave *slave;
struct udevice *dev;
- u8 din[10], dout[10];
- int ret, i;
- size_t len = 0;
- char module_topology[128];
+ int ret;
- ret = spi_get_bus_and_cs(0, 1, 20000000, SPI_CPHA, "spi_generic_drv",
- "mox-modules@1", &dev, &slave);
+ ret = spi_get_bus_and_cs(0, 1, 1000000, SPI_CPHA | SPI_CPOL,
+ "spi_generic_drv", "moxtet@1", &dev,
+ &slave);
if (ret)
goto fail;
if (ret)
goto fail_free;
- memset(din, 0, 10);
- memset(dout, 0, 10);
+ ret = spi_xfer(slave, size * 8, out, in, SPI_XFER_ONCE);
+
+ spi_release_bus(slave);
+fail_free:
+ spi_free_slave(slave);
+fail:
+ return ret;
+}
+
+static int mox_get_topology(const u8 **ptopology, int *psize, int *pis_sd)
+{
+ static int is_sd;
+ static u8 topology[MAX_MOX_MODULES - 1];
+ static int size;
+ u8 din[MAX_MOX_MODULES], dout[MAX_MOX_MODULES];
+ int ret, i;
+
+ if (size) {
+ if (ptopology)
+ *ptopology = topology;
+ if (psize)
+ *psize = size;
+ if (pis_sd)
+ *pis_sd = is_sd;
+ return 0;
+ }
+
+ memset(din, 0, MAX_MOX_MODULES);
+ memset(dout, 0, MAX_MOX_MODULES);
+
+ ret = mox_do_spi(din, dout, MAX_MOX_MODULES);
+ if (ret)
+ return ret;
+
+ if (din[0] == 0x10)
+ is_sd = 1;
+ else if (din[0] == 0x00)
+ is_sd = 0;
+ else
+ return -ENODEV;
+
+ for (i = 1; i < MAX_MOX_MODULES && din[i] != 0xff; ++i)
+ topology[i - 1] = din[i] & 0xf;
+ size = i - 1;
+
+ if (ptopology)
+ *ptopology = topology;
+ if (psize)
+ *psize = size;
+ if (pis_sd)
+ *pis_sd = is_sd;
+
+ return 0;
+}
+
+int comphy_update_map(struct comphy_map *serdes_map, int count)
+{
+ int ret, i, size, sfpindex = -1, swindex = -1;
+ const u8 *topology;
- ret = spi_xfer(slave, 80, dout, din, SPI_XFER_ONCE);
+ ret = mox_get_topology(&topology, &size, NULL);
if (ret)
- goto fail_release;
+ return ret;
+
+ for (i = 0; i < size; ++i) {
+ if (topology[i] == MOX_MODULE_SFP && sfpindex == -1)
+ sfpindex = i;
+ else if ((topology[i] == MOX_MODULE_TOPAZ ||
+ topology[i] == MOX_MODULE_PERIDOT) &&
+ swindex == -1)
+ swindex = i;
+ }
+
+ if (sfpindex >= 0 && swindex >= 0) {
+ if (sfpindex < swindex)
+ serdes_map[0].speed = PHY_SPEED_1_25G;
+ else
+ serdes_map[0].speed = PHY_SPEED_3_125G;
+ } else if (sfpindex >= 0) {
+ serdes_map[0].speed = PHY_SPEED_1_25G;
+ } else if (swindex >= 0) {
+ serdes_map[0].speed = PHY_SPEED_3_125G;
+ }
+
+ return 0;
+}
+
+#define SW_SMI_CMD_R(d, r) (0x9800 | (((d) & 0x1f) << 5) | ((r) & 0x1f))
+#define SW_SMI_CMD_W(d, r) (0x9400 | (((d) & 0x1f) << 5) | ((r) & 0x1f))
+
+static int sw_multi_read(struct mii_dev *bus, int sw, int dev, int reg)
+{
+ bus->write(bus, sw, 0, 0, SW_SMI_CMD_R(dev, reg));
+ mdelay(5);
+ return bus->read(bus, sw, 0, 1);
+}
+
+static void sw_multi_write(struct mii_dev *bus, int sw, int dev, int reg,
+ u16 val)
+{
+ bus->write(bus, sw, 0, 1, val);
+ bus->write(bus, sw, 0, 0, SW_SMI_CMD_W(dev, reg));
+ mdelay(5);
+}
+
+static int sw_scratch_read(struct mii_dev *bus, int sw, int reg)
+{
+ sw_multi_write(bus, sw, 0x1c, 0x1a, (reg & 0x7f) << 8);
+ return sw_multi_read(bus, sw, 0x1c, 0x1a) & 0xff;
+}
+
+static void sw_led_write(struct mii_dev *bus, int sw, int port, int reg,
+ u16 val)
+{
+ sw_multi_write(bus, sw, port, 0x16, 0x8000 | ((reg & 7) << 12)
+ | (val & 0x7ff));
+}
+
+static void sw_blink_leds(struct mii_dev *bus, int peridot, int topaz)
+{
+ int i, p;
+ struct {
+ int port;
+ u16 val;
+ int wait;
+ } regs[] = {
+ { 2, 0xef, 1 }, { 2, 0xfe, 1 }, { 2, 0x33, 0 },
+ { 4, 0xef, 1 }, { 4, 0xfe, 1 }, { 4, 0x33, 0 },
+ { 3, 0xfe, 1 }, { 3, 0xef, 1 }, { 3, 0x33, 0 },
+ { 1, 0xfe, 1 }, { 1, 0xef, 1 }, { 1, 0x33, 0 }
+ };
+
+ for (i = 0; i < 12; ++i) {
+ for (p = 0; p < peridot; ++p) {
+ sw_led_write(bus, 0x10 + p, regs[i].port, 0,
+ regs[i].val);
+ sw_led_write(bus, 0x10 + p, regs[i].port + 4, 0,
+ regs[i].val);
+ }
+ if (topaz) {
+ sw_led_write(bus, 0x2, 0x10 + regs[i].port, 0,
+ regs[i].val);
+ }
+
+ if (regs[i].wait)
+ mdelay(75);
+ }
+}
+
+static void check_switch_address(struct mii_dev *bus, int addr)
+{
+ if (sw_scratch_read(bus, addr, 0x70) >> 3 != addr)
+ printf("Check of switch MDIO address failed for 0x%02x\n",
+ addr);
+}
+
+static int sfp, pci, topaz, peridot, usb, passpci;
+static int sfp_pos, peridot_pos[3];
+static int module_count;
+
+static int configure_peridots(struct gpio_desc *reset_gpio)
+{
+ int i, ret;
+ u8 dout[MAX_MOX_MODULES];
+
+ memset(dout, 0, MAX_MOX_MODULES);
+
+ /* set addresses of Peridot modules */
+ for (i = 0; i < peridot; ++i)
+ dout[module_count - peridot_pos[i]] = (~i) & 3;
+
+ /*
+ * if there is a SFP module connected to the last Peridot module, set
+ * the P10_SMODE to 1 for the Peridot module
+ */
+ if (sfp)
+ dout[module_count - peridot_pos[i - 1]] |= 1 << 3;
+
+ dm_gpio_set_value(reset_gpio, 1);
+ mdelay(10);
- if (din[0] != 0x00 && din[0] != 0xff)
- goto fail_release;
+ ret = mox_do_spi(NULL, dout, module_count + 1);
- printf("Module Topology:\n");
- for (i = 1; i < 10 && din[i] != 0xff; ++i) {
- u8 mid = din[i] & 0xf;
- size_t mlen;
- const char *mname = "";
+ mdelay(10);
+ dm_gpio_set_value(reset_gpio, 0);
- switch (mid) {
- case 0x1:
- mname = "sfp-";
- printf("% 4i: SFP Module\n", i);
+ mdelay(50);
+
+ return ret;
+}
+
+static int get_reset_gpio(struct gpio_desc *reset_gpio)
+{
+ int node;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "cznic,moxtet");
+ if (node < 0) {
+ printf("Cannot find Moxtet bus device node!\n");
+ return -1;
+ }
+
+ gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpios", 0,
+ reset_gpio, GPIOD_IS_OUT);
+
+ if (!dm_gpio_is_valid(reset_gpio)) {
+ printf("Cannot find reset GPIO for Moxtet bus!\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ int ret;
+ u8 mac1[6], mac2[6];
+
+ ret = mbox_sp_get_board_info(NULL, mac1, mac2, NULL, NULL);
+ if (ret < 0) {
+ printf("Cannot read data from OTP!\n");
+ return 0;
+ }
+
+ if (is_valid_ethaddr(mac1) && !env_get("ethaddr"))
+ eth_env_set_enetaddr("ethaddr", mac1);
+
+ if (is_valid_ethaddr(mac2) && !env_get("eth1addr"))
+ eth_env_set_enetaddr("eth1addr", mac2);
+
+ return 0;
+}
+
+static void mox_print_info(void)
+{
+ int ret, board_version, ram_size;
+ u64 serial_number;
+ const char *pub_key;
+
+ ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
+ &ram_size);
+ if (ret < 0)
+ return;
+
+ printf("Turris Mox:\n");
+ printf(" Board version: %i\n", board_version);
+ printf(" RAM size: %i MiB\n", ram_size);
+ printf(" Serial Number: %016llX\n", serial_number);
+
+ pub_key = mox_sp_get_ecdsa_public_key();
+ if (pub_key)
+ printf(" ECDSA Public Key: %s\n", pub_key);
+ else
+ printf("Cannot read ECDSA Public Key\n");
+}
+
+int last_stage_init(void)
+{
+ int ret, i;
+ const u8 *topology;
+ int is_sd;
+ struct mii_dev *bus;
+ struct gpio_desc reset_gpio = {};
+
+ mox_print_info();
+
+ ret = mox_get_topology(&topology, &module_count, &is_sd);
+ if (ret) {
+ printf("Cannot read module topology!\n");
+ return 0;
+ }
+
+ printf(" SD/eMMC version: %s\n", is_sd ? "SD" : "eMMC");
+
+ if (module_count)
+ printf("Module Topology:\n");
+
+ for (i = 0; i < module_count; ++i) {
+ switch (topology[i]) {
+ case MOX_MODULE_SFP:
+ printf("% 4i: SFP Module\n", i + 1);
+ break;
+ case MOX_MODULE_PCI:
+ printf("% 4i: Mini-PCIe Module\n", i + 1);
+ break;
+ case MOX_MODULE_TOPAZ:
+ printf("% 4i: Topaz Switch Module (4-port)\n", i + 1);
break;
- case 0x2:
- mname = "pci-";
- printf("% 4i: Mini-PCIe Module\n", i);
+ case MOX_MODULE_PERIDOT:
+ printf("% 4i: Peridot Switch Module (8-port)\n", i + 1);
break;
- case 0x3:
- mname = "topaz-";
- printf("% 4i: Topaz Switch Module\n", i);
+ case MOX_MODULE_USB3:
+ printf("% 4i: USB 3.0 Module (4 ports)\n", i + 1);
+ break;
+ case MOX_MODULE_PASSPCI:
+ printf("% 4i: Passthrough Mini-PCIe Module\n", i + 1);
break;
default:
- printf("% 4i: unknown (ID %i)\n", i, mid);
+ printf("% 4i: unknown (ID %i)\n", i + 1, topology[i]);
}
+ }
- mlen = strlen(mname);
- if (len + mlen < sizeof(module_topology)) {
- strcpy(module_topology + len, mname);
- len += mlen;
+ /* now check if modules are connected in supported mode */
+
+ for (i = 0; i < module_count; ++i) {
+ switch (topology[i]) {
+ case MOX_MODULE_SFP:
+ if (sfp) {
+ printf("Error: Only one SFP module is supported!\n");
+ } else if (topaz) {
+ printf("Error: SFP module cannot be connected after Topaz Switch module!\n");
+ } else {
+ sfp_pos = i;
+ ++sfp;
+ }
+ break;
+ case MOX_MODULE_PCI:
+ if (pci) {
+ printf("Error: Only one Mini-PCIe module is supported!\n");
+ } else if (usb) {
+ printf("Error: Mini-PCIe module cannot come after USB 3.0 module!\n");
+ } else if (i && (i != 1 || !passpci)) {
+ printf("Error: Mini-PCIe module should be the first connected module or come right after Passthrough Mini-PCIe module!\n");
+ } else {
+ ++pci;
+ }
+ break;
+ case MOX_MODULE_TOPAZ:
+ if (topaz) {
+ printf("Error: Only one Topaz module is supported!\n");
+ } else if (peridot >= 3) {
+ printf("Error: At most two Peridot modules can come before Topaz module!\n");
+ } else {
+ ++topaz;
+ }
+ break;
+ case MOX_MODULE_PERIDOT:
+ if (sfp || topaz) {
+ printf("Error: Peridot module must come before SFP or Topaz module!\n");
+ } else if (peridot >= 3) {
+ printf("Error: At most three Peridot modules are supported!\n");
+ } else {
+ peridot_pos[peridot] = i;
+ ++peridot;
+ }
+ break;
+ case MOX_MODULE_USB3:
+ if (pci) {
+ printf("Error: USB 3.0 module cannot come after Mini-PCIe module!\n");
+ } else if (usb) {
+ printf("Error: Only one USB 3.0 module is supported!\n");
+ } else if (i && (i != 1 || !passpci)) {
+ printf("Error: USB 3.0 module should be the first connected module or come right after Passthrough Mini-PCIe module!\n");
+ } else {
+ ++usb;
+ }
+ break;
+ case MOX_MODULE_PASSPCI:
+ if (passpci) {
+ printf("Error: Only one Passthrough Mini-PCIe module is supported!\n");
+ } else if (i != 0) {
+ printf("Error: Passthrough Mini-PCIe module should be the first connected module!\n");
+ } else {
+ ++passpci;
+ }
}
}
- printf("\n");
- module_topology[len > 0 ? len - 1 : 0] = '\0';
+ /* now configure modules */
- env_set("module_topology", module_topology);
+ if (get_reset_gpio(&reset_gpio) < 0)
+ return 0;
-fail_release:
- spi_release_bus(slave);
-fail_free:
- spi_free_slave(slave);
-fail:
- if (ret)
- printf("Cannot read module topology!\n");
- return ret;
+ if (peridot > 0) {
+ if (configure_peridots(&reset_gpio) < 0) {
+ printf("Cannot configure Peridot modules!\n");
+ peridot = 0;
+ }
+ } else {
+ dm_gpio_set_value(&reset_gpio, 1);
+ mdelay(50);
+ dm_gpio_set_value(&reset_gpio, 0);
+ mdelay(50);
+ }
+
+ if (peridot || topaz) {
+ /*
+ * now check if the addresses are set by reading Scratch & Misc
+ * register 0x70 of Peridot (and potentially Topaz) modules
+ */
+
+ bus = miiphy_get_dev_by_name("neta@30000");
+ if (!bus) {
+ printf("Cannot get MDIO bus device!\n");
+ } else {
+ for (i = 0; i < peridot; ++i)
+ check_switch_address(bus, 0x10 + i);
+
+ if (topaz)
+ check_switch_address(bus, 0x2);
+
+ sw_blink_leds(bus, peridot, topaz);
+ }
+ }
+
+ printf("\n");
+
+ return 0;
}
DECLARE_GLOBAL_DATA_PTR;
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2016_T1.0.eng_drop_v10"
DECLARE_GLOBAL_DATA_PTR;
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2014_T3.0"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Allied Telesis Labs
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
+ const char *node_name, const char *gpio_name, int value)
+{
+ int node;
+ int count;
+ int i;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
+ if (node < 0)
+ return -ENODEV;
+
+ if (!dm_gpio_is_valid(gpiod)) {
+ count =
+ gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+ gpio_name, gpiod, max_count,
+ GPIOD_IS_OUT);
+ if (count < 0)
+ return count;
+
+ for (i = 0; i < count; i++)
+ dm_gpio_set_value(&gpiod[i], value);
+ }
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
+ const char *gpio_name, int value);
+
+static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
+ const char *gpio_name, int value)
+{
+ return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
+}
--- /dev/null
+x530 BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/alliedtelesis/x530/
+F: board/alliedtelesis/common/gpio_hog.c
+F: board/alliedtelesis/common/gpio_hog.h
+F: arch/arm/dts/armada-385-atl-x530.dts
+F: arch/arm/dts/armada-385-atl-x530.dtsi
+F: arch/arm/dts/armada-385-atl-x530DP.dts
+F: arch/arm/dts/armada-385-atl-x530DP.dtsi
+F: include/configs/x530.h
+F: configs/x530_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Allied Telesis Labs
+#
+
+obj-y := $(BOARD).o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/gpio_hog.o
+endif
--- /dev/null
+#
+# Copyright (C) 2017 Allied Telesis Labs
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include "../common/gpio_hog.h"
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
+
+#define CONFIG_NVS_LOCATION 0xf4800000
+#define CONFIG_NVS_SIZE (512 << 10)
+
+static struct serdes_map board_serdes_map[] = {
+ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+ DEBUG_LEVEL_ERROR,
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1866M, /* speed_bin */
+ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
+ MV_DDR_DIE_CAP_4GBIT, /* die capacity */
+ MV_DDR_FREQ_933, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_2T} }, /* timing */
+ BUS_MASK_32BIT_ECC, /* subphys mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x00001111, MVEBU_MPP_BASE + 0x00);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+ writel(0x55000000, MVEBU_MPP_BASE + 0x08);
+ writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
+ writel(0x55555555, MVEBU_MPP_BASE + 0x10);
+ writel(0x00100565, MVEBU_MPP_BASE + 0x14);
+ writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+ writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* window for NVS */
+ mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+
+ /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
+ writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
+
+ return 0;
+}
+
+static int led_7seg_init(unsigned int segments)
+{
+ int node;
+ int ret;
+ int i;
+ struct gpio_desc desc[8];
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
+ "atl,of-led-7seg");
+ if (node < 0)
+ return -ENODEV;
+
+ ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+ "segment-gpios", desc,
+ ARRAY_SIZE(desc), GPIOD_IS_OUT);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(desc); i++) {
+ ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
+ led_en = {};
+
+ gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
+ gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
+ gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
+ gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
+
+#ifdef MTDPARTS_MTDOOPS
+ env_set("mtdoops", MTDPARTS_MTDOOPS);
+#endif
+
+ led_7seg_init(0xff);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board: " CONFIG_SYS_BOARD "\n");
+
+ return 0;
+}
+#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*/
#include <common.h>
enum fm_port port, int offset)
{
struct fixed_link f_link;
+ const u32 *handle;
+ const char *prop = NULL;
+ int off;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
switch (port) {
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
(port == FM1_10GEC1 || port == FM1_10GEC2)) {
- /* XFI interface */
- f_link.phy_id = cpu_to_fdt32(port);
- f_link.duplex = cpu_to_fdt32(1);
- f_link.link_speed = cpu_to_fdt32(10000);
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for XFI */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+ handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
+ prop = NULL;
+ if (handle) {
+ off = fdt_node_offset_by_phandle(fdt,
+ fdt32_to_cpu(*handle));
+ prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
+ }
+ if (!prop || strcmp(prop, "10gbase-kr")) {
+ /* XFI interface */
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(10000);
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "xgmii");
+ }
}
}
LS1088ARDB BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1088a/
F: include/configs/ls1088ardb.h
F: configs/ls1088ardb_qspi_defconfig
F: configs/ls1088ardb_sdcard_qspi_defconfig
+F: configs/ls1088ardb_tfa_defconfig
+F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
LS1088AQDS BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1088a/
F: include/configs/ls1088aqds.h
F: configs/ls1088aqds_sdcard_qspi_defconfig
F: configs/ls1088aqds_defconfig
F: configs/ls1088aqds_sdcard_ifc_defconfig
+F: configs/ls1088aqds_tfa_defconfig
LS1088AQDS_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+ return 0;
+}
+#else
int fsl_initdram(void)
{
puts("Initializing DDR....using SPD\n");
#endif
return 0;
}
+#endif /* CONFIG_TFABOOT */
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TARGET_LS1088AQDS
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nor0",
+ CONFIG_SYS_NOR0_CSPR_EARLY,
+ CONFIG_SYS_NOR0_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ 0,
+ CONFIG_SYS_NOR0_CSPR,
+ 0,
+ },
+ {
+ "nor1",
+ CONFIG_SYS_NOR1_CSPR_EARLY,
+ CONFIG_SYS_NOR0_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK_EARLY,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ 0,
+ CONFIG_SYS_NOR1_CSPR,
+ CONFIG_SYS_NOR_AMASK,
+ },
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "fpga",
+ CONFIG_SYS_FPGA_CSPR,
+ CONFIG_SYS_FPGA_CSPR_EXT,
+ SYS_FPGA_AMASK,
+ CONFIG_SYS_FPGA_CSOR,
+ {
+ SYS_FPGA_CS_FTIM0,
+ SYS_FPGA_CS_FTIM1,
+ SYS_FPGA_CS_FTIM2,
+ SYS_FPGA_CS_FTIM3
+ },
+ 0,
+ SYS_FPGA_CSPR_FINAL,
+ 0,
+ }
+};
+
+struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "reserved",
+ },
+ {
+ "fpga",
+ CONFIG_SYS_FPGA_CSPR,
+ CONFIG_SYS_FPGA_CSPR_EXT,
+ SYS_FPGA_AMASK,
+ CONFIG_SYS_FPGA_CSOR,
+ {
+ SYS_FPGA_CS_FTIM0,
+ SYS_FPGA_CS_FTIM1,
+ SYS_FPGA_CS_FTIM2,
+ SYS_FPGA_CS_FTIM3
+ },
+ 0,
+ SYS_FPGA_CSPR_FINAL,
+ 0,
+ }
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+ enum boot_src src = get_boot_src();
+
+ if (src == BOOT_SOURCE_QSPI_NOR)
+ regs_info->regs = ifc_cfg_qspi_nor_boot;
+ else
+ regs_info->regs = ifc_cfg_ifc_nor_boot;
+
+ regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+#endif /* CONFIG_TFABOOT */
+#endif /* CONFIG_TARGET_LS1088AQDS */
+
int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
#if !defined(CONFIG_SPL_BUILD)
int checkboard(void)
{
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+#endif
char buf[64];
u8 sw;
static const char *const freq[] = {"100", "125", "156.25",
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+#ifdef CONFIG_TFABOOT
+ if (src == BOOT_SOURCE_SD_MMC)
+ puts("SD card\n");
+#else
#ifdef CONFIG_SD_BOOT
puts("SD card\n");
#endif
+#endif /* CONFIG_TFABOOT */
switch (sw) {
#ifdef CONFIG_TARGET_LS1088AQDS
case 0:
return;
}
- if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
void fsl_fdt_fixup_flash(void *fdt)
{
int offset;
+#ifdef CONFIG_TFABOOT
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 val;
+#endif
/*
* IFC-NOR and QSPI are muxed on SoC.
* disable QSPI node in dts in case QSPI is not enabled.
*/
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+ bool disable_ifc = false;
+
+ switch (src) {
+ case BOOT_SOURCE_IFC_NOR:
+ disable_ifc = false;
+ break;
+ case BOOT_SOURCE_QSPI_NOR:
+ disable_ifc = true;
+ break;
+ default:
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+ if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+ disable_ifc = true;
+ break;
+ }
+
+ if (disable_ifc) {
+ offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/ifc/nor");
+ } else {
+ offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/quadspi");
+ }
+
+#else
#ifdef CONFIG_FSL_QSPI
offset = fdt_path_offset(fdt, "/soc/ifc/nor");
if (offset < 0)
offset = fdt_path_offset(fdt, "/quadspi");
+#endif
#endif
if (offset < 0)
return;
}
#endif
#endif /* defined(CONFIG_SPL_BUILD) */
+
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_MTD_NOR_FLASH
+int is_flash_available(void)
+{
+ char *env_hwconfig = env_get("hwconfig");
+ enum boot_src src = get_boot_src();
+ int is_nor_flash_available = 1;
+
+ switch (src) {
+ case BOOT_SOURCE_IFC_NOR:
+ is_nor_flash_available = 1;
+ break;
+ case BOOT_SOURCE_QSPI_NOR:
+ is_nor_flash_available = 0;
+ break;
+ /*
+ * In Case of SD boot,if qspi is defined in env_hwconfig
+ * disable nor flash probe.
+ */
+ default:
+ if (hwconfig_f("qspi", env_hwconfig))
+ is_nor_flash_available = 0;
+ break;
+ }
+ return is_nor_flash_available;
+}
+#endif
+
+void *env_sf_get_env_addr(void)
+{
+ return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
return;
}
- if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
{
}
#endif
+
+#ifdef CONFIG_TFABOOT
+void *env_sf_get_env_addr(void)
+{
+ return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
+}
+#endif
LS2080A BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
F: configs/ls2080aqds_nand_defconfig
F: configs/ls2080aqds_qspi_defconfig
F: configs/ls2080aqds_sdcard_defconfig
+F: configs/ls2088aqds_tfa_defconfig
LS2080A_SECURE_BOOT BOARD
#M: Saksham Jain <saksham.jain@nxp.freescale.com>
}
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
return 0;
}
+#endif /* CONFIG_TFABOOT */
return;
}
- if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
LS2088A_QSPI-boot BOARD
M: Priyanka Jain <priyanka.jain@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: configs/ls2088ardb_qspi_defconfig
+F: configs/ls2088ardb_tfa_defconfig
+F: configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
LS2081ARDB BOARD
M: Priyanka Jain <priyanka.jain@nxp.com>
}
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
return 0;
}
+#endif /* CONFIG_TFABOOT */
return;
}
- if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
void fsl_fdt_fixup_flash(void *fdt)
{
int offset;
+#ifdef CONFIG_TFABOOT
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 val;
+#endif
/*
* IFC and QSPI are muxed on board.
* So disable IFC node in dts if QSPI is enabled or
* disable QSPI node in dts in case QSPI is not enabled.
*/
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+ bool disable_ifc = false;
+
+ switch (src) {
+ case BOOT_SOURCE_IFC_NOR:
+ disable_ifc = false;
+ break;
+ case BOOT_SOURCE_QSPI_NOR:
+ disable_ifc = true;
+ break;
+ default:
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+ if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+ disable_ifc = true;
+ break;
+ }
+
+ if (disable_ifc) {
+ offset = fdt_path_offset(fdt, "/soc/ifc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/ifc");
+ } else {
+ offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/quadspi");
+ }
+
+#else
#ifdef CONFIG_FSL_QSPI
offset = fdt_path_offset(fdt, "/soc/ifc");
if (offset < 0)
offset = fdt_path_offset(fdt, "/quadspi");
#endif
+#endif
+
if (offset < 0)
return;
DECLARE_GLOBAL_DATA_PTR;
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
#define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
#define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
DECLARE_GLOBAL_DATA_PTR;
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK BIT(ETH_PHY_CTRL_POWER_DOWN_BIT)
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
return 0;
}
+
+int mmc_get_boot_dev(void)
+{
+ int g_mmc_devid = -1;
+ char *uflag = (char *)0x81DFFFF0;
+ if (strncmp(uflag,"eMMC",4)==0) {
+ g_mmc_devid = 0;
+ printf("Boot From Emmc(id:%d)\n\n", g_mmc_devid);
+ } else {
+ g_mmc_devid = 1;
+ printf("Boot From SD(id:%d)\n\n", g_mmc_devid);
+ }
+ return g_mmc_devid;
+}
+
+int mmc_get_env_dev(void)
+{
+ return mmc_get_boot_dev();
+}
#include <environment.h>
#include <spi.h>
#include <led.h>
+#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
BOARD_TYPE_PCB123,
};
+void mscc_switch_reset(bool enter)
+{
+ /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+ mscc_gpio_set_alternate(19, 2);
+
+ debug("applying SwC reset\n");
+
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
+ PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
+ pr_err("Tiemout while waiting for switch reset\n");
+
+ /*
+ * Reset GPIO19 mode back as regular GPIO, output, high (DDR
+ * not reset) (Order is important)
+ */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ mscc_gpio_set_alternate(19, 0);
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_SERVAL
+
+config SYS_BOARD
+ default "serval"
+
+config SYS_CONFIG_NAME
+ default "serval"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVAL) := serval.o
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+ BOARD_TYPE_PCB106 = 0xAABBCD00,
+ BOARD_TYPE_PCB105,
+};
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+ /* LED setup */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+static void do_board_detect(void)
+{
+ u16 gpio_in_reg;
+
+ /* Set MDIO and MDC */
+ mscc_gpio_set_alternate(9, 2);
+ mscc_gpio_set_alternate(10, 2);
+
+ /* Set GPIO page */
+ mscc_phy_wr(1, 16, 31, 0x10);
+ if (!mscc_phy_rd(1, 16, 15, &gpio_in_reg)) {
+ if (gpio_in_reg & 0x200)
+ gd->board_type = BOARD_TYPE_PCB106;
+ else
+ gd->board_type = BOARD_TYPE_PCB105;
+ mscc_phy_wr(1, 16, 15, 0);
+ } else {
+ gd->board_type = BOARD_TYPE_PCB105;
+ }
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB106 &&
+ strcmp(name, "serval_pcb106") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB105 &&
+ strcmp(name, "serval_pcb105") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_SERVALT
+
+config SYS_BOARD
+ default "servalt"
+
+config SYS_CONFIG_NAME
+ default "servalt"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVALT) := servalt.o
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+ BOARD_TYPE_PCB116 = 0xAABBCE00,
+};
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+ /* LED setup */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+static void do_board_detect(void)
+{
+ gd->board_type = BOARD_TYPE_PCB116; /* ServalT */
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB116 &&
+ strcmp(name, "servalt_pcb116") == 0)
+ return 0;
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
DECLARE_GLOBAL_DATA_PTR;
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-15t1-clearfog"
F: configs/am335x_boneblack_defconfig
F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
-F: configs/am335x_evm_nor_defconfig
-F: configs/am335x_evm_norboot_defconfig
-F: configs/am335x_evm_spiboot_defconfig
F: configs/am335x_evm_usbspl_defconfig
F: board/ti/am43xx/
F: include/configs/am43xx_evm.h
F: configs/am43xx_evm_defconfig
-F: configs/am43xx_evm_ethboot_defconfig
F: configs/am43xx_evm_qspiboot_defconfig
F: configs/am43xx_evm_usbhost_boot_defconfig
F: configs/am43xx_evm_rtconly_defconfig
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00030000U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
static unsigned long ps7_clock_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
- EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
- EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
- EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A03U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00200500U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB52U),
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
default "work_92105"
config CMD_HD44760
- bool "Enable 'hd44780' LCD-control comand"
+ bool "Enable 'hd44780' LCD-control command"
help
This controls the LCD driver.
"zynqmp mmio_write address mask value - write value after masking to\n"
" address\n"
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
- "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n"
- " initialized before accessing to avoid ECC\n"
- " errors. mode specifies in which mode TCM has\n"
- " to be initialized. Supported modes will be\n"
- " lock(0)/split(1)\n"
+ "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n"
+ " initialized before accessing to avoid ECC\n"
+ " errors. mode specifies in which mode TCM has\n"
+ " to be initialized. Supported modes will be\n"
+ " lock(0)/split(1)\n"
#endif
;
#endif
{
}
+#if defined(CONFIG_BOARD_LATE_INIT)
static const struct {
u32 bit;
const char *name;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@ff160000", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff160000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@ff170000", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff170000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
return 0;
}
+#endif
int checkboard(void)
{
}
#endif /* CONFIG_AUTO_COMPLETE */
-static char mtd_help_text[] =
#ifdef CONFIG_SYS_LONGHELP
+static char mtd_help_text[] =
"- generic operations on memory technology devices\n\n"
"mtd list\n"
"mtd read[.raw][.oob] <name> <addr> [<off> [<size>]]\n"
"\t\t* must be a multiple of a block for erase\n"
"\t\t* must be a multiple of a page otherwise (special case: default is a page with dump)\n"
"\n"
- "The .dontskipff option forces writing empty pages, don't use it if unsure.\n"
+ "The .dontskipff option forces writing empty pages, don't use it if unsure.\n";
#endif
- "";
U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils", mtd_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_mtd_list),
the relocation phase. The board function checkboard() is called to do
this.
+config BOUNCE_BUFFER
+ bool "Include bounce buffer API"
+ help
+ Some peripherals support DMA from a subset of physically
+ addressable memory only. To support such peripherals, the
+ bounce buffer API uses a temporary buffer: it copies data
+ to/from DMA regions while managing cache operations.
+
+ A second possible use of bounce buffers is their ability to
+ provide aligned buffers for DMA operations.
+
menu "Start-up hooks"
config ARCH_EARLY_INIT_R
default "tpl/u-boot-with-tpl.bin" if TPL
default "u-boot.bin"
help
- Payload for SPL boot. For backward compability, default to
+ Payload for SPL boot. For backward compatibility, default to
u-boot.bin, i.e. RAW image without any header. In case of
TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to
use u-boot.img.
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_SPL=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_NOR=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00080000
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_NAND=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x08000000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_NOR=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NOR_BOOT=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),4m(kernel),-(rootfs)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_DEVICE=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=m25p80-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=m25p80-flash.0:128k(SPL),512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),3464k(kernel),-(rootfs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),-(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
CONFIG_ENV_IS_IN_UBI=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
-CONFIG_OF_CONTROL=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS65910=y
CONFIG_CONS_INDEX=4
-CONFIG_SPI=y
# CONFIG_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50"
-CONFIG_OF_CONTROL=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MII=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_AM43XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x40000
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DM_ETH=y
# CONFIG_NETDEVICES is not set
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_ZYNQ_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_CMD_NVME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
+CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
# CONFIG_CMD_IMI is not set
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX6 # "
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_BOOTCOMMAND="echo SDP Display5 recovery"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HWECC=y
CONFIG_PHYLIB=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
CONFIG_UBIFS_SILENCE_MSG=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_BOUNCE_BUFFER=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
-CONFIG_DOS_PARTITION=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y
-CONFIG_FS_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_BOOTDELAY=1
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SECURE_BOOT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NR_DRAM_BANKS=3
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_MP=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SECURE_BOOT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NR_DRAM_BANKS=3
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NR_DRAM_BANKS=3
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_E1000=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_CONS_INDEX=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_LZMA=y
-CONFIG_XZ=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_DM_GPIO=y
-CONFIG_MTD=y
-CONFIG_MTD_SPI_NAND=y
CONFIG_MSCC_SGPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
+CONFIG_MSCC_OCELOT_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_DM_SERIAL=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_MSCC=y
+CONFIG_SOC_SERVAL=y
+CONFIG_DDRTYPE_H5TQ1G63BFA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="serval # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106"
+CONFIG_OF_LIST="serval_pcb106 serval_pcb105"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MSCC_BB_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_MSCC=y
+CONFIG_SOC_SERVALT=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="servalt # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="servalt_pcb116"
+CONFIG_OF_LIST="servalt_pcb116"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MSCC_BB_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_BLOCK_CACHE is not set
CONFIG_CLK=y
-CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_MTK=y
-CONFIG_DM_RESET=y
-CONFIG_RESET_MEDIATEK=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_MEDIATEK_ETH=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
# CONFIG_PARTITIONS is not set
-CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-parents"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_RESET=y
-CONFIG_RESET_MEDIATEK=y
CONFIG_DM_ETH=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NVME=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVPP2=y
+CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NVME=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVPP2=y
+CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg"
CONFIG_SPI_BOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
-CONFIG_UT_OVERLAY=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_FPGA_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Matrix U-Boot> "
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Titanium > "
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
-CONFIG_SYS_I2C_ZYNQ=y
-CONFIG_ZYNQ_I2C0=y
-CONFIG_ZYNQ_I2C1=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
-CONFIG_SYS_I2C_ZYNQ=y
-CONFIG_ZYNQ_I2C0=y
-CONFIG_ZYNQ_I2C1=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
-CONFIG_SYS_I2C_ZYNQ=y
-CONFIG_ZYNQ_I2C0=y
-CONFIG_ZYNQ_I2C1=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6s-wru4.dtb"
CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_MISC_INIT_R=y
CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
CONFIG_CMD_BTRFS=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_WATCHDOG=y
CONFIG_WDT=y
CONFIG_WDT_ARMADA_37XX=y
CONFIG_SHA1=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_TARGET_WARP7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_X530=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_NAND=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_MTD_UBI=y
+CONFIG_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
# CONFIG_EFI_LOADER is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_SF=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
CONFIG_SPL_DM=y
-# CONFIG_BLK is not set
CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_SF=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
CONFIG_SPL_DM=y
-# CONFIG_BLK is not set
CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_SF=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
CONFIG_SPL_DM=y
-# CONFIG_BLK is not set
CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_XILINX_GMII2RGMII=y
+CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_MTD_DEVICE=y
CONFIG_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_MAX_CHIPS=2
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MTD_DEVICE=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DM_ETH=y
# CONFIG_NETDEVICES is not set
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_ZYNQ_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C1=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ZYNQ_I2C1=y
CONFIG_MISC=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
+CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-dlc20-rev1.0"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
-CONFIG_SYS_I2C_ZYNQ=y
-CONFIG_ZYNQ_I2C0=y
-CONFIG_ZYNQ_I2C1=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
-CONFIG_SYS_I2C_ZYNQ=y
-CONFIG_ZYNQ_I2C0=y
-CONFIG_ZYNQ_I2C1=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
return name;
}
-static efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
+static const efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
static inline int is_bootable(gpt_entry *p)
{
2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
It only can be 512 or 1024.
-Take AT91SAM9X5EK as an example, the board definition file likes:
+Take 'configs/at91sam9x5ek_nandflash_defconfig' as an example, the board
+configuration file has the following entries:
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC 1
-#define CONFIG_ATMEL_NAND_HW_PMECC 1
-#define CONFIG_PMECC_CAP 2
-#define CONFIG_PMECC_SECTOR_SIZE 512
+ CONFIG_PMECC_CAP=2
+ CONFIG_PMECC_SECTOR_SIZE=512
+ CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
How to enable PMECC header for direct programmable boot.bin
-----------------------------------------------------------
look like. In order to do so we have a new image type added to mkimage to
generate this PMECC header and integrated this into the build process of SPL.
-To enable the generation of atmel PMECC header for SPL one need to define
+To enable the generation of atmel PMECC header for SPL one needs to define
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from
board configuration and compiled into the host tools atmel_pmecc_params. This
tool will be called in build process to parametrize mkimage for atmelimage
Is this option is enabled then support for the ISA bus will
be included for addresses read from DT. This is something that
should be known to be required or not based upon the board
- being targetted, and whether or not it makes use of an ISA bus.
+ being targeted, and whether or not it makes use of an ISA bus.
The bus is matched based upon its node name equalling "isa". The
busses #address-cells should equal 2, with the first cell being
(u32)bsize, 0, ret_payload);
if (ret)
- debug("PL FPGA LOAD fail\n");
+ puts("PL FPGA LOAD fail\n");
return ret;
}
config SYS_I2C_MXC
bool "NXP MXC I2C driver"
help
- Add support for the NXP I2C driver. This supports upto for bus
- channels and operating on standard mode upto 100 kbits/s and fast
- mode upto 400 kbits/s.
+ Add support for the NXP I2C driver. This supports up to four bus
+ channels and operating on standard mode up to 100 kbits/s and fast
+ mode up to 400 kbits/s.
if SYS_I2C_MXC
config SYS_I2C_MXC_I2C1
help
Add support for the Rockchip I2C driver. This is used with various
Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
- have several I2C ports and all are provided, controled by the
+ have several I2C ports and all are provided, controlled by the
device tree.
config SYS_I2C_SANDBOX
struct clk clk;
int ret;
- i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
+ i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
if (!i2c_bus->regs)
return -ENOMEM;
#include <common.h>
#include <fsl_ifc.h>
+#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"cs0",
regs_info->regs = ifc_cfg_default_boot;
regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
}
+#endif
void print_ifc_regs(void)
{
}
}
+#ifdef CONFIG_TFABOOT
void init_early_memctl_regs(void)
{
int i, j;
regs[i].amask);
}
}
+#else
+void init_early_memctl_regs(void)
+{
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+ set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+
+#ifndef CONFIG_A003399_NOR_WORKAROUND
+#ifdef CONFIG_SYS_CSPR0_EXT
+ set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR0_EXT
+ set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#endif
+ set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+ set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+ set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_CSPR1_EXT
+ set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR1_EXT
+ set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+ set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+
+ set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
+ set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
+ set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+#endif
+
+#ifdef CONFIG_SYS_CSPR2_EXT
+ set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR2_EXT
+ set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+ set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+
+ set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
+ set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+ set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+#endif
+
+#ifdef CONFIG_SYS_CSPR3_EXT
+ set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR3_EXT
+ set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
+ set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+
+ set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
+ set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+ set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+#endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+ set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR4_EXT
+ set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+ set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+ set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+ set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+ set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+ set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR5_EXT
+ set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+ set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+ set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+ set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+ set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+ set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR6_EXT
+ set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+ set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+ set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+ set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+ set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+ set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR7_EXT
+ set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+ set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+ set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+ set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+ set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
+}
+
+void init_final_memctl_regs(void)
+{
+#ifdef CONFIG_SYS_CSPR0_FINAL
+ set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK0_FINAL
+ set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#endif
+#ifdef CONFIG_SYS_CSPR1_FINAL
+ set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK1_FINAL
+ set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
+#endif
+#ifdef CONFIG_SYS_CSPR2_FINAL
+ set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK2_FINAL
+ set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#endif
+#ifdef CONFIG_SYS_CSPR3_FINAL
+ set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
+#endif
+#ifdef CONFIG_SYS_AMASK3_FINAL
+ set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#endif
+}
+#endif
config MMC_DW
bool "Synopsys DesignWare Memory Card Interface"
+ select BOUNCE_BUFFER
help
This selects support for the Synopsys DesignWare Mobile Storage IP
block, this provides host support for SD and MMC interfaces, in both
config MMC_MXS
bool "Freescale MXS Multimedia Card Interface support"
depends on MX23 || MX28 || MX6 || MX7
+ select BOUNCE_BUFFER
select APBH_DMA
select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
config MMC_SDHCI_TEGRA
bool "SDHCI platform support for the Tegra SD/MMC Controller"
depends on TEGRA
+ select BOUNCE_BUFFER
default y
help
This selects the Tegra SD/MMC controller. If you have a Tegra
{
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- return true;
return esdhc_getcd_common(priv);
}
u8 deviceid;
u8 bank;
u8 no_1p8;
- bool pwrseq;
};
#if defined(CONFIG_ARCH_ZYNQMP)
Enable this driver for NAND flash platforms using an Atmel NAND
controller.
+if NAND_ATMEL
+
+config ATMEL_NAND_HWECC
+ bool "Atmel Hardware ECC"
+ default n
+
+config ATMEL_NAND_HW_PMECC
+ bool "Atmel Programmable Multibit ECC (PMECC)"
+ select ATMEL_NAND_HWECC
+ default n
+ help
+ The Programmable Multibit ECC (PMECC) controller is a programmable
+ binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
+
+config PMECC_CAP
+ int "PMECC Correctable ECC Bits"
+ depends on ATMEL_NAND_HW_PMECC
+ default 2
+ help
+ Correctable ECC bits, can be 2, 4, 8, 12, and 24.
+
+config PMECC_SECTOR_SIZE
+ int "PMECC Sector Size"
+ depends on ATMEL_NAND_HW_PMECC
+ default 512
+ help
+ Sector size, in bytes, can be 512 or 1024.
+
+config SPL_GENERATE_ATMEL_PMECC_HEADER
+ bool "Atmel PMECC Header Generation"
+ select ATMEL_NAND_HWECC
+ select ATMEL_NAND_HW_PMECC
+ default n
+ help
+ Generate Programmable Multibit ECC (PMECC) header for SPL image.
+
+endif
+
config NAND_DAVINCI
bool "Support TI Davinci NAND controller"
help
not available while configuring controller. So a static CONFIG_NAND_xx
is needed to know the device's bus-width in advance.
+config SYS_NAND_MAX_CHIPS
+ int "NAND max chips"
+ default 1
+ depends on NAND_ARASAN
+ help
+ The maximum number of NAND chips per device to be supported.
+
if SPL
config SYS_NAND_U_BOOT_LOCATIONS
#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
#define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
+#define ARASAN_NAND_MEM_ADDR2_CS0_MASK (0x3 << 30)
+#define ARASAN_NAND_MEM_ADDR2_CS1_MASK (0x1 << 30)
#define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
#define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
{
+ u32 reg_val;
+
+ reg_val = readl(&arasan_nand_base->memadr_reg2);
+ if (chip == 0) {
+ reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK;
+ writel(reg_val, &arasan_nand_base->memadr_reg2);
+ } else if (chip == 1) {
+ reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK;
+ writel(reg_val, &arasan_nand_base->memadr_reg2);
+ }
}
static void arasan_nand_enable_ecc(void)
reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
writel(reg_val, &arasan_nand_base->memadr_reg2);
- reg_val = readl(&arasan_nand_base->memadr_reg2);
- reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
- writel(reg_val, &arasan_nand_base->memadr_reg2);
return 0;
}
reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
writel(reg_val, &arasan_nand_base->memadr_reg2);
- reg_val = readl(&arasan_nand_base->memadr_reg2);
- reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
- writel(reg_val, &arasan_nand_base->memadr_reg2);
writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
while (!(readl(&arasan_nand_base->intsts_reg) &
reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
writel(reg_val, &arasan_nand_base->pkt_reg);
- reg_val = readl(&arasan_nand_base->memadr_reg2);
- reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
- writel(reg_val, &arasan_nand_base->memadr_reg2);
-
writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
while (!(readl(&arasan_nand_base->intsts_reg) &
ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
writel(reg_val, &arasan_nand_base->memadr_reg2);
- reg_val = readl(&arasan_nand_base->memadr_reg2);
- reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
- writel(reg_val, &arasan_nand_base->memadr_reg2);
buf_index = 0;
return 0;
writel(0x0, &arasan_nand_base->pgm_reg);
/* first scan to find the device and get the page size */
- if (nand_scan_ident(mtd, 1, NULL)) {
+ if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) {
printf("%s: nand_scan_ident failed\n", __func__);
goto fail;
}
This driver implements support for the Socionext AVE Ethernet
controller, as found on the Socionext UniPhier family.
+config MSCC_OCELOT_SWITCH
+ bool "Ocelot switch driver"
+ depends on DM_ETH && ARCH_MSCC
+ select PHYLIB
+ help
+ This driver supports the Ocelot network switch device.
+
config ETHER_ON_FEC1
bool "FEC1"
depends on MPC8XX_FEC
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
return -EPERM;
}
- length = max(length, ETH_ZLEN);
-
memcpy((void *)data_start, packet, length);
+ if (length < ETH_ZLEN) {
+ memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
+ length = ETH_ZLEN;
+ }
/* Flush data to be sent */
flush_dcache_range(data_start, data_end);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
- desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
- DESC_TXCTRL_SIZE1MASK;
+ desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
+ ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK);
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
- desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
- DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
- DESC_TXCTRL_TXFIRST;
+ desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
+ ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
+ DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
return mc_dpl_applied;
}
+int is_lazy_dpl_addr_valid(void)
+{
+ return !!mc_lazy_dpl_addr;
+}
+
/*
* Return the MC address of private DRAM block.
* As per MC design document, MC initial base address
{
struct eth_pdata *pdata = dev_get_platdata(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
+ if (!pdata->iobase)
+ return -EINVAL;
return macb_late_eth_ofdata_to_platdata(dev);
}
phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
- return -EINVAL;
- }
+ else
+ pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
dmvgbe->phy_interface = pdata->phy_interface;
#include <asm/arch/soc.h>
#include <linux/compat.h>
#include <linux/mbus.h>
+#include <asm-generic/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
int init;
int phyaddr;
struct phy_device *phydev;
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc phy_reset_gpio;
+#endif
struct mii_dev *bus;
};
if (ret)
return ret;
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &pp->phy_reset_gpio, GPIOD_IS_OUT);
+
+ if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
+ dm_gpio_set_value(&pp->phy_reset_gpio, 1);
+ mdelay(10);
+ dm_gpio_set_value(&pp->phy_reset_gpio, 0);
+ }
+#endif
+
return board_network_enable(bus);
}
void __iomem *base;
void __iomem *lms_base;
void __iomem *iface_base;
- void __iomem *mdio_base;
void __iomem *mpcs_base;
void __iomem *xpcs_base;
/* Maximum number of RXQs per port */
unsigned int max_port_rxqs;
- struct mii_dev *bus;
-
int probe_done;
u8 num_ports;
};
/* Per-port registers' base address */
void __iomem *base;
+ void __iomem *mdio_base;
struct mvpp2_rx_queue **rxqs;
struct mvpp2_tx_queue **txqs;
phy_interface_t phy_interface;
int phy_node;
int phyaddr;
+ struct mii_dev *bus;
#ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
struct gpio_desc phy_tx_disable_gpio;
struct phy_device *phy_dev;
if (!port->init || port->link == 0) {
- phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
+ phy_dev = phy_connect(port->bus, port->phyaddr, dev,
port->phy_interface);
port->phy_dev = phy_dev;
if (!phy_dev) {
{
int port_node = dev_of_offset(dev);
const char *phy_mode_str;
- int phy_node, mdio_off, cp_node;
+ int phy_node;
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
- phys_addr_t mdio_addr;
+
+ /* Default mdio_base from the same eth base */
+ if (port->priv->hw_version == MVPP21)
+ port->mdio_base = port->priv->lms_base + MVPP21_SMI;
+ else
+ port->mdio_base = port->priv->iface_base + MVPP22_SMI;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
if (phy_node > 0) {
+ ofnode phy_ofnode;
+ fdt_addr_t phy_base;
+
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
if (phyaddr < 0) {
dev_err(&pdev->dev, "could not find phy address\n");
return -1;
}
- mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
-
- /* TODO: This WA for mdio issue. U-boot 2017 don't have
- * mdio driver and on MACHIATOBin board ports from CP1
- * connected to mdio on CP0.
- * WA is to get mdio address from phy handler parent
- * base address. WA should be removed after
- * mdio driver implementation.
- */
- mdio_addr = fdtdec_get_uint(gd->fdt_blob,
- mdio_off, "reg", 0);
-
- cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
- mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
- cp_node);
- port->priv->mdio_base = (void *)mdio_addr;
+ phy_ofnode = ofnode_get_parent(offset_to_ofnode(phy_node));
+ phy_base = ofnode_get_addr(phy_ofnode);
+ port->mdio_base = (void *)phy_base;
- if (port->priv->mdio_base < 0) {
+ if (port->mdio_base < 0) {
dev_err(&pdev->dev, "could not find mdio base address\n");
return -1;
}
/* SMI / MDIO functions */
-static int smi_wait_ready(struct mvpp2 *priv)
+static int smi_wait_ready(struct mvpp2_port *priv)
{
u32 timeout = MVPP2_SMI_TIMEOUT;
u32 smi_reg;
*/
static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct mvpp2 *priv = bus->priv;
+ struct mvpp2_port *priv = bus->priv;
u32 smi_reg;
u32 timeout;
static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 value)
{
- struct mvpp2 *priv = bus->priv;
+ struct mvpp2_port *priv = bus->priv;
u32 smi_reg;
/* check parameters */
static int mvpp2_base_probe(struct udevice *dev)
{
struct mvpp2 *priv = dev_get_priv(dev);
- struct mii_dev *bus;
void *bd_space;
u32 size = 0;
int i;
priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(priv->lms_base))
return PTR_ERR(priv->lms_base);
-
- priv->mdio_base = priv->lms_base + MVPP21_SMI;
} else {
priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
- priv->mdio_base = priv->iface_base + MVPP22_SMI;
-
/* Store common base addresses for all ports */
priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
else
priv->max_port_rxqs = 32;
- /* Finally create and register the MDIO bus driver */
- bus = mdio_alloc();
- if (!bus) {
- printf("Failed to allocate MDIO bus\n");
- return -ENOMEM;
- }
-
- bus->read = mpp2_mdio_read;
- bus->write = mpp2_mdio_write;
- snprintf(bus->name, sizeof(bus->name), dev->name);
- bus->priv = (void *)priv;
- priv->bus = bus;
-
- return mdio_register(bus);
+ return 0;
}
static int mvpp2_probe(struct udevice *dev)
{
struct mvpp2_port *port = dev_get_priv(dev);
struct mvpp2 *priv = dev_get_priv(dev->parent);
+ struct mii_dev *bus;
int err;
/* Only call the probe function for the parent once */
port->priv = dev_get_priv(dev->parent);
+ /* Create and register the MDIO bus driver */
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mpp2_mdio_read;
+ bus->write = mpp2_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)port;
+ port->bus = bus;
+
+ err = mdio_register(bus);
+ if (err)
+ return err;
+
err = phy_info_parse(dev, port);
if (err)
return err;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/of_addr.h>
+#include <fdt_support.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <miiphy.h>
+#include <net.h>
+#include <wait_bit.h>
+
+#define MIIM_STATUS 0x0
+#define MIIM_STAT_BUSY BIT(3)
+#define MIIM_CMD 0x8
+#define MIIM_CMD_SCAN BIT(0)
+#define MIIM_CMD_OPR_WRITE BIT(1)
+#define MIIM_CMD_OPR_READ BIT(2)
+#define MIIM_CMD_SINGLE_SCAN BIT(3)
+#define MIIM_CMD_WRDATA(x) ((x) << 4)
+#define MIIM_CMD_REGAD(x) ((x) << 20)
+#define MIIM_CMD_PHYAD(x) ((x) << 25)
+#define MIIM_CMD_VLD BIT(31)
+#define MIIM_DATA 0xC
+#define MIIM_DATA_ERROR (0x2 << 16)
+
+#define PHY_CFG 0x0
+#define PHY_CFG_ENA 0xF
+#define PHY_CFG_COMMON_RST BIT(4)
+#define PHY_CFG_RST (0xF << 5)
+#define PHY_STAT 0x4
+#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
+
+#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
+#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
+#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
+#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
+#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
+#define ANA_TABLES_MACHDATA 0x8b34
+#define ANA_TABLES_MACLDATA 0x8b38
+#define ANA_TABLES_MACACCESS 0x8b3c
+#define ANA_TABLES_MACACCESS_VALID BIT(11)
+#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
+#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
+#define MACACCESS_CMD_IDLE 0
+#define MACACCESS_CMD_LEARN 1
+#define MACACCESS_CMD_GET_NEXT 4
+#define ANA_PGID(x) (0x8c00 + 4 * (x))
+
+#define SYS_FRM_AGING 0x574
+#define SYS_FRM_AGING_ENA BIT(20)
+
+#define SYS_SYSTEM_RST_CFG 0x508
+#define SYS_SYSTEM_RST_MEM_INIT BIT(0)
+#define SYS_SYSTEM_RST_MEM_ENA BIT(1)
+#define SYS_SYSTEM_RST_CORE_ENA BIT(2)
+#define SYS_PORT_MODE(x) (0x514 + 0x4 * (x))
+#define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3)
+#define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
+#define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1)
+#define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
+#define SYS_PAUSE_CFG(x) (0x608 + 0x4 * (x))
+#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
+
+#define QSYS_SWITCH_PORT_MODE(x) (0x11234 + 0x4 * (x))
+#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
+#define QSYS_QMAP 0x112d8
+#define QSYS_EGR_NO_SHARING 0x1129c
+
+/* Port registers */
+#define DEV_CLOCK_CFG 0x0
+#define DEV_CLOCK_CFG_LINK_SPEED_1000 1
+#define DEV_MAC_ENA_CFG 0x1c
+#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
+#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
+
+#define DEV_MAC_IFG_CFG 0x30
+#define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
+#define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
+#define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
+
+#define PCS1G_CFG 0x48
+#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
+#define PCS1G_MODE_CFG 0x4c
+#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
+#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
+#define PCS1G_SD_CFG 0x50
+#define PCS1G_ANEG_CFG 0x54
+#define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
+
+#define QS_XTR_GRP_CFG(x) (4 * (x))
+#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
+#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
+#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_XTR_RD(x) (0x8 + 4 * (x))
+#define QS_XTR_FLUSH 0x18
+#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
+#define QS_XTR_DATA_PRESENT 0x1c
+#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
+#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
+#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_INJ_WR(x) (0x2c + 4 * (x))
+#define QS_INJ_CTRL(x) (0x34 + 4 * (x))
+#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
+#define QS_INJ_CTRL_EOF BIT(19)
+#define QS_INJ_CTRL_SOF BIT(18)
+#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
+
+#define XTR_EOF_0 ntohl(0x80000000u)
+#define XTR_EOF_1 ntohl(0x80000001u)
+#define XTR_EOF_2 ntohl(0x80000002u)
+#define XTR_EOF_3 ntohl(0x80000003u)
+#define XTR_PRUNED ntohl(0x80000004u)
+#define XTR_ABORT ntohl(0x80000005u)
+#define XTR_ESCAPE ntohl(0x80000006u)
+#define XTR_NOT_READY ntohl(0x80000007u)
+
+#define IFH_INJ_BYPASS BIT(31)
+#define IFH_TAG_TYPE_C 0
+#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
+#define MAC_VID 1
+#define CPU_PORT 11
+#define INTERNAL_PORT_MSK 0xF
+#define IFH_LEN 4
+#define OCELOT_BUF_CELL_SZ 60
+#define ETH_ALEN 6
+#define PGID_BROADCAST 13
+#define PGID_UNICAST 14
+#define PGID_SRC 80
+
+enum ocelot_target {
+ ANA,
+ QS,
+ QSYS,
+ REW,
+ SYS,
+ HSIO,
+ PORT0,
+ PORT1,
+ PORT2,
+ PORT3,
+ TARGET_MAX,
+};
+
+#define MAX_PORT (PORT3 - PORT0)
+
+/* MAC table entry types.
+ * ENTRYTYPE_NORMAL is subject to aging.
+ * ENTRYTYPE_LOCKED is not subject to aging.
+ * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
+ * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
+ */
+enum macaccess_entry_type {
+ ENTRYTYPE_NORMAL = 0,
+ ENTRYTYPE_LOCKED,
+ ENTRYTYPE_MACv4,
+ ENTRYTYPE_MACv6,
+};
+
+enum ocelot_mdio_target {
+ MIIM,
+ PHY,
+ TARGET_MDIO_MAX,
+};
+
+enum ocelot_phy_id {
+ INTERNAL,
+ EXTERNAL,
+ NUM_PHY,
+};
+
+struct ocelot_private {
+ void __iomem *regs[TARGET_MAX];
+
+ struct mii_dev *bus[NUM_PHY];
+ struct phy_device *phydev;
+ int phy_mode;
+ int max_speed;
+
+ int rx_pos;
+ int rx_siz;
+ int rx_off;
+ int tx_num;
+
+ u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
+ void *tx_adj_buf;
+};
+
+struct mscc_miim_dev {
+ void __iomem *regs;
+ void __iomem *phy_regs;
+};
+
+struct mscc_miim_dev miim[NUM_PHY];
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
+ false, 250, false);
+}
+
+static int mscc_miim_reset(struct mii_dev *bus)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+
+ if (miim->phy_regs) {
+ writel(0, miim->phy_regs + PHY_CFG);
+ writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
+ | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);
+ mdelay(500);
+ }
+
+ return 0;
+}
+
+static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
+ miim->regs + MIIM_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + MIIM_DATA);
+ if (val & MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0xFFFF;
+ out:
+ return ret;
+}
+
+static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
+ MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
+ out:
+ return ret;
+}
+
+/* For now only setup the internal mdio bus */
+static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
+{
+ unsigned long phy_size[TARGET_MAX];
+ phys_addr_t phy_base[TARGET_MAX];
+ struct ofnode_phandle_args phandle;
+ ofnode eth_node, node, mdio_node;
+ struct resource res;
+ struct mii_dev *bus;
+ fdt32_t faddr;
+ int i;
+
+ bus = mdio_alloc();
+
+ if (!bus)
+ return NULL;
+
+ /* gathered only the first mdio bus */
+ eth_node = dev_read_first_subnode(dev);
+ node = ofnode_first_subnode(eth_node);
+ ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
+ &phandle);
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ for (i = 0; i < TARGET_MDIO_MAX; i++) {
+ if (ofnode_read_resource(mdio_node, i, &res)) {
+ pr_err("%s: get OF resource failed\n", __func__);
+ return NULL;
+ }
+ faddr = cpu_to_fdt32(res.start);
+ phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
+ phy_size[i] = res.end - res.start;
+ }
+
+ strcpy(bus->name, "miim-internal");
+ miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
+ miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
+ bus->priv = &miim[INTERNAL];
+ bus->reset = mscc_miim_reset;
+ bus->read = mscc_miim_read;
+ bus->write = mscc_miim_write;
+
+ if (mdio_register(bus))
+ return NULL;
+ else
+ return bus;
+}
+
+__weak void mscc_switch_reset(void)
+{
+}
+
+static void ocelot_stop(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ int i;
+
+ mscc_switch_reset();
+ for (i = 0; i < NUM_PHY; i++)
+ if (priv->bus[i])
+ mscc_miim_reset(priv->bus[i]);
+}
+
+static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
+{
+ int i;
+
+ /* map the 8 CPU extraction queues to CPU port 11 */
+ writel(0, priv->regs[QSYS] + QSYS_QMAP);
+
+ for (i = 0; i <= 1; i++) {
+ /*
+ * Do byte-swap and expect status after last data word
+ * Extraction: Mode: manual extraction) | Byte_swap
+ */
+ writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
+ priv->regs[QS] + QS_XTR_GRP_CFG(i));
+ /*
+ * Injection: Mode: manual extraction | Byte_swap
+ */
+ writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
+ priv->regs[QS] + QS_INJ_GRP_CFG(i));
+ }
+
+ for (i = 0; i <= 1; i++)
+ /* Enable IFH insertion/parsing on CPU ports */
+ writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
+ SYS_PORT_MODE_INCL_XTR_HDR(1),
+ priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
+ /*
+ * Setup the CPU port as VLAN aware to support switching frames
+ * based on tags
+ */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
+
+ /* Disable learning (only RECV_ENA must be set) */
+ writel(ANA_PORT_PORT_CFG_RECV_ENA,
+ priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
+
+ /* Enable switching to/from cpu port */
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
+ QSYS_SWITCH_PORT_MODE_PORT_ENA);
+
+ /* No pause on CPU port - not needed (off by default) */
+ clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
+ SYS_PAUSE_CFG_PAUSE_ENA);
+
+ setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
+}
+
+static void ocelot_port_init(struct ocelot_private *priv, int port)
+{
+ void __iomem *regs = priv->regs[port];
+
+ /* Enable PCS */
+ writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
+
+ /* Disable Signal Detect */
+ writel(0, regs + PCS1G_SD_CFG);
+
+ /* Enable MAC RX and TX */
+ writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
+ regs + DEV_MAC_ENA_CFG);
+
+ /* Clear sgmii_mode_ena */
+ writel(0, regs + PCS1G_MODE_CFG);
+
+ /*
+ * Clear sw_resolve_ena(bit 0) and set adv_ability to
+ * something meaningful just in case
+ */
+ writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
+
+ /* Set MAC IFG Gaps */
+ writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
+ DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
+
+ /* Set link speed and release all resets */
+ writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+
+ /* Enable the port in the core */
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),
+ QSYS_SWITCH_PORT_MODE_PORT_ENA);
+}
+
+static int ocelot_switch_init(struct ocelot_private *priv)
+{
+ /* Reset switch & memories */
+ writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
+ priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
+
+ /* Wait to complete */
+ if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
+ pr_err("Timeout in memory reset\n");
+ return -EIO;
+ }
+
+ /* Enable switch core */
+ setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_CORE_ENA);
+
+ return 0;
+}
+
+static void ocelot_switch_flush(struct ocelot_private *priv)
+{
+ /* All Queues flush */
+ setbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
+ /* Allow to drain */
+ mdelay(1);
+ /* All Queues normal */
+ clrbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
+}
+
+static int ocelot_initialize(struct ocelot_private *priv)
+{
+ int ret, i;
+
+ /* Initialize switch memories, enable core */
+ ret = ocelot_switch_init(priv);
+ if (ret)
+ return ret;
+ /*
+ * Disable port-to-port by switching
+ * Put fron ports in "port isolation modes" - i.e. they cant send
+ * to other ports - via the PGID sorce masks.
+ */
+ for (i = 0; i <= MAX_PORT; i++)
+ writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
+
+ /* Flush queues */
+ ocelot_switch_flush(priv);
+
+ /* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
+ writel(SYS_FRM_AGING_ENA | (20000000 / 65),
+ priv->regs[SYS] + SYS_FRM_AGING);
+
+ for (i = PORT0; i <= PORT3; i++)
+ ocelot_port_init(priv, i);
+
+ ocelot_cpu_capture_setup(priv);
+
+ debug("Ports enabled\n");
+
+ return 0;
+}
+
+static inline int ocelot_vlant_wait_for_completion(struct ocelot_private *priv)
+{
+ unsigned int val, timeout = 10;
+
+ /* Wait for the issued mac table command to be completed, or timeout.
+ * When the command read from ANA_TABLES_MACACCESS is
+ * MACACCESS_CMD_IDLE, the issued command completed successfully.
+ */
+ do {
+ val = readl(priv->regs[ANA] + ANA_TABLES_MACACCESS);
+ val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
+ } while (val != MACACCESS_CMD_IDLE && timeout--);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int ocelot_mac_table_add(struct ocelot_private *priv,
+ const unsigned char mac[ETH_ALEN], int pgid)
+{
+ u32 macl = 0, mach = 0;
+ int ret;
+
+ /* Set the MAC address to handle and the vlan associated in a format
+ * understood by the hardware.
+ */
+ mach |= MAC_VID << 16;
+ mach |= ((u32)mac[0]) << 8;
+ mach |= ((u32)mac[1]) << 0;
+ macl |= ((u32)mac[2]) << 24;
+ macl |= ((u32)mac[3]) << 16;
+ macl |= ((u32)mac[4]) << 8;
+ macl |= ((u32)mac[5]) << 0;
+
+ writel(macl, priv->regs[ANA] + ANA_TABLES_MACLDATA);
+ writel(mach, priv->regs[ANA] + ANA_TABLES_MACHDATA);
+
+ writel(ANA_TABLES_MACACCESS_VALID |
+ ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
+ ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
+ ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
+ priv->regs[ANA] + ANA_TABLES_MACACCESS);
+
+ ret = ocelot_vlant_wait_for_completion(priv);
+
+ return ret;
+}
+
+static int ocelot_write_hwaddr(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int ocelot_start(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff };
+ int ret;
+
+ ret = ocelot_initialize(priv);
+ if (ret)
+ return ret;
+
+ /* Set MAC address tables entries for CPU redirection */
+ ocelot_mac_table_add(priv, mac, PGID_BROADCAST);
+
+ writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
+ priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
+
+ /* It should be setup latter in ocelot_write_hwaddr */
+ ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int ocelot_send(struct udevice *dev, void *packet, int length)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ u32 ifh[IFH_LEN];
+ int port = BIT(0); /* use port 0 */
+ u8 grp = 0; /* Send everything on CPU group 0 */
+ int i, count = (length + 3) / 4, last = length % 4;
+ u32 *buf = packet;
+
+ writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
+ priv->regs[QS] + QS_INJ_CTRL(grp));
+
+ /*
+ * Generate the IFH for frame injection
+ *
+ * The IFH is a 128bit-value
+ * bit 127: bypass the analyzer processing
+ * bit 56-67: destination mask
+ * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
+ * bit 20-27: cpu extraction queue mask
+ * bit 16: tag type 0: C-tag, 1: S-tag
+ * bit 0-11: VID
+ */
+ ifh[0] = IFH_INJ_BYPASS;
+ ifh[1] = (0xf00 & port) >> 8;
+ ifh[2] = (0xff & port) << 24;
+ ifh[3] = (IFH_TAG_TYPE_C << 16);
+
+ for (i = 0; i < IFH_LEN; i++)
+ writel(ifh[i], priv->regs[QS] + QS_INJ_WR(grp));
+
+ for (i = 0; i < count; i++)
+ writel(buf[i], priv->regs[QS] + QS_INJ_WR(grp));
+
+ /* Add padding */
+ while (i < (OCELOT_BUF_CELL_SZ / 4)) {
+ writel(0, priv->regs[QS] + QS_INJ_WR(grp));
+ i++;
+ }
+
+ /* Indicate EOF and valid bytes in last word */
+ writel(QS_INJ_CTRL_GAP_SIZE(1) |
+ QS_INJ_CTRL_VLD_BYTES(length < OCELOT_BUF_CELL_SZ ? 0 : last) |
+ QS_INJ_CTRL_EOF, priv->regs[QS] + QS_INJ_CTRL(grp));
+
+ /* Add dummy CRC */
+ writel(0, priv->regs[QS] + QS_INJ_WR(grp));
+
+ return 0;
+}
+
+static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ u8 grp = 0; /* Send everything on CPU group 0 */
+ u32 *rxbuf = (u32 *)net_rx_packets[0];
+ int i, byte_cnt = 0;
+ bool eof_flag = false, pruned_flag = false, abort_flag = false;
+
+ if (!(readl(priv->regs[QS] + QS_XTR_DATA_PRESENT) & BIT(grp)))
+ return -EAGAIN;
+
+ /* skip IFH */
+ for (i = 0; i < IFH_LEN; i++)
+ readl(priv->regs[QS] + QS_XTR_RD(grp));
+
+ while (!eof_flag) {
+ u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
+
+ switch (val) {
+ case XTR_NOT_READY:
+ debug("%d NOT_READY...?\n", byte_cnt);
+ break;
+ case XTR_ABORT:
+ /* really nedeed?? not done in linux */
+ *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ abort_flag = true;
+ eof_flag = true;
+ debug("XTR_ABORT\n");
+ break;
+ case XTR_EOF_0:
+ case XTR_EOF_1:
+ case XTR_EOF_2:
+ case XTR_EOF_3:
+ byte_cnt += XTR_VALID_BYTES(val);
+ *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ eof_flag = true;
+ debug("EOF\n");
+ break;
+ case XTR_PRUNED:
+ /* But get the last 4 bytes as well */
+ eof_flag = true;
+ pruned_flag = true;
+ debug("PRUNED\n");
+ /* fallthrough */
+ case XTR_ESCAPE:
+ *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ byte_cnt += 4;
+ rxbuf++;
+ debug("ESCAPED\n");
+ break;
+ default:
+ *rxbuf = val;
+ byte_cnt += 4;
+ rxbuf++;
+ }
+ }
+
+ if (abort_flag || pruned_flag || !eof_flag) {
+ debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
+ abort_flag, pruned_flag, eof_flag);
+ return -EAGAIN;
+ }
+
+ *packetp = net_rx_packets[0];
+
+ return byte_cnt;
+}
+
+static int ocelot_probe(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ int ret, i;
+
+ struct {
+ enum ocelot_target id;
+ char *name;
+ } reg[] = {
+ { SYS, "sys" },
+ { REW, "rew" },
+ { QSYS, "qsys" },
+ { ANA, "ana" },
+ { QS, "qs" },
+ { HSIO, "hsio" },
+ { PORT0, "port0" },
+ { PORT1, "port1" },
+ { PORT2, "port2" },
+ { PORT3, "port3" },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(reg); i++) {
+ priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
+ if (!priv->regs[reg[i].id]) {
+ pr_err
+ ("Error %d: can't get regs base addresses for %s\n",
+ ret, reg[i].name);
+ return -ENOMEM;
+ }
+ }
+
+ priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+
+ for (i = 0; i < 4; i++) {
+ phy_connect(priv->bus[INTERNAL], i, dev,
+ PHY_INTERFACE_MODE_NONE);
+ }
+
+ return 0;
+}
+
+static int ocelot_remove(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < NUM_PHY; i++) {
+ mdio_unregister(priv->bus[i]);
+ mdio_free(priv->bus[i]);
+ }
+
+ return 0;
+}
+
+static const struct eth_ops ocelot_ops = {
+ .start = ocelot_start,
+ .stop = ocelot_stop,
+ .send = ocelot_send,
+ .recv = ocelot_recv,
+ .write_hwaddr = ocelot_write_hwaddr,
+};
+
+static const struct udevice_id mscc_ocelot_ids[] = {
+ {.compatible = "mscc,vsc7514-switch"},
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(ocelot) = {
+ .name = "ocelot-switch",
+ .id = UCLASS_ETH,
+ .of_match = mscc_ocelot_ids,
+ .probe = ocelot_probe,
+ .remove = ocelot_remove,
+ .ops = &ocelot_ops,
+ .priv_auto_alloc_size = sizeof(struct ocelot_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
* Aquantia PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*/
#include <config.h>
#include <common.h>
#define AQUNTIA_SPEED_LSB_MASK 0x2000
#define AQUNTIA_SPEED_MSB_MASK 0x40
+#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
+#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
+#define AQUANTIA_FIRMWARE_ID 0x20
+#define AQUANTIA_RESERVED_STATUS 0xc885
+#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
+#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
+#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
+
+#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
+#define AQUANTIA_SI_IN_USE_MASK 0x0078
+#define AQUANTIA_SI_USXGMII 0x0018
+
/* registers in MDIO_MMD_VEND1 region */
#define GLOBAL_FIRMWARE_ID 0x20
#define GLOBAL_FAULT 0xc850
int aquantia_config(struct phy_device *phydev)
{
u32 val, id, rstatus, fault;
+ u32 reg_val1 = 0;
id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
AQUNTIA_SPEED_LSB_MASK |
AQUNTIA_SPEED_MSB_MASK);
+
+ val = phy_read(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_SYSTEM_INTERFACE_SR);
+ /* If SI is USXGMII then start USXGMII autoneg */
+ if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) {
+ phy_write(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_VENDOR_PROVISIONING_REG,
+ AQUANTIA_USX_AUTONEG_CONTROL_ENA);
+ printf("%s: system interface USXGMII\n",
+ phydev->dev->name);
+ } else {
+ printf("%s: system interface XFI\n",
+ phydev->dev->name);
+ }
+
} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
}
+
+ val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
+ reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
+
+ printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
+ phydev->drv->name,
+ (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
+ reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
+ (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
+
return 0;
}
} else {
changed = 1; /* Value was changed in OF */
/* Calculate the register value and fix corner cases */
- if (val[i] > ps_to_regval * 0xf) {
- max = (1 << ofcfg->grp[i].size) - 1;
+ max = (1 << ofcfg->grp[i].size) - 1;
+ if (val[i] > ps_to_regval * max) {
regval |= max << offset;
} else {
regval |= (val[i] / ps_to_regval) << offset;
}
static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
- u32 phy_id,
+ u32 phy_id, bool is_c45,
phy_interface_t interface)
{
struct phy_device *dev;
dev->addr = addr;
dev->phy_id = phy_id;
+ dev->is_c45 = is_c45;
dev->bus = bus;
dev->drv = get_phy_driver(dev, interface);
phy_interface_t interface)
{
u32 phy_id = 0xffffffff;
+ bool is_c45;
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
/* If the PHY ID is mostly f's, we didn't find anything */
- if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff)
- return phy_device_create(bus, addr, phy_id, interface);
+ if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
+ is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
+ return phy_device_create(bus, addr, phy_id, is_c45,
+ interface);
+ }
phy_mask &= ~(1 << addr);
}
return NULL;
debug("%s connected to %s\n", dev->name, phydev->drv->name);
}
+#ifdef CONFIG_PHY_FIXED
#ifdef CONFIG_DM_ETH
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct udevice *dev,
- phy_interface_t interface)
+static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
+ struct udevice *dev,
+ phy_interface_t interface)
#else
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct eth_device *dev,
- phy_interface_t interface)
+static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
+ struct eth_device *dev,
+ phy_interface_t interface)
#endif
{
struct phy_device *phydev = NULL;
-#ifdef CONFIG_PHY_FIXED
int sn;
const char *name;
while (sn > 0) {
name = fdt_get_name(gd->fdt_blob, sn, NULL);
if (name && strcmp(name, "fixed-link") == 0) {
- phydev = phy_device_create(bus,
- sn, PHY_FIXED_ID, interface);
+ phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
+ interface);
break;
}
sn = fdt_next_subnode(gd->fdt_blob, sn);
}
+
+ return phydev;
+}
+#endif
+
+#ifdef CONFIG_DM_ETH
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ struct udevice *dev,
+ phy_interface_t interface)
+#else
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ struct eth_device *dev,
+ phy_interface_t interface)
#endif
+{
+ struct phy_device *phydev = NULL;
+
+#ifdef CONFIG_PHY_FIXED
+ phydev = phy_connect_fixed(bus, dev, interface);
+#endif
+
if (!phydev)
phydev = phy_find_by_mask(bus, 1 << addr, interface);
#define MIIM_RTL8211F_TX_DELAY 0x100
#define MIIM_RTL8211F_LCR 0x10
+static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
+ int devaddr, int regnum)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT);
+ int val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
+
+ return val;
+}
+
+static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
+ phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
+
+ return 0;
+}
+
static int rtl8211b_probe(struct phy_device *phydev)
{
#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
.config = &rtl8211f_config,
.startup = &rtl8211f_startup,
.shutdown = &genphy_shutdown,
+ .readext = &rtl8211f_phy_extread,
+ .writeext = &rtl8211f_phy_extwrite,
};
int phy_realtek_init(void)
static int rtl_transmit(struct eth_device *dev, void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
-#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
-static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set)
+static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
{
return (0);
}
-#endif
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
-#ifdef CONFIG_MCAST_TFTP
dev->mcast = rtl_bcast_addr;
-#endif
eth_register (dev);
0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
}
-#ifdef CONFIG_MCAST_TFTP
+/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
+ * and this is the ethernet-crc method needed for TSEC -- and perhaps
+ * some other adapter -- hash tables
+ */
+#define CRCPOLY_LE 0xedb88320
+static u32 ether_crc(size_t len, unsigned char const *p)
+{
+ int i;
+ u32 crc;
+
+ crc = ~0;
+ while (len--) {
+ crc ^= *p++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
+ }
+ /* an reverse the bits, cuz of way they arrive -- last-first */
+ crc = (crc >> 16) | (crc << 16);
+ crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
+ crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
+ crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
+ crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
+ return crc;
+}
/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
* the entry.
*/
#ifndef CONFIG_DM_ETH
-static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
+static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
+ int join)
#else
-static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
+static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
value = BIT(31 - whichbit);
- if (set)
+ if (join)
setbits_be32(®s->hash.gaddr0 + whichreg, value);
else
clrbits_be32(®s->hash.gaddr0 + whichreg, value);
return 0;
}
-#endif /* Multicast TFTP ? */
/*
* Initialized required registers to appropriate values, zeroing
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
-#ifdef CONFIG_MCAST_TFTP
dev->mcast = tsec_mcast_addr;
-#endif
/* Tell U-Boot to get the addr from the env */
for (i = 0; i < 6; i++)
.recv = tsec_recv,
.free_pkt = tsec_free_pkt,
.stop = tsec_halt,
-#ifdef CONFIG_MCAST_TFTP
.mcast = tsec_mcast_addr,
-#endif
};
static const struct udevice_id tsec_ids[] = {
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(len, ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
-
- addr = (ulong)priv->rxbuffers;
- addr &= ~(ARCH_DMA_MINALIGN - 1);
- size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
- flush_dcache_range(addr, addr + size);
barrier();
/* Start transmit */
*packetp = (uchar *)(uintptr_t)addr;
+ invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+ barrier();
+
return frame_len;
}
return -ENOMEM;
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
+ u32 addr = (ulong)priv->rxbuffers;
+ flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+ barrier();
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
{
struct udevice *bus = pcie->bus;
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ return -ENODEV;
+
if (!pcie->enabled)
return -ENXIO;
struct ls_pcie *pcie = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
- u8 header_type;
u16 link_sta;
- bool ep_mode;
uint svr;
int ret;
fdt_size_t cfg_size;
(unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
pcie->big_endian);
- header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
- ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
- printf("PCIe%u: %s %s", pcie->idx, dev->name,
- ep_mode ? "Endpoint" : "Root Complex");
+ pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
- if (ep_mode)
- ls_pcie_setup_ep(pcie);
- else
- ls_pcie_setup_ctrl(pcie);
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ ls_pcie_setup_ep(pcie);
+ } else {
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ ls_pcie_setup_ctrl(pcie);
+ }
if (!ls_pcie_link_up(pcie)) {
/* Let the user know there's no PCIe link */
bool big_endian;
bool enabled;
int next_lut_index;
+ int mode;
};
extern struct list_head ls_pcie_list;
}
#endif
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
{
int off;
uint svr;
return;
}
- if (pcie->enabled)
+ if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ else
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+{
+ int off;
+
+ off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
+ pcie->dbi_res.start);
+ if (off < 0)
+ return;
+
+ if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
else
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+{
+ ft_pcie_ep_fix(blob, pcie);
+ ft_pcie_rc_fix(blob, pcie);
+}
+
/* Fixup Kernel DT for PCIe */
void ft_pci_setup(void *blob, bd_t *bd)
{
Supports individual pin selection and configuration for each
remappable peripheral available on Microchip PIC32
SoCs. This driver is controlled by a device tree node which
- contains both GPIO defintion and pin control functions.
+ contains both GPIO definition and pin control functions.
config PINCTRL_QCA953X
bool "QCA/Athores qca953x pin control driver"
help
Support pin multiplexing and pin configuration control on
Microsemi jr2 SoCs.
+
+config PINCTRL_MSCC_SERVALT
+ depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi servalt family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi servalt SoCs.
+
+config PINCTRL_MSCC_SERVAL
+ depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi serval family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi serval SoCs.
+
obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVALT) += pinctrl-servalt.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVAL) += pinctrl-serval.o
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0,
+ FUNC_IRQ1,
+ FUNC_MIIM1,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SIO,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MD,
+ FUNC_PTP1588,
+ FUNC_MAX
+};
+
+static char * const serval_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
+ [FUNC_IRQ1] = "irq1",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0] = "reco_clk0",
+ [FUNC_RECO_CLK1] = "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10] = "sfp10",
+ [FUNC_SIO] = "sio",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+ [FUNC_MD] = "md",
+ [FUNC_PTP1588] = "1588",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, TACHO, NONE, NONE);
+MSCC_P(5, PWM, NONE, NONE);
+MSCC_P(6, TWI, NONE, NONE);
+MSCC_P(7, TWI, NONE, NONE);
+MSCC_P(8, SI, NONE, NONE);
+MSCC_P(9, SI, MD, NONE);
+MSCC_P(10, SI, MD, NONE);
+MSCC_P(11, SFP0, MD, TWI_SCL_M);
+MSCC_P(12, SFP1, MD, TWI_SCL_M);
+MSCC_P(13, SFP2, UART2, TWI_SCL_M);
+MSCC_P(14, SFP3, UART2, TWI_SCL_M);
+MSCC_P(15, SFP4, PTP1588, TWI_SCL_M);
+MSCC_P(16, SFP5, PTP1588, TWI_SCL_M);
+MSCC_P(17, SFP6, PCI_WAKE, TWI_SCL_M);
+MSCC_P(18, SFP7, NONE, TWI_SCL_M);
+MSCC_P(19, SFP8, NONE, TWI_SCL_M);
+MSCC_P(20, SFP9, NONE, TWI_SCL_M);
+MSCC_P(21, SFP10, NONE, TWI_SCL_M);
+MSCC_P(22, NONE, NONE, NONE);
+MSCC_P(23, NONE, NONE, NONE);
+MSCC_P(24, NONE, NONE, NONE);
+MSCC_P(25, NONE, NONE, NONE);
+MSCC_P(26, UART, NONE, NONE);
+MSCC_P(27, UART, NONE, NONE);
+MSCC_P(28, IRQ0, NONE, NONE);
+MSCC_P(29, IRQ1, NONE, NONE);
+MSCC_P(30, PTP1588, NONE, NONE);
+MSCC_P(31, PTP1588, NONE, NONE);
+
+#define SERVAL_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data serval_pins[] = {
+ SERVAL_PIN(0),
+ SERVAL_PIN(1),
+ SERVAL_PIN(2),
+ SERVAL_PIN(3),
+ SERVAL_PIN(4),
+ SERVAL_PIN(5),
+ SERVAL_PIN(6),
+ SERVAL_PIN(7),
+ SERVAL_PIN(8),
+ SERVAL_PIN(9),
+ SERVAL_PIN(10),
+ SERVAL_PIN(11),
+ SERVAL_PIN(12),
+ SERVAL_PIN(13),
+ SERVAL_PIN(14),
+ SERVAL_PIN(15),
+ SERVAL_PIN(16),
+ SERVAL_PIN(17),
+ SERVAL_PIN(18),
+ SERVAL_PIN(19),
+ SERVAL_PIN(20),
+ SERVAL_PIN(21),
+ SERVAL_PIN(22),
+ SERVAL_PIN(23),
+ SERVAL_PIN(24),
+ SERVAL_PIN(25),
+ SERVAL_PIN(26),
+ SERVAL_PIN(27),
+ SERVAL_PIN(28),
+ SERVAL_PIN(29),
+ SERVAL_PIN(30),
+ SERVAL_PIN(31),
+};
+
+static const unsigned long serval_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x04,
+ [MSCC_GPIO_OUT] = 0x08,
+ [MSCC_GPIO_IN] = 0x0c,
+ [MSCC_GPIO_OE] = 0x10,
+ [MSCC_GPIO_INTR] = 0x14,
+ [MSCC_GPIO_INTR_ENA] = 0x18,
+ [MSCC_GPIO_INTR_IDENT] = 0x1c,
+ [MSCC_GPIO_ALT0] = 0x20,
+ [MSCC_GPIO_ALT1] = 0x24,
+};
+
+static int serval_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "serval-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(serval_pins);
+
+ return 0;
+}
+
+static struct driver serval_gpio_driver = {
+ .name = "serval-gpio",
+ .id = UCLASS_GPIO,
+ .probe = serval_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+static int serval_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, serval_pins,
+ ARRAY_SIZE(serval_pins),
+ serval_function_names,
+ serval_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &serval_gpio_driver, "serval-gpio", NULL,
+ dev_of_offset(dev), NULL);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id serval_pinctrl_of_match[] = {
+ { .compatible = "mscc,serval-pinctrl" },
+ {},
+};
+
+U_BOOT_DRIVER(serval_pinctrl) = {
+ .name = "serval-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(serval_pinctrl_of_match),
+ .probe = serval_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0_IN,
+ FUNC_IRQ0_OUT,
+ FUNC_IRQ1_IN,
+ FUNC_IRQ1_OUT,
+ FUNC_MIIM1,
+ FUNC_MIIM2,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RCVRD_CLK0,
+ FUNC_RCVRD_CLK1,
+ FUNC_RCVRD_CLK2,
+ FUNC_RCVRD_CLK3,
+ FUNC_REF_CLK0,
+ FUNC_REF_CLK1,
+ FUNC_REF_CLK2,
+ FUNC_REF_CLK3,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SFP11,
+ FUNC_SFP12,
+ FUNC_SFP13,
+ FUNC_SFP14,
+ FUNC_SFP15,
+ FUNC_SIO,
+ FUNC_SPI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI2,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MAX
+};
+
+static char * const servalt_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0_IN] = "irq0_in",
+ [FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1_IN] = "irq1_in",
+ [FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_MIIM2] = "miim2",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RCVRD_CLK0] = "rcvrd_clk0",
+ [FUNC_RCVRD_CLK1] = "rcvrd_clk1",
+ [FUNC_RCVRD_CLK2] = "rcvrd_clk2",
+ [FUNC_RCVRD_CLK3] = "rcvrd_clk3",
+ [FUNC_REF_CLK0] = "ref_clk0",
+ [FUNC_REF_CLK1] = "ref_clk1",
+ [FUNC_REF_CLK2] = "ref_clk2",
+ [FUNC_REF_CLK3] = "ref_clk3",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10] = "sfp10",
+ [FUNC_SFP11] = "sfp11",
+ [FUNC_SFP12] = "sfp12",
+ [FUNC_SFP13] = "sfp13",
+ [FUNC_SFP14] = "sfp14",
+ [FUNC_SFP15] = "sfp15",
+ [FUNC_SIO] = "sio",
+ [FUNC_SPI] = "spi",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI2] = "twi2",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
+MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
+MSCC_P(6, UART, NONE, NONE);
+MSCC_P(7, UART, NONE, NONE);
+MSCC_P(8, SPI, SFP0, TWI_SCL_M);
+MSCC_P(9, PCI_WAKE, SFP1, SPI);
+MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
+MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
+MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
+MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
+MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
+MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
+MSCC_P(16, TACHO, SFP6, SPI);
+MSCC_P(17, PWM, NONE, TWI_SCL_M);
+MSCC_P(18, PTP2, SFP7, SPI);
+MSCC_P(19, PTP3, SFP8, SPI);
+MSCC_P(20, UART2, SFP9, SPI);
+MSCC_P(21, UART2, NONE, NONE);
+MSCC_P(22, MIIM1, SFP10, TWI2);
+MSCC_P(23, MIIM1, SFP11, TWI2);
+MSCC_P(24, TWI, NONE, NONE);
+MSCC_P(25, TWI, SFP12, TWI_SCL_M);
+MSCC_P(26, TWI_SCL_M, SFP13, SPI);
+MSCC_P(27, TWI_SCL_M, SFP14, SPI);
+MSCC_P(28, TWI_SCL_M, SFP15, SPI);
+MSCC_P(29, TWI_SCL_M, NONE, NONE);
+MSCC_P(30, TWI_SCL_M, NONE, NONE);
+MSCC_P(31, TWI_SCL_M, NONE, NONE);
+MSCC_P(32, TWI_SCL_M, NONE, NONE);
+MSCC_P(33, RCVRD_CLK0, NONE, NONE);
+MSCC_P(34, RCVRD_CLK1, NONE, NONE);
+MSCC_P(35, RCVRD_CLK2, NONE, NONE);
+MSCC_P(36, RCVRD_CLK3, NONE, NONE);
+
+#define SERVALT_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data servalt_pins[] = {
+ SERVALT_PIN(0),
+ SERVALT_PIN(1),
+ SERVALT_PIN(2),
+ SERVALT_PIN(3),
+ SERVALT_PIN(4),
+ SERVALT_PIN(5),
+ SERVALT_PIN(6),
+ SERVALT_PIN(7),
+ SERVALT_PIN(8),
+ SERVALT_PIN(9),
+ SERVALT_PIN(10),
+ SERVALT_PIN(11),
+ SERVALT_PIN(12),
+ SERVALT_PIN(13),
+ SERVALT_PIN(14),
+ SERVALT_PIN(15),
+ SERVALT_PIN(16),
+ SERVALT_PIN(17),
+ SERVALT_PIN(18),
+ SERVALT_PIN(19),
+ SERVALT_PIN(20),
+ SERVALT_PIN(21),
+ SERVALT_PIN(22),
+ SERVALT_PIN(23),
+ SERVALT_PIN(24),
+ SERVALT_PIN(25),
+ SERVALT_PIN(26),
+ SERVALT_PIN(27),
+ SERVALT_PIN(28),
+ SERVALT_PIN(29),
+ SERVALT_PIN(30),
+ SERVALT_PIN(31),
+ SERVALT_PIN(32),
+ SERVALT_PIN(33),
+ SERVALT_PIN(34),
+ SERVALT_PIN(35),
+ SERVALT_PIN(36),
+};
+
+static const unsigned long servalt_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x08,
+ [MSCC_GPIO_OUT] = 0x10,
+ [MSCC_GPIO_IN] = 0x18,
+ [MSCC_GPIO_OE] = 0x20,
+ [MSCC_GPIO_INTR] = 0x28,
+ [MSCC_GPIO_INTR_ENA] = 0x30,
+ [MSCC_GPIO_INTR_IDENT] = 0x38,
+ [MSCC_GPIO_ALT0] = 0x40,
+ [MSCC_GPIO_ALT1] = 0x48,
+};
+
+static int servalt_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "servalt-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(servalt_pins);
+
+ return 0;
+}
+
+static struct driver servalt_gpio_driver = {
+ .name = "servalt-gpio",
+ .id = UCLASS_GPIO,
+ .probe = servalt_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+static int servalt_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, servalt_pins,
+ ARRAY_SIZE(servalt_pins),
+ servalt_function_names,
+ servalt_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
+ dev_of_offset(dev), NULL);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id servalt_pinctrl_of_match[] = {
+ { .compatible = "mscc,servalt-pinctrl" },
+ {},
+};
+
+U_BOOT_DRIVER(servalt_pinctrl) = {
+ .name = "servalt-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(servalt_pinctrl_of_match),
+ .probe = servalt_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
netdev->halt = usb_eth_halt;
netdev->priv = l_priv;
-#ifdef CONFIG_MCAST_TFTP
- #error not supported
-#endif
eth_register(netdev);
return 0;
}
help
This enables Mobile Industry Processor Interface(MIPI) display
support. The mipi controller and dphy on rk3288& rk3399 support
- 16,18, 24 bits per pixel with upto 2k resolution ratio.
+ 16,18, 24 bits per pixel with up to 2k resolution ratio.
endif
};
/*
- * We use Counter 1 for watchdog timer, because so does Marvell's Linux by
- * default.
+ * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
*/
-#define CNTR_CTRL 0x10
+#define CNTR_CTRL(id) ((id) * 0x10)
#define CNTR_CTRL_ENABLE 0x0001
#define CNTR_CTRL_ACTIVE 0x0002
#define CNTR_CTRL_MODE_MASK 0x000c
#define CNTR_CTRL_MODE_ONESHOT 0x0000
+#define CNTR_CTRL_MODE_HWSIG 0x000c
+#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
+#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
#define CNTR_CTRL_PRESCALE_MASK 0xff00
#define CNTR_CTRL_PRESCALE_MIN 2
#define CNTR_CTRL_PRESCALE_SHIFT 8
-#define CNTR_COUNT_LOW 0x14
-#define CNTR_COUNT_HIGH 0x18
+#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
+#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
-static void set_counter_value(struct a37xx_wdt *priv)
+static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val)
{
- writel(priv->timeout & 0xffffffff, priv->reg + CNTR_COUNT_LOW);
- writel(priv->timeout >> 32, priv->reg + CNTR_COUNT_HIGH);
+ writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));
+ writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));
}
-static void a37xx_wdt_enable(struct a37xx_wdt *priv)
+static void counter_enable(struct a37xx_wdt *priv, int id)
{
- u32 reg = readl(priv->reg + CNTR_CTRL);
+ setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
+}
- reg |= CNTR_CTRL_ENABLE;
- writel(reg, priv->reg + CNTR_CTRL);
+static void counter_disable(struct a37xx_wdt *priv, int id)
+{
+ clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
}
-static void a37xx_wdt_disable(struct a37xx_wdt *priv)
+static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
{
- u32 reg = readl(priv->reg + CNTR_CTRL);
+ u32 reg;
+
+ reg = readl(priv->reg + CNTR_CTRL(id));
+ if (reg & CNTR_CTRL_ACTIVE)
+ return -EBUSY;
+
+ reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
+ CNTR_CTRL_TRIG_SRC_MASK);
+
+ /* set mode */
+ reg |= mode;
+
+ /* set prescaler to the min value */
+ reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
+
+ /* set trigger source */
+ reg |= trig_src;
- reg &= ~CNTR_CTRL_ENABLE;
- writel(reg, priv->reg + CNTR_CTRL);
+ writel(reg, priv->reg + CNTR_CTRL(id));
+
+ return 0;
}
static int a37xx_wdt_reset(struct udevice *dev)
if (!priv->timeout)
return -EINVAL;
- a37xx_wdt_disable(priv);
- set_counter_value(priv);
- a37xx_wdt_enable(priv);
+ /* counter 1 is retriggered by forcing end count on counter 0 */
+ counter_disable(priv, 0);
+ counter_enable(priv, 0);
return 0;
}
{
struct a37xx_wdt *priv = dev_get_priv(dev);
- a37xx_wdt_disable(priv);
- priv->timeout = 0;
- set_counter_value(priv);
- a37xx_wdt_enable(priv);
+ /* first we set timeout to 0 */
+ counter_disable(priv, 1);
+ set_counter_value(priv, 1, 0);
+ counter_enable(priv, 1);
+
+ /* and then we start counter 1 by forcing end count on counter 0 */
+ counter_disable(priv, 0);
+ counter_enable(priv, 0);
return 0;
}
static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
{
struct a37xx_wdt *priv = dev_get_priv(dev);
- u32 reg;
-
- reg = readl(priv->reg + CNTR_CTRL);
-
- if (reg & CNTR_CTRL_ACTIVE)
- return -EBUSY;
+ int err;
- /* set mode */
- reg = (reg & ~CNTR_CTRL_MODE_MASK) | CNTR_CTRL_MODE_ONESHOT;
+ err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
+ if (err < 0)
+ return err;
- /* set prescaler to the min value */
- reg &= ~CNTR_CTRL_PRESCALE_MASK;
- reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
+ err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG,
+ CNTR_CTRL_TRIG_SRC_PREV_CNTR);
+ if (err < 0)
+ return err;
priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
- writel(reg, priv->reg + CNTR_CTRL);
+ set_counter_value(priv, 0, 0);
+ set_counter_value(priv, 1, priv->timeout);
+ counter_enable(priv, 1);
- set_counter_value(priv);
- a37xx_wdt_enable(priv);
+ /* we have to force end count on counter 0 to start counter 1 */
+ counter_enable(priv, 0);
return 0;
}
{
struct a37xx_wdt *priv = dev_get_priv(dev);
- a37xx_wdt_disable(priv);
+ counter_disable(priv, 1);
+ counter_disable(priv, 0);
+ writel(0, priv->sel_reg);
return 0;
}
priv->clk_rate = (ulong)get_ref_clk() * 1000000;
- a37xx_wdt_disable(priv);
-
/*
- * We use timer 1 as watchdog timer (because Marvell's Linux uses that
- * timer as default), therefore we only set bit TIMER1_IS_WCHDOG_TIMER.
+ * We use counter 1 as watchdog timer, therefore we only set bit
+ * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on
+ * counter 1.
*/
writel(1 << 1, priv->sel_reg);
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP 2
-#define CONFIG_PMECC_SECTOR_SIZE 512
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC 1
-#define CONFIG_ATMEL_NAND_HW_PMECC 1
-#define CONFIG_PMECC_CAP 2
-#define CONFIG_PMECC_SECTOR_SIZE 512
-
/* USB */
#ifdef CONFIG_CMD_USB
#ifndef CONFIG_USB_EHCI_HCD
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
* Console configuration
*/
-/*
- * Misc utility configuration
- */
-#define CONFIG_BOUNCE_BUFFER
-
#endif /* _CONFIG_AXS10X_H_ */
/* Enable Time Command */
-/* Misc utility code */
-#define CONFIG_BOUNCE_BUFFER
-
#endif /* __BCM_EP_BOARD_H */
#define CONFIG_SYS_MALLOC_LEN SZ_64K
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-/* Required by DW MMC driver */
-#define CONFIG_BOUNCE_BUFFER
-
/*
* Environment
*/
/* select serial console configuration */
-/* SD/MMC configuration */
-#define CONFIG_BOUNCE_BUFFER
-
/* PWM */
#define CONFIG_PWM
#define CONFIG_HIKEY_GPIO
-/* SD/MMC configuration */
-#define CONFIG_BOUNCE_BUFFER
-
/* Command line configuration */
/* BOOTP options */
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-/*
- * Misc utility configuration
- */
-#define CONFIG_BOUNCE_BUFFER
-
/* Cli configuration */
#define CONFIG_SYS_CBSIZE SZ_2K
CONFIG_SYS_MALLOC_LEN - \
CONFIG_ENV_SIZE
-/* Required by DW MMC driver */
-#define CONFIG_BOUNCE_BUFFER
-
/*
* Environment
*/
"env exists secureboot && esbc_halt;"
#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
"env exists secureboot && esbc_halt;"
+#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
#define LS1088ARDB_PB_BOARD 0x4A
/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
/* Link Definitions */
-
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#else
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
CONFIG_ENV_OFFSET)
#endif
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
+#ifndef CONFIG_TFABOOT
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
"sf read 0x80001000 0xd00000 0x100000;"\
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
+#endif /* CONFIG_TFABOOT */
#endif
/* Monitor Command Prompt */
unsigned long get_board_ddr_clk(void);
#endif
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0x500000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#else
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
+#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
FTIM2_GPCM_TWP(0x3E))
#define SYS_FPGA_CS_FTIM3 0x0
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
+#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#endif
+#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* QSPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#if !defined(CONFIG_TFABOOT) && \
+ !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_CS 0
#endif
"fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
"mcmemsize=0x70000000 \0"
#else /* if !(CONFIG_SECURE_BOOT) */
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD \
+ "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
+ "sf read 0x80100000 0xE00000 0x100000;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+#define SD_MC_INIT_CMD \
+ "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD \
+ "fsl_mc start mc 0x580A00000 0x580E00000\0"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x90100000\0" \
+ "kernel_addr=0x100000\0" \
+ "kernel_addr_sd=0x800\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x1000000\0" \
+ "kernel_start_sd=0x8000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
+ "sf read 0x80100000 0xE00000 0x100000;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0" \
+ "mcmemsize=0x70000000 \0"
+#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \
+ "sf read 0x80001000 0xd00000 0x100000;"\
+ " fsl_mc lazyapply dpl 0x80001000 &&" \
+ " sf read $kernel_load $kernel_start" \
+ " $kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
+ " fsl_mc lazyapply dpl 0x80001000 &&" \
+ " mmc read $kernel_load $kernel_start_sd" \
+ " $kernel_size_sd && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
+ " cp.b $kernel_start $kernel_load" \
+ " $kernel_size && bootm $kernel_load"
+#else
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
"mcmemsize=0x70000000 \0"
#endif
+#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_SECURE_BOOT */
#ifdef CONFIG_FSL_MC_ENET
#include "ls1088a_common.h"
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x500000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#else
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
+#endif /* CONFIG_TFABOOT */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_QIXIS_I2C_ACCESS
#endif
FTIM2_GPCM_TWP(0x3E))
#define SYS_FPGA_CS_FTIM3 0x0
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#endif
-
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define I2C_MUX_CH_VOL_MONITOR 0xA
#ifndef SPL_NO_QSPI
/* QSPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
#ifndef SPL_NO_ENV
/* Initial environment variables */
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD \
+ "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
+ "sf read 0x80100000 0xE00000 0x100000;" \
+ "env exists secureboot && " \
+ "sf read 0x80700000 0x700000 0x40000 && " \
+ "sf read 0x80740000 0x740000 0x40000 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+#define SD_MC_INIT_CMD \
+ "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "env exists secureboot && " \
+ "mmc read 0x80700000 0x3800 0x10 && " \
+ "mmc read 0x80740000 0x3A00 0x10 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+#else
#if defined(CONFIG_QSPI_BOOT)
#define MC_INIT_CMD \
"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
"fsl_mc start mc 0x80000000 0x80100000\0" \
"mcmemsize=0x70000000\0"
#endif
+#endif /* CONFIG_TFABOOT */
#undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_TFABOOT
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "BOARD=ls1088ardb\0" \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x64f00000\0" \
+ "kernel_addr=0x1000000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernel_start=0x580100000\0" \
+ "kernelheader_start=0x580800000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr=0x800000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "kernelheader_size=0x40000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "kernelhdr_size_sd=0x10\0" \
+ QSPI_MC_INIT_CMD \
+ "mcmemsize=0x70000000\0" \
+ BOOTENV \
+ "boot_scripts=ls1088ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "installer=load mmc 0:2 $load_addr " \
+ "/flex_installer_arm64.itb; " \
+ "env exists mcinitcmd && run mcinitcmd && " \
+ "mmc read 0x80001000 0x6800 0x800;" \
+ "fsl_mc lazyapply dpl 0x80001000;" \
+ "bootm $load_addr#ls1088ardb\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_addr $kernel_size ; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ "bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"BOARD=ls1088ardb\0" \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
+#endif /* CONFIG_TFABOOT */
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND \
+ "sf read 0x80001000 0xd00000 0x100000;" \
+ "env exists mcinitcmd && env exists secureboot " \
+ " && sf read 0x80780000 0x780000 0x100000 " \
+ "&& esbc_validate 0x80780000;env exists mcinitcmd " \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
+ "run distro_bootcmd;run qspi_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
+#define SD_BOOTCOMMAND \
+ "env exists mcinitcmd && mmcinfo; " \
+ "mmc read 0x80001000 0x6800 0x800; " \
+ "env exists mcinitcmd && env exists secureboot " \
+ " && mmc read 0x80780000 0x3C00 0x10 " \
+ "&& esbc_validate 0x80780000;env exists mcinitcmd " \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
+ "run distro_bootcmd;run sd_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
+#else
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
#endif
+#endif /* CONFIG_TFABOOT */
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#include <asm/arch/config.h>
/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
/* We need architecture specific misc initializations */
/* Link Definitions */
+#ifndef CONFIG_TFABOOT
#ifndef CONFIG_QSPI_BOOT
#else
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
+#ifndef CONFIG_TFABOOT
#ifdef CONFIG_SD_BOOT
#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
" fsl_mc apply dpl 0x80200000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
+#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0x500000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
+
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
"esbc_validate 0x580740000;" \
"fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
+#else
+#ifdef CONFIG_TFABOOT
+#define SD_MC_INIT_CMD \
+ "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD \
+ "fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "loadaddr_sd=0x90100000\0" \
+ "kernel_addr=0x100000\0" \
+ "kernel_addr_sd=0x800\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581000000\0" \
+ "kernel_start_sd=0x8000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "mcinitcmd=fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0" \
+ "mcmemsize=0x70000000 \0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"mcmemsize=0x40000000\0" \
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
+#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_SECURE_BOOT */
-
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB_10G
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
-#ifndef CONFIG_FSL_QSPI
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
+
+#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#ifndef CONFIG_TFABOOT
#define CONFIG_ENV_OFFSET (2048 * 1024)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
+#endif
#define CONFIG_SPL_PAD_TO 0x80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#ifndef CONFIG_TFABOOT
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#endif
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
func(SCSI, scsi, 0)
#include <config_distro_bootcmd.h>
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD \
+ "env exists secureboot && " \
+ "esbc_validate 0x20700000 && " \
+ "esbc_validate 0x20740000;" \
+ "fsl_mc start mc 0x20a00000 0x20e00000 \0"
+#define SD_MC_INIT_CMD \
+ "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "env exists secureboot && " \
+ "mmc read 0x80700000 0x3800 0x10 && " \
+ "mmc read 0x80740000 0x3A00 0x10 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD \
+ "env exists secureboot && " \
+ "esbc_validate 0x580700000 && " \
+ "esbc_validate 0x580740000; " \
+ "fsl_mc start mc 0x580a00000 0x580e00000 \0"
+#else
#ifdef CONFIG_QSPI_BOOT
#define MC_INIT_CMD \
"mcinitcmd=env exists secureboot && " \
"esbc_validate 0x580740000; " \
"fsl_mc start mc 0x580a00000 0x580e00000 \0"
#endif
+#endif
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_TFABOOT
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x64f00000\0" \
+ "kernel_addr=0x581000000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x800000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernelheader_addr=0x580800000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "kernelheader_size=0x40000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "console=ttyAMA0,38400n8\0" \
+ "mcmemsize=0x70000000\0" \
+ "sd_bootcmd=echo Trying load from SD ..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "bootm $load_addr#$board\0" \
+ QSPI_MC_INIT_CMD \
+ BOOTENV \
+ "boot_scripts=ls2088ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$board\0" \
+ "nor_bootcmd=echo Trying load from nor..;" \
+ "cp.b $kernel_addr $load_addr " \
+ "$kernel_size ; env exists secureboot && " \
+ "cp.b $kernelheader_addr $kernelheader_addr_r " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ "bootm $load_addr#$board\0"
+#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x800000\0" \
"cp.b $kernelheader_addr $kernelheader_addr_r " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
"bootm $load_addr#$board\0"
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& esbc_validate 0x20780000; " \
+ "env exists mcinitcmd && " \
+ "fsl_mc lazyapply dpl 0x20d00000; " \
+ "run distro_bootcmd;run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+/* Try to boot an on-SD kernel first, then do normal distro boot */
+#define SD_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
+ "&& esbc_validate $load_addr; " \
+ "env exists mcinitcmd && run mcinitcmd " \
+ "&& mmc read 0x88000000 0x6800 0x800 " \
+ "&& fsl_mc lazyapply dpl 0x88000000; " \
+ "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+/* Try to boot an on-NOR kernel first, then do normal distro boot */
+#define IFC_NOR_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& esbc_validate 0x580780000; env exists mcinitcmd "\
+ "&& fsl_mc lazyapply dpl 0x580d00000;" \
+ "run distro_bootcmd;run nor_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#else
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_QSPI_BOOT
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
"run distro_bootcmd;run nor_bootcmd; " \
"env exists secureboot && esbc_halt;"
#endif
+#endif
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET 0x100000
+
#endif
#define CONFIG_SYS_MAXARGS 32
/* MMC */
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_USDHC
/* Fuses */
#define CONFIG_MXC_UART
/* MMC */
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_USDHC
/* Fuses */
#define IRAM_BASE_ADDR OCRAM_0_BASE
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_USDHC
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_VIDEO_MXS
#endif
-/* MMC */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_BOUNCE_BUFFER
-#endif
-
/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* USB configuration */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-/* SD/MMC */
-#define CONFIG_BOUNCE_BUFFER
-
/*****************************************************************************
* Initial environment variables
*****************************************************************************/
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_SPL_STACK 0x10087fff
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE 0x80000000
# define CONFIG_SPL_TEXT_BASE 0xff704000
#endif
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
-/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
/* FAT sd card locations. */
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
-#define CONFIG_BOUNCE_BUFFER
-
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-/* MMC/SD IP block */
-#define CONFIG_BOUNCE_BUFFER
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP 4
-#define CONFIG_PMECC_SECTOR_SIZE 512
/* USB */
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP 4
-#define CONFIG_PMECC_SECTOR_SIZE 512
/* USB */
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
/* SPL */
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#endif
-#define CONFIG_PMECC_CAP 8
-#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
/* SPL */
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#endif
-#define CONFIG_PMECC_CAP 8
-#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
/* NAND Flash */
-#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_BOUNCE_BUFFER
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
* SDMMC configurations
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
#endif
/*
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
#endif
-/* Misc utility code */
-#define CONFIG_BOUNCE_BUFFER
-
#endif /* _TEGRA_COMMON_H_ */
#ifndef _CONFIG_TURRIS_MOX_H
#define _CONFIG_TURRIS_MOX_H
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
#define CONFIG_LAST_STAGE_INIT
/*
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
-#ifdef CONFIG_SOC_LUTON
+#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
+#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
#else
+#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC 1
-#define CONFIG_ATMEL_NAND_HW_PMECC 1
-#define CONFIG_PMECC_CAP 4
-#define CONFIG_PMECC_SECTOR_SIZE 512
-
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif /* __CONFIG_H__ */
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP 8
-#define CONFIG_PMECC_SECTOR_SIZE 512
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Allied Telesis Labs
+ */
+
+#ifndef _CONFIG_X530_H
+#define _CONFIG_X530_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
+#endif
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_PCI
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define BBT_CUSTOM_SCAN
+#define BBT_CUSTOM_SCAN_PAGE 0
+#define BBT_CUSTOM_SCAN_POSITION 2048
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
+#define MTDPARTS_MTDOOPS "errlog"
+
+/* Partition support */
+
+/* Additional FS support/configuration */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_SYS_MALLOC_LEN (4 << 20)
+
+#include <asm/arch/config.h>
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in low memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+#define CONFIG_SYS_LOAD_ADDR 0x1000000
+#define CONFIG_UBI_PART user
+#define CONFIG_UBIFS_VOLUME user
+
+/* SPL */
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+
+#endif /* _CONFIG_X530_H */
# define CONFIG_CPU_FREQ_HZ 800000000
#endif
+#define CONFIG_REMAKE_ELF
+
/* Cache options */
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012 Xilinx
- * (C) Copyright 2014 Digilent Inc.
- *
- * Configuration for Zynq Development Board - ZYBO
- * See zynq-common.h for Zynq common configs
- */
-
-#ifndef __CONFIG_ZYNQ_ZYBO_H
-#define __CONFIG_ZYNQ_ZYBO_H
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50
-
-#include <configs/zynq-common.h>
-
-#endif /* __CONFIG_ZYNQ_ZYBO_H */
#ifdef CONFIG_REGEX
#define ENV_DOT_ESCAPE "\\"
-#define ETHADDR_WILDCARD "\\d?"
#else
#define ENV_DOT_ESCAPE
-#define ETHADDR_WILDCARD
#endif
#ifdef CONFIG_CMD_DNS
#ifdef CONFIG_CMD_NET
#ifdef CONFIG_REGEX
-#define ETHADDR_WILDCARD "\\d?"
+#define ETHADDR_WILDCARD "\\d*"
#else
#define ETHADDR_WILDCARD
#endif
extern void env_reloc(void);
#endif
-#ifdef CONFIG_ENV_IS_IN_MMC
-#include <mmc.h>
-
-extern int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
-# ifdef CONFIG_SYS_MMC_ENV_PART
-extern uint mmc_get_env_part(struct mmc *mmc);
-# endif
-#endif
-
#ifndef DO_DEPS_ONLY
#include <env_attr.h>
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
+int is_lazy_dpl_addr_valid(void);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+# ifdef CONFIG_SYS_MMC_ENV_PART
+extern uint mmc_get_env_part(struct mmc *mmc);
+# endif
int mmc_get_env_dev(void);
/* Set block count limit because of 16 bit register limit on some hardware*/
int (*recv)(struct udevice *dev, int flags, uchar **packetp);
int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
void (*stop)(struct udevice *dev);
-#ifdef CONFIG_MCAST_TFTP
int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
-#endif
int (*write_hwaddr)(struct udevice *dev);
int (*read_rom_hwaddr)(struct udevice *dev);
};
int (*send)(struct eth_device *, void *packet, int length);
int (*recv)(struct eth_device *);
void (*halt)(struct eth_device *);
-#ifdef CONFIG_MCAST_TFTP
- int (*mcast)(struct eth_device *, const u8 *enetaddr, u8 set);
-#endif
+ int (*mcast)(struct eth_device *, const u8 *enetaddr, int join);
int (*write_hwaddr)(struct eth_device *);
struct eth_device *next;
int index;
int eth_rx(void); /* Check for received packets */
void eth_halt(void); /* stop SCC */
const char *eth_get_name(void); /* get name of current device */
-
-#ifdef CONFIG_MCAST_TFTP
int eth_mcast_join(struct in_addr mcast_addr, int join);
-u32 ether_crc(size_t len, unsigned char const *p);
-#endif
-
/**********************************************************************/
/*
extern int net_ntp_time_offset; /* offset time from UTC */
#endif
-#if defined(CONFIG_MCAST_TFTP)
-extern struct in_addr net_mcast_addr;
-#endif
-
/* Initialize the network adapter */
void net_init(void);
int net_loop(enum proto_t);
int pause;
int asym_pause;
u32 phy_id;
+ bool is_c45;
u32 flags;
};
The faster memset() is the arch-specific one (if available) enabled
by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get
better performance by writing a word at a time. But in very
- size-constrained envrionments even this may be too big. Enable this
+ size-constrained environments even this may be too big. Enable this
option to reduce code size slightly at the cost of some speed.
config TPL_TINY_MEMSET
The faster memset() is the arch-specific one (if available) enabled
by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get
better performance by writing a word at a time. But in very
- size-constrained envrionments even this may be too big. Enable this
+ size-constrained environments even this may be too big. Enable this
option to reduce code size slightly at the cost of some speed.
config RBTREE
ops->free_pkt += gd->reloc_off;
if (ops->stop)
ops->stop += gd->reloc_off;
-#ifdef CONFIG_MCAST_TFTP
if (ops->mcast)
ops->mcast += gd->reloc_off;
-#endif
if (ops->write_hwaddr)
ops->write_hwaddr += gd->reloc_off;
if (ops->read_rom_hwaddr)
return num_devices;
}
-#ifdef CONFIG_MCAST_TFTP
/* Multicast.
* mcast_addr: multicast ipaddr from which multicast Mac is made
* join: 1=join, 0=leave.
return eth_current->mcast(eth_current, mcast_mac, join);
}
-/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
- * and this is the ethernet-crc method needed for TSEC -- and perhaps
- * some other adapter -- hash tables
- */
-#define CRCPOLY_LE 0xedb88320
-u32 ether_crc(size_t len, unsigned char const *p)
-{
- int i;
- u32 crc;
- crc = ~0;
- while (len--) {
- crc ^= *p++;
- for (i = 0; i < 8; i++)
- crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
- }
- /* an reverse the bits, cuz of way they arrive -- last-first */
- crc = (crc >> 16) | (crc << 16);
- crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
- crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
- crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
- crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
- return crc;
-}
-
-#endif
-
-
int eth_init(void)
{
struct eth_device *old_current;
struct in_addr net_dns_server2;
#endif
-#ifdef CONFIG_MCAST_TFTP /* Multicast TFTP */
-struct in_addr net_mcast_addr;
-#endif
-
/** END OF BOOTP EXTENTIONS **/
/* Our ethernet address */
/* Invalidate the last protocol */
eth_set_last_protocol(BOOTP);
debug_cond(DEBUG_INT_STATE, "--- net_loop Fail!\n");
+ ret = -ENONET;
goto done;
case NETLOOP_CONTINUE:
dst_ip = net_read_ip(&ip->ip_dst);
if (net_ip.s_addr && dst_ip.s_addr != net_ip.s_addr &&
dst_ip.s_addr != 0xFFFFFFFF) {
-#ifdef CONFIG_MCAST_TFTP
- if (net_mcast_addr != dst_ip)
-#endif
return;
}
/* Read source IP address for later use */
static unsigned short tftp_block_size = TFTP_BLOCK_SIZE;
static unsigned short tftp_block_size_option = TFTP_MTU_BLOCKSIZE;
-#ifdef CONFIG_MCAST_TFTP
-#include <malloc.h>
-#define MTFTP_BITMAPSIZE 0x1000
-static unsigned *tftp_mcast_bitmap;
-static int tftp_mcast_prev_hole;
-static int tftp_mcast_bitmap_size = MTFTP_BITMAPSIZE;
-static int tftp_mcast_disabled;
-static int tftp_mcast_master_client;
-static int tftp_mcast_active;
-static int tftp_mcast_port;
-/* can get 'last' block before done..*/
-static ulong tftp_mcast_ending_block;
-
-static void parse_multicast_oack(char *pkt, int len);
-
-static void mcast_cleanup(void)
-{
- if (net_mcast_addr)
- eth_mcast_join(net_mcast_addr, 0);
- if (tftp_mcast_bitmap)
- free(tftp_mcast_bitmap);
- tftp_mcast_bitmap = NULL;
- net_mcast_addr.s_addr = 0;
- tftp_mcast_active = 0;
- tftp_mcast_port = 0;
- tftp_mcast_ending_block = -1;
-}
-
-#endif /* CONFIG_MCAST_TFTP */
-
static inline int store_block(int block, uchar *src, unsigned int len)
{
ulong offset = block * tftp_block_size + tftp_block_wrap_offset;
memcpy(ptr, src, len);
unmap_sysmem(ptr);
}
-#ifdef CONFIG_MCAST_TFTP
- if (tftp_mcast_active)
- ext2_set_bit(block, tftp_mcast_bitmap);
-#endif
if (net_boot_file_size < newsize)
net_boot_file_size = newsize;
static void restart(const char *msg)
{
printf("\n%s; starting again\n", msg);
-#ifdef CONFIG_MCAST_TFTP
- mcast_cleanup();
-#endif
net_start_again();
}
int len = 0;
ushort *s;
-#ifdef CONFIG_MCAST_TFTP
- /* Multicast TFTP.. non-MasterClients do not ACK data. */
- if (tftp_mcast_active && tftp_state == STATE_DATA &&
- tftp_mcast_master_client == 0)
- return;
-#endif
/*
* We will always be sending some sort of packet, so
* cobble together the packet headers now.
/* try for more effic. blk size */
pkt += sprintf((char *)pkt, "blksize%c%d%c",
0, tftp_block_size_option, 0);
-#ifdef CONFIG_MCAST_TFTP
- /* Check all preconditions before even trying the option */
- if (!tftp_mcast_disabled) {
- tftp_mcast_bitmap = malloc(tftp_mcast_bitmap_size);
- if (tftp_mcast_bitmap && eth_get_dev()->mcast) {
- free(tftp_mcast_bitmap);
- tftp_mcast_bitmap = NULL;
- pkt += sprintf((char *)pkt, "multicast%c%c",
- 0, 0);
- }
- }
-#endif /* CONFIG_MCAST_TFTP */
len = pkt - xp;
break;
case STATE_OACK:
-#ifdef CONFIG_MCAST_TFTP
- /* My turn! Start at where I need blocks I missed. */
- if (tftp_mcast_active)
- tftp_cur_block = ext2_find_next_zero_bit(
- tftp_mcast_bitmap,
- tftp_mcast_bitmap_size * 8, 0);
- /* fall through */
-#endif
case STATE_RECV_WRQ:
case STATE_DATA:
int i;
if (dest != tftp_our_port) {
-#ifdef CONFIG_MCAST_TFTP
- if (tftp_mcast_active &&
- (!tftp_mcast_port || dest != tftp_mcast_port))
-#endif
return;
}
if (tftp_state != STATE_SEND_RRQ && src != tftp_remote_port &&
}
#endif
}
-#ifdef CONFIG_MCAST_TFTP
- parse_multicast_oack((char *)pkt, len - 1);
- if ((tftp_mcast_active) && (!tftp_mcast_master_client))
- tftp_state = STATE_DATA; /* passive.. */
- else
-#endif
#ifdef CONFIG_CMD_TFTPPUT
if (tftp_put_active) {
/* Get ready to send the first block */
tftp_remote_port = src;
new_transfer();
-#ifdef CONFIG_MCAST_TFTP
- if (tftp_mcast_active) { /* start!=1 common if mcast */
- tftp_prev_block = tftp_cur_block - 1;
- } else
-#endif
if (tftp_cur_block != 1) { /* Assertion */
puts("\nTFTP error: ");
printf("First block is not block 1 (%ld)\n",
* Acknowledge the block just received, which will prompt
* the remote for the next one.
*/
-#ifdef CONFIG_MCAST_TFTP
- /* if I am the MasterClient, actively calculate what my next
- * needed block is; else I'm passive; not ACKING
- */
- if (tftp_mcast_active) {
- if (len < tftp_block_size) {
- tftp_mcast_ending_block = tftp_cur_block;
- } else if (tftp_mcast_master_client) {
- tftp_mcast_prev_hole = ext2_find_next_zero_bit(
- tftp_mcast_bitmap,
- tftp_mcast_bitmap_size * 8,
- tftp_mcast_prev_hole);
- tftp_cur_block = tftp_mcast_prev_hole;
- if (tftp_cur_block >
- ((tftp_mcast_bitmap_size * 8) - 1)) {
- debug("tftpfile too big\n");
- /* try to double it and retry */
- tftp_mcast_bitmap_size <<= 1;
- mcast_cleanup();
- net_start_again();
- return;
- }
- tftp_prev_block = tftp_cur_block;
- }
- }
-#endif
tftp_send();
-#ifdef CONFIG_MCAST_TFTP
- if (tftp_mcast_active) {
- if (tftp_mcast_master_client &&
- (tftp_cur_block >= tftp_mcast_ending_block)) {
- puts("\nMulticast tftp done\n");
- mcast_cleanup();
- net_set_state(NETLOOP_SUCCESS);
- }
- } else
-#endif
if (len < tftp_block_size)
tftp_complete();
break;
case TFTP_ERR_FILE_ALREADY_EXISTS:
default:
puts("Starting again\n\n");
-#ifdef CONFIG_MCAST_TFTP
- mcast_cleanup();
-#endif
net_start_again();
break;
}
memset(net_server_ethaddr, 0, 6);
/* Revert tftp_block_size to dflt */
tftp_block_size = TFTP_BLOCK_SIZE;
-#ifdef CONFIG_MCAST_TFTP
- mcast_cleanup();
-#endif
#ifdef CONFIG_TFTP_TSIZE
tftp_tsize = 0;
tftp_tsize_num_hash = 0;
}
#endif /* CONFIG_CMD_TFTPSRV */
-#ifdef CONFIG_MCAST_TFTP
-/*
- * Credits: atftp project.
- */
-
-/*
- * Pick up BcastAddr, Port, and whether I am [now] the master-client.
- * Frame:
- * +-------+-----------+---+-------~~-------+---+
- * | opc | multicast | 0 | addr, port, mc | 0 |
- * +-------+-----------+---+-------~~-------+---+
- * The multicast addr/port becomes what I listen to, and if 'mc' is '1' then
- * I am the new master-client so must send ACKs to DataBlocks. If I am not
- * master-client, I'm a passive client, gathering what DataBlocks I may and
- * making note of which ones I got in my bitmask.
- * In theory, I never go from master->passive..
- * .. this comes in with pkt already pointing just past opc
- */
-static void parse_multicast_oack(char *pkt, int len)
-{
- int i;
- struct in_addr addr;
- char *mc_adr;
- char *port;
- char *mc;
-
- mc_adr = NULL;
- port = NULL;
- mc = NULL;
- /* march along looking for 'multicast\0', which has to start at least
- * 14 bytes back from the end.
- */
- for (i = 0; i < len - 14; i++)
- if (strcmp(pkt + i, "multicast") == 0)
- break;
- if (i >= (len - 14)) /* non-Multicast OACK, ign. */
- return;
-
- i += 10; /* strlen multicast */
- mc_adr = pkt + i;
- for (; i < len; i++) {
- if (*(pkt + i) == ',') {
- *(pkt + i) = '\0';
- if (port) {
- mc = pkt + i + 1;
- break;
- } else {
- port = pkt + i + 1;
- }
- }
- }
- if (!port || !mc_adr || !mc)
- return;
- if (tftp_mcast_active && tftp_mcast_master_client) {
- printf("I got a OACK as master Client, WRONG!\n");
- return;
- }
- /* ..I now accept packets destined for this MCAST addr, port */
- if (!tftp_mcast_active) {
- if (tftp_mcast_bitmap) {
- printf("Internal failure! no mcast.\n");
- free(tftp_mcast_bitmap);
- tftp_mcast_bitmap = NULL;
- tftp_mcast_disabled = 1;
- return;
- }
- /* I malloc instead of pre-declare; so that if the file ends
- * up being too big for this bitmap I can retry
- */
- tftp_mcast_bitmap = malloc(tftp_mcast_bitmap_size);
- if (!tftp_mcast_bitmap) {
- printf("No bitmap, no multicast. Sorry.\n");
- tftp_mcast_disabled = 1;
- return;
- }
- memset(tftp_mcast_bitmap, 0, tftp_mcast_bitmap_size);
- tftp_mcast_prev_hole = 0;
- tftp_mcast_active = 1;
- }
- addr = string_to_ip(mc_adr);
- if (net_mcast_addr.s_addr != addr.s_addr) {
- if (net_mcast_addr.s_addr)
- eth_mcast_join(net_mcast_addr, 0);
- net_mcast_addr = addr;
- if (eth_mcast_join(net_mcast_addr, 1)) {
- printf("Fail to set mcast, revert to TFTP\n");
- tftp_mcast_disabled = 1;
- mcast_cleanup();
- net_start_again();
- }
- }
- tftp_mcast_master_client = simple_strtoul((char *)mc, NULL, 10);
- tftp_mcast_port = (unsigned short)simple_strtoul(port, NULL, 10);
- printf("Multicast: %s:%d [%d]\n", mc_adr, tftp_mcast_port,
- tftp_mcast_master_client);
- return;
-}
-
-#endif /* Multicast TFTP */
-n "$(shell cd $(srctree); readlink -f $(CONFIG_PMUFW_INIT_FILE))"
endif
-spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
+$(obj)/$(SPL_BIN)-align.bin: $(obj)/$(SPL_BIN).bin
+ @dd if=$< of=$@ conv=block,sync bs=4 2>/dev/null;
+
+spl/boot.bin: $(obj)/$(SPL_BIN)-align.bin FORCE
$(call if_changed,mkimage)
endif
CONFIG_ATMEL_LCD_RGB565
CONFIG_ATMEL_LEGACY
CONFIG_ATMEL_MCI_8BIT
-CONFIG_ATMEL_NAND_HWECC
-CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_ATMEL_SPI0
CONFIG_AT_TRANS
CONFIG_AUTO_ZRELADDR
CONFIG_BOOT_PARAMS_ADDR
CONFIG_BOOT_RETRY_MIN
CONFIG_BOOT_RETRY_TIME
-CONFIG_BOUNCE_BUFFER
CONFIG_BPTR_VIRT_ADDR
CONFIG_BS_ADDR_DEVICE
CONFIG_BS_ADDR_RAM
CONFIG_MAX_MEM_MAPPED
CONFIG_MAX_PKT
CONFIG_MAX_RAM_BANK_SIZE
-CONFIG_MCAST_TFTP
CONFIG_MCF5249
CONFIG_MCF5253
CONFIG_MCFFEC
CONFIG_PM
CONFIG_PMC_BR_PRELIM
CONFIG_PMC_OR_PRELIM
-CONFIG_PMECC_CAP
-CONFIG_PMECC_SECTOR_SIZE
CONFIG_PME_PLAT_CLK_DIV
CONFIG_PMU
CONFIG_PMW_BASE
CONFIG_SPL_FS_LOAD_KERNEL_NAME
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
CONFIG_SPL_GD_ADDR
-CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
CONFIG_SPL_INIT_MINIMAL
CONFIG_SPL_JR0_LIODN_NS
CONFIG_SPL_JR0_LIODN_S
env_set("ethact", "eth@10004000");
env_set("netretry", "no");
sandbox_eth_skip_timeout();
- ut_asserteq(-ETIMEDOUT, net_loop(PING));
+ ut_asserteq(-ENONET, net_loop(PING));
ut_asserteq_str("eth@10004000", env_get("ethact"));
return 0;
static int bif_add_part(struct bif_entry *bf, const char *data, size_t len)
{
size_t parthdr_offset = 0;
+ size_t len_padded = ROUND(len, 4);
+
struct partition_header parthdr = {
- .len_enc = cpu_to_le32(len / 4),
- .len_unenc = cpu_to_le32(len / 4),
- .len = cpu_to_le32(len / 4),
+ .len_enc = cpu_to_le32(len_padded / 4),
+ .len_unenc = cpu_to_le32(len_padded / 4),
+ .len = cpu_to_le32(len_padded / 4),
.entry_point = cpu_to_le64(bf->entry),
.load_address = cpu_to_le64(bf->load),
};
int r;
uint32_t csum;
+ if (len < len_padded) {
+ char *newdata = malloc(len_padded);
+ memcpy(newdata, data, len);
+ memset(newdata + len, 0, len_padded - len);
+ data = newdata;
+ }
+
if (bf->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE))
return bif_add_pmufw(bf, data, len);
if (!bif_output.header->image_offset)
bif_output.header->image_offset =
cpu_to_le32(bf->offset);
- bif_output.header->image_size = cpu_to_le32(len);
- bif_output.header->image_stored_size = cpu_to_le32(len);
+ bif_output.header->image_size = cpu_to_le32(len_padded);
+ bif_output.header->image_stored_size = cpu_to_le32(len_padded);
bif_output.header->image_attributes &= ~HEADER_CPU_SELECT_MASK;
switch (bf->dest_cpu) {
git.openpandora.org / pandora-u-boot.git / commitdiff