Merge branch 'drm-intel-fixes' into drm-intel-next

diff --combined drivers/gpu/drm/i915/intel_dp.c
index 52b79d9,dcc7ae6..6a9ec00
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -178,14 -178,12 +178,14 @@@ intel_dp_link_clock(uint8_t link_bw
  static int
  intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
  {
 -      struct drm_i915_private *dev_priv = dev->dev_private;
 +      struct drm_crtc *crtc = intel_dp->base.base.crtc;
 +      struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 +      int bpp = 24;
  
 -      if (is_edp(intel_dp))
 -              return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 -      else
 -              return pixel_clock * 3;
 +      if (intel_crtc)
 +              bpp = intel_crtc->bpp;
 +
 +      return (pixel_clock * bpp + 7) / 8;
  }
  
  static int
@@@ -683,7 -681,7 +683,7 @@@ intel_dp_set_m_n(struct drm_crtc *crtc
        struct drm_encoder *encoder;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 -      int lane_count = 4, bpp = 24;
 +      int lane_count = 4;
        struct intel_dp_m_n m_n;
        int pipe = intel_crtc->pipe;
  
@@@ -702,6 -700,7 +702,6 @@@
                        break;
                } else if (is_edp(intel_dp)) {
                        lane_count = dev_priv->edp.lanes;
 -                      bpp = dev_priv->edp.bpp;
                        break;
                }
        }
@@@ -711,7 -710,7 +711,7 @@@
         * the number of bytes_per_pixel post-LUT, which we always
         * set up for 8-bits of R/G/B, or 3 bytes total.
         */
 -      intel_dp_compute_m_n(bpp, lane_count,
 +      intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
                             mode->clock, adjusted_mode->clock, &m_n);
  
        if (HAS_PCH_SPLIT(dev)) {
@@@ -1335,10 -1334,16 +1335,16 @@@ intel_dp_start_link_train(struct intel_
        u32 reg;
        uint32_t DP = intel_dp->DP;
  
-       /* Enable output, wait for it to become active */
-       I915_WRITE(intel_dp->output_reg, intel_dp->DP);
-       POSTING_READ(intel_dp->output_reg);
-       intel_wait_for_vblank(dev, intel_crtc->pipe);
+       /*
+        * On CPT we have to enable the port in training pattern 1, which
+        * will happen below in intel_dp_set_link_train.  Otherwise, enable
+        * the port and wait for it to become active.
+        */
+       if (!HAS_PCH_CPT(dev)) {
+               I915_WRITE(intel_dp->output_reg, intel_dp->DP);
+               POSTING_READ(intel_dp->output_reg);
+               intel_wait_for_vblank(dev, intel_crtc->pipe);
+       }
  
        /* Write the link configuration data */
        intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
@@@ -1371,7 -1376,8 +1377,8 @@@
                        reg = DP | DP_LINK_TRAIN_PAT_1;
  
                if (!intel_dp_set_link_train(intel_dp, reg,
-                                            DP_TRAINING_PATTERN_1))
+                                            DP_TRAINING_PATTERN_1 |
+                                            DP_LINK_SCRAMBLING_DISABLE))
                        break;
                /* Set training pattern 1 */
  
@@@ -1446,7 -1452,8 +1453,8 @@@ intel_dp_complete_link_train(struct int
  
                /* channel eq pattern */
                if (!intel_dp_set_link_train(intel_dp, reg,
-                                            DP_TRAINING_PATTERN_2))
+                                            DP_TRAINING_PATTERN_2 |
+                                            DP_LINK_SCRAMBLING_DISABLE))
                        break;
  
                udelay(400);