config %config: scripts_basic outputmakefile FORCE
$(Q)mkdir -p include/linux
$(Q)$(MAKE) $(build)=scripts/kconfig $@
- $(Q)$(MAKE) .kernelrelease
+ $(Q)$(MAKE) -C $(srctree) KBUILD_SRC= .kernelrelease
else
# ===========================================================================
@ln -sfn $(SRC_ARCH)/$(SARCH)/lib $(SRC_ARCH)/lib
@ln -sfn $(SRC_ARCH)/$(SARCH) $(SRC_ARCH)/arch
@ln -sfn $(SRC_ARCH)/$(SARCH)/vmlinux.lds.S $(SRC_ARCH)/kernel/vmlinux.lds.S
- @ln -sfn $(SRC_ARCH)/$(SARCH)/asm-offsets.c $(SRC_ARCH)/kernel/asm-offsets.c
+ @ln -sfn $(SRC_ARCH)/$(SARCH)/kernel/asm-offsets.c $(SRC_ARCH)/kernel/asm-offsets.c
@touch $@
# Create link to sub arch includes
* completely.
* But only ack when the APIC is enabled -AK
*/
- if (!cpu_has_apic)
+ if (cpu_has_apic)
ack_APIC_irq();
}
select SYS_HAS_CPU_R5000
select SYS_HAS_CPU_R10000 if BROKEN
select SYS_HAS_CPU_RM7000
+ select SYS_HAS_CPU_NEVADA
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
endif
CHECKFLAGS-y += -D__linux__ -D__mips__ \
+ -D_MIPS_SZINT=32 \
-D_ABIO32=1 \
-D_ABIN32=2 \
-D_ABI64=3
CHECKFLAGS-$(CONFIG_32BIT) += -D_MIPS_SIM=_ABIO32 \
-D_MIPS_SZLONG=32 \
+ -D_MIPS_SZPTR=32 \
-D__PTRDIFF_TYPE__=int
CHECKFLAGS-$(CONFIG_64BIT) += -m64 -D_MIPS_SIM=_ABI64 \
-D_MIPS_SZLONG=64 \
+ -D_MIPS_SZPTR=64 \
-D__PTRDIFF_TYPE__="long int"
CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__
CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__
#
cflags-$(CONFIG_CPU_R3000) += \
$(call set_gccflags,r3000,mips1,r3000,mips1,mips1)
+CHECKFLAGS-$(CONFIG_CPU_R3000) += -D_MIPS_ISA=_MIPS_ISA_MIPS1
cflags-$(CONFIG_CPU_TX39XX) += \
$(call set_gccflags,r3900,mips1,r3000,mips1,mips1)
+CHECKFLAGS-$(CONFIG_CPU_TX39XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS1
cflags-$(CONFIG_CPU_R6000) += \
$(call set_gccflags,r6000,mips2,r6000,mips2,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R6000) += -D_MIPS_ISA=_MIPS_ISA_MIPS2
cflags-$(CONFIG_CPU_R4300) += \
$(call set_gccflags,r4300,mips3,r4300,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R4300) += -D_MIPS_ISA=_MIPS_ISA_MIPS3
cflags-$(CONFIG_CPU_VR41XX) += \
$(call set_gccflags,r4100,mips3,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_VR41XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS3
cflags-$(CONFIG_CPU_R4X00) += \
$(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R4X00) += -D_MIPS_ISA=_MIPS_ISA_MIPS3
cflags-$(CONFIG_CPU_TX49XX) += \
$(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_TX49XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS3
cflags-$(CONFIG_CPU_MIPS32_R1) += \
$(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_MIPS32_R1) += -D_MIPS_ISA=_MIPS_ISA_MIPS32
cflags-$(CONFIG_CPU_MIPS32_R2) += \
$(call set_gccflags,mips32r2,mips32r2,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_MIPS32_R2) += -D_MIPS_ISA=_MIPS_ISA_MIPS32
cflags-$(CONFIG_CPU_MIPS64_R1) += \
$(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_MIPS64_R1) += -D_MIPS_ISA=_MIPS_ISA_MIPS64
cflags-$(CONFIG_CPU_MIPS64_R2) += \
$(call set_gccflags,mips64r2,mips64r2,r4600,mips3,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_MIPS64_R2) += -D_MIPS_ISA=_MIPS_ISA_MIPS64
cflags-$(CONFIG_CPU_R5000) += \
$(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R5000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
cflags-$(CONFIG_CPU_R5432) += \
$(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R5432) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
cflags-$(CONFIG_CPU_NEVADA) += \
$(call set_gccflags,rm5200,mips4,r5000,mips4,mips2) \
-Wa,--trap
-# $(call cc-option,-mmad)
+CHECKFLAGS-$(CONFIG_CPU_NEVADA) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
cflags-$(CONFIG_CPU_RM7000) += \
$(call set_gccflags,rm7000,mips4,r5000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_RM7000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
cflags-$(CONFIG_CPU_RM9000) += \
$(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_RM9000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
cflags-$(CONFIG_CPU_SB1) += \
$(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_SB1) += -D_MIPS_ISA=_MIPS_ISA_MIPS64
cflags-$(CONFIG_CPU_R8000) += \
$(call set_gccflags,r8000,mips4,r8000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R8000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
cflags-$(CONFIG_CPU_R10000) += \
$(call set_gccflags,r10000,mips4,r8000,mips4,mips2) \
-Wa,--trap
+CHECKFLAGS-$(CONFIG_CPU_R10000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4
ifdef CONFIG_CPU_SB1
ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
# Cobalt Server
#
core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
-cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
+cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/mach-cobalt
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
#
}
set_c0_status(ST0_BEV | ST0_ERL);
- set_c0_config(CONF_CM_UNCACHED);
+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_c0_wired(0);
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
+#include <linux/pm.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#endif
_machine_restart = au1000_restart;
_machine_halt = au1000_halt;
- _machine_power_off = au1000_power_off;
+ pm_power_off = au1000_power_off;
board_time_init = au1xxx_time_init;
board_timer_setup = au1xxx_timer_setup;
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/gt64120.h>
#include <asm/ptrace.h>
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
extern void cobalt_handle_int(void);
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
void cobalt_machine_halt(void)
{
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
*
*/
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
+#include <linux/pm.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <asm/gt64120.h>
#include <asm/serial.h>
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
- _machine_power_off = cobalt_machine_power_off;
+ pm_power_off = cobalt_machine_power_off;
board_timer_setup = cobalt_timer_setup;
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_R5000=y
+CONFIG_SYS_HAS_CPU_NEVADA=y
CONFIG_SYS_HAS_CPU_RM7000=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15-rc2
-# Thu Nov 24 01:07:00 2005
+# Linux kernel version: 2.6.16-rc2
+# Fri Feb 3 17:14:27 2006
#
CONFIG_MIPS=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_SYSCTL is not set
# CONFIG_AUDIT is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
# CONFIG_BUG is not set
+CONFIG_ELF_CORE=y
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SHMEM is not set
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_SLAB=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=1
+# CONFIG_SLOB is not set
#
# Loadable module support
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=y
-CONFIG_IEEE80211_CRYPT_TKIP=y
+# CONFIG_IEEE80211 is not set
#
# Device Drivers
#
# SCSI device support
#
-CONFIG_RAID_ATTRS=y
+# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
#
#
# PHY device support
#
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
+# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
+# CONFIG_MII is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_DEPCA is not set
# CONFIG_HP100 is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
#
# CONFIG_I2C is not set
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
#
# Dallas's 1-wire bus
#
# SN Devices
#
+#
+# EDAC - error detection and reporting (RAS)
+#
+
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
#
# Cryptographic options
#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO is not set
#
# Hardware crypto devices
# Library routines
#
# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
+# CONFIG_CRC16 is not set
CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
+# CONFIG_LIBCRC32C is not set
#include <linux/ide.h>
#include <linux/ioport.h>
#include <linux/irq.h>
+#include <linux/pm.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
_machine_restart = ddb_machine_restart;
_machine_halt = ddb_machine_halt;
- _machine_power_off = ddb_machine_power_off;
+ pm_power_off = ddb_machine_power_off;
ddb_out32(DDB_BAR0, 0);
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/pci.h>
+#include <linux/pm.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
_machine_restart = ddb_machine_restart;
_machine_halt = ddb_machine_halt;
- _machine_power_off = ddb_machine_power_off;
+ pm_power_off = ddb_machine_power_off;
/* request io port/mem resources */
if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
#include <linux/major.h>
#include <linux/kdev_t.h>
#include <linux/root_dev.h>
+#include <linux/pm.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
_machine_restart = ddb_machine_restart;
_machine_halt = ddb_machine_halt;
- _machine_power_off = ddb_machine_power_off;
+ pm_power_off = ddb_machine_power_off;
/* setup resource limits */
ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
+#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
_machine_restart = dec_machine_restart;
_machine_halt = dec_machine_halt;
- _machine_power_off = dec_machine_power_off;
+ pm_power_off = dec_machine_power_off;
ioport_resource.start = ~0UL;
ioport_resource.end = 0UL;
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
+#include <linux/pm.h>
+
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/io.h>
{
_machine_restart = galileo_machine_restart;
_machine_halt = galileo_machine_halt;
- _machine_power_off = galileo_machine_power_off;
+ pm_power_off = galileo_machine_power_off;
board_time_init = gt64120_time_init;
set_io_port_base(KSEG1);
* BRIEF MODULE DESCRIPTION
* Momentum Computer Ocelot (CP7000) - board dependent boot routines
*
- * Copyright (C) 1996, 1997, 2001 Ralf Baechle
+ * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer
#include <linux/pci.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
+#include <linux/pm.h>
+
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
- _machine_power_off = momenco_ocelot_power_off;
+ pm_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (ulong)ocelot_initrd_start;
#include <linux/major.h>
#include <linux/kdev_t.h>
#include <linux/root_dev.h>
+#include <linux/pm.h>
#include <asm/cpu.h>
#include <asm/time.h>
_machine_restart = it8172_restart;
_machine_halt = it8172_halt;
- _machine_power_off = it8172_power_off;
+ pm_power_off = it8172_power_off;
/*
* IO/MEM resources.
#include <linux/console.h>
#include <linux/fb.h>
#include <linux/ide.h>
+#include <linux/pm.h>
+
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/jazz.h>
_machine_restart = jazz_machine_restart;
_machine_halt = jazz_machine_halt;
- _machine_power_off = jazz_machine_power_off;
+ pm_power_off = jazz_machine_power_off;
#warning "Somebody should check if screen_info is ok for Jazz."
#include <linux/ioport.h>
#include <linux/param.h> /* for HZ */
#include <linux/delay.h>
+#include <linux/pm.h>
#ifdef CONFIG_SERIAL_TXX9
#include <linux/tty.h>
#include <linux/serial.h>
_machine_restart = jmr3927_machine_restart;
_machine_halt = jmr3927_machine_halt;
- _machine_power_off = jmr3927_machine_power_off;
+ pm_power_off = jmr3927_machine_power_off;
/*
* IO/MEM resources.
* Processor capabilities determination functions.
*
* Copyright (C) xxxx the Anonymous
+ * Copyright (C) 1994 - 2006 Ralf Baechle
* Copyright (C) 2003, 2004 Maciej W. Rozycki
- * Copyright (C) 1994 - 2003 Ralf Baechle
* Copyright (C) 2001, 2004 MIPS Inc.
*
* This program is free software; you can redistribute it and/or
switch (c->processor_id & 0xff00) {
case PRID_IMP_SB1:
c->cputype = CPU_SB1;
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
/* FPU in pass1 is known to have issues. */
- c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
-#endif
+ if ((c->processor_id & 0xff) < 0x20)
+ c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
break;
case PRID_IMP_SB1A:
c->cputype = CPU_SB1A;
NESTED(nmi_handler, PT_SIZE, sp)
.set push
.set noat
- .set mips3
SAVE_ALL
move a0, sp
jal nmi_exception_handler
RESTORE_ALL
+ .set mips3
eret
.set pop
END(nmi_handler)
ret = -EIO;
if (copied != sizeof(tmp))
break;
- ret = put_user(tmp, (unsigned int *) (unsigned long) data);
+ ret = put_user(tmp, (unsigned int __user *) (unsigned long) data);
break;
}
case FPC_EIR: { /* implementation / version register */
unsigned int flags;
- if (!cpu_has_fpu)
+ if (!cpu_has_fpu) {
+ tmp = 0;
break;
+ }
preempt_disable();
if (cpu_has_mipsmt) {
preempt_enable();
break;
}
- case DSP_BASE ... DSP_BASE + 5:
+ case DSP_BASE ... DSP_BASE + 5: {
+ dspreg_t *dregs;
+
if (!cpu_has_dsp) {
tmp = 0;
ret = -EIO;
goto out_tsk;
}
- dspreg_t *dregs = __get_dsp_regs(child);
+ dregs = __get_dsp_regs(child);
tmp = (unsigned long) (dregs[addr - DSP_BASE]);
break;
+ }
case DSP_CONTROL:
if (!cpu_has_dsp) {
tmp = 0;
ret = -EIO;
goto out_tsk;
}
- ret = put_user(tmp, (unsigned *) (unsigned long) data);
+ ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
break;
}
else
child->thread.fpu.soft.fcr31 = data;
break;
- case DSP_BASE ... DSP_BASE + 5:
+ case DSP_BASE ... DSP_BASE + 5: {
+ dspreg_t *dregs;
+
if (!cpu_has_dsp) {
ret = -EIO;
break;
}
- dspreg_t *dregs = __get_dsp_regs(child);
+ dregs = __get_dsp_regs(child);
dregs[addr - DSP_BASE] = data;
break;
+ }
case DSP_CONTROL:
if (!cpu_has_dsp) {
ret = -EIO;
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2001 by Ralf Baechle
+ * Copyright (C) 2001, 06 by Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/pm.h>
#include <linux/types.h>
#include <linux/reboot.h>
-#include <asm/reboot.h>
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
+#include <asm/reboot.h>
/*
* Urgs ... Too many MIPS machines to handle this in a generic way.
*/
void (*_machine_restart)(char *command);
void (*_machine_halt)(void);
-void (*_machine_power_off)(void);
+void (*pm_power_off)(void);
void machine_restart(char *command)
{
- _machine_restart(command);
+ if (_machine_restart)
+ _machine_restart(command);
}
void machine_halt(void)
{
- _machine_halt();
+ if (_machine_halt)
+ _machine_halt();
}
void machine_power_off(void)
{
if (pm_power_off)
pm_power_off();
-
- _machine_power_off();
}
-
/*
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/poll.h>
#include <linux/sched.h>
#include <linux/wait.h>
+
#include <asm/mipsmtregs.h>
#include <asm/bitops.h>
#include <asm/cpu.h>
#include <linux/config.h>
static inline int
-setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
+setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
{
int err = 0;
}
static inline int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
{
unsigned int used_math;
unsigned long treg;
/*
* Determine which stack to use..
*/
-static inline void *
+static inline void __user *
get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
{
unsigned long sp;
if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
sp = current->sas_ss_sp + current->sas_ss_size;
- return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK));
+ return (void __user *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK));
}
static inline int install_sigtramp(unsigned int __user *tramp,
__attribute_used__ noinline static void
_sys_sigreturn(nabi_no_regargs struct pt_regs regs)
{
- struct sigframe *frame;
+ struct sigframe __user *frame;
sigset_t blocked;
- frame = (struct sigframe *) regs.regs[29];
+ frame = (struct sigframe __user *) regs.regs[29];
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&blocked, &frame->sf_mask, sizeof(blocked)))
__attribute_used__ noinline static void
_sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
{
- struct rt_sigframe *frame;
+ struct rt_sigframe __user *frame;
sigset_t set;
stack_t st;
- frame = (struct rt_sigframe *) regs.regs[29];
+ frame = (struct rt_sigframe __user *) regs.regs[29];
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set)))
goto badframe;
/* It is more difficult to avoid calling this function than to
call it and ignore errors. */
- do_sigaltstack(&st, NULL, regs.regs[29]);
+ do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]);
/*
* Don't let your children do this ...
int setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set)
{
- struct sigframe *frame;
+ struct sigframe __user *frame;
int err = 0;
frame = get_sigframe(ka, regs, sizeof(*frame));
int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set, siginfo_t *info)
{
- struct rt_sigframe *frame;
+ struct rt_sigframe __user *frame;
int err = 0;
frame = get_sigframe(ka, regs, sizeof(*frame));
/* Create the ucontext. */
err |= __put_user(0, &frame->rs_uc.uc_flags);
- err |= __put_user(0, &frame->rs_uc.uc_link);
+ err |= __put_user(NULL, &frame->rs_uc.uc_link);
err |= __put_user((void *)current->sas_ss_sp,
&frame->rs_uc.uc_stack.ss_sp);
err |= __put_user(sas_ss_flags(regs->regs[29]),
extern void __put_sigset_unknown_nsig(void);
extern void __get_sigset_unknown_nsig(void);
-static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t *ubuf)
+static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t __user *ubuf)
{
int err = 0;
if (!access_ok(VERIFY_READ, act, sizeof(*act)))
return -EFAULT;
err |= __get_user(handler, &act->sa_handler);
- new_ka.sa.sa_handler = (void*)(s64)handler;
+ new_ka.sa.sa_handler = (void __user *)(s64)handler;
err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags);
err |= __get_user(mask, &act->sa_mask.sig[0]);
if (err)
asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs)
{
- const stack32_t *uss = (const stack32_t *) regs.regs[4];
- stack32_t *uoss = (stack32_t *) regs.regs[5];
+ const stack32_t __user *uss = (const stack32_t __user *) regs.regs[4];
+ stack32_t __user *uoss = (stack32_t __user *) regs.regs[5];
unsigned long usp = regs.regs[29];
stack_t kss, koss;
int ret, err = 0;
}
set_fs (KERNEL_DS);
- ret = do_sigaltstack(uss ? &kss : NULL , uoss ? &koss : NULL, usp);
+ ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL,
+ uoss ? (stack_t __user *)&koss : NULL, usp);
set_fs (old_fs);
if (!ret && uoss) {
return ret;
}
-static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc)
+static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 __user *sc)
{
u32 used_math;
int err = 0;
#endif
};
-int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from)
+int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
{
int err;
err |= __put_user(from->si_uid, &to->si_uid);
break;
case __SI_FAULT >> 16:
- err |= __put_user((long)from->si_addr, &to->si_addr);
+ err |= __put_user((unsigned long)from->si_addr, &to->si_addr);
break;
case __SI_POLL >> 16:
err |= __put_user(from->si_band, &to->si_band);
__attribute_used__ noinline static void
_sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
{
- struct sigframe *frame;
+ struct sigframe __user *frame;
sigset_t blocked;
- frame = (struct sigframe *) regs.regs[29];
+ frame = (struct sigframe __user *) regs.regs[29];
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&blocked, &frame->sf_mask, sizeof(blocked)))
__attribute_used__ noinline static void
_sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
{
- struct rt_sigframe32 *frame;
+ struct rt_sigframe32 __user *frame;
mm_segment_t old_fs;
sigset_t set;
stack_t st;
s32 sp;
- frame = (struct rt_sigframe32 *) regs.regs[29];
+ frame = (struct rt_sigframe32 __user *) regs.regs[29];
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set)))
call it and ignore errors. */
old_fs = get_fs();
set_fs (KERNEL_DS);
- do_sigaltstack(&st, NULL, regs.regs[29]);
+ do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]);
set_fs (old_fs);
/*
}
static inline int setup_sigcontext32(struct pt_regs *regs,
- struct sigcontext32 *sc)
+ struct sigcontext32 __user *sc)
{
int err = 0;
/*
* Determine which stack to use..
*/
-static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
- size_t frame_size)
+static inline void __user *get_sigframe(struct k_sigaction *ka,
+ struct pt_regs *regs,
+ size_t frame_size)
{
unsigned long sp;
if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
sp = current->sas_ss_sp + current->sas_ss_size;
- return (void *)((sp - frame_size) & ALMASK);
+ return (void __user *)((sp - frame_size) & ALMASK);
}
int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set)
{
- struct sigframe *frame;
+ struct sigframe __user *frame;
int err = 0;
frame = get_sigframe(ka, regs, sizeof(*frame));
int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set, siginfo_t *info)
{
- struct rt_sigframe32 *frame;
+ struct rt_sigframe32 __user *frame;
int err = 0;
s32 sp;
}
asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 *act,
- struct sigaction32 *oact,
+ struct sigaction32 __user *oact,
unsigned int sigsetsize)
{
struct k_sigaction new_sa, old_sa;
if (!access_ok(VERIFY_READ, act, sizeof(*act)))
return -EFAULT;
err |= __get_user(handler, &act->sa_handler);
- new_sa.sa.sa_handler = (void*)(s64)handler;
+ new_sa.sa.sa_handler = (void __user *)(s64)handler;
err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags);
err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask);
if (err)
}
asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t *set,
- compat_sigset_t *oset, unsigned int sigsetsize)
+ compat_sigset_t __user *oset, unsigned int sigsetsize)
{
sigset_t old_set, new_set;
int ret;
return -EFAULT;
set_fs (KERNEL_DS);
- ret = sys_rt_sigprocmask(how, set ? &new_set : NULL,
- oset ? &old_set : NULL, sigsetsize);
+ ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL,
+ oset ? (sigset_t __user *)&old_set : NULL,
+ sigsetsize);
set_fs (old_fs);
if (!ret && oset && put_sigset(&old_set, oset))
return ret;
}
-asmlinkage int sys32_rt_sigpending(compat_sigset_t *uset,
+asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset,
unsigned int sigsetsize)
{
int ret;
mm_segment_t old_fs = get_fs();
set_fs (KERNEL_DS);
- ret = sys_rt_sigpending(&set, sigsetsize);
+ ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize);
set_fs (old_fs);
if (!ret && put_sigset(&set, uset))
return ret;
}
-asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t *uinfo)
+asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *uinfo)
{
siginfo_t info;
int ret;
copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE))
return -EFAULT;
set_fs (KERNEL_DS);
- ret = sys_rt_sigqueueinfo(pid, sig, &info);
+ ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info);
set_fs (old_fs);
return ret;
}
#define __NR_N32_rt_sigreturn 6211
#define __NR_N32_restart_syscall 6214
+#define DEBUG_SIG 0
+
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
/* IRIX compatible stack_t */
__attribute_used__ noinline static void
_sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
{
- struct rt_sigframe_n32 *frame;
+ struct rt_sigframe_n32 __user *frame;
sigset_t set;
stack_t st;
s32 sp;
- frame = (struct rt_sigframe_n32 *) regs.regs[29];
+ frame = (struct rt_sigframe_n32 __user *) regs.regs[29];
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set)))
/* It is more difficult to avoid calling this function than to
call it and ignore errors. */
- do_sigaltstack(&st, NULL, regs.regs[29]);
+ do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]);
/*
* Don't let your children do this ...
int setup_rt_frame_n32(struct k_sigaction * ka,
struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info)
{
- struct rt_sigframe_n32 *frame;
+ struct rt_sigframe_n32 __user *frame;
int err = 0;
s32 sp;
#endif
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
status_set |= ST0_XX;
- change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
+ change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
status_set);
if (cpu_has_dsp)
#include <linux/config.h>
+#include <asm/asm-offsets.h>
#include <asm-generic/vmlinux.lds.h>
#undef mips /* CPP really sucks for this job */
we can shorten the on-disk segment size. */
.sdata : { *(.sdata) }
- . = ALIGN(4096);
+ . = ALIGN(_PAGE_SIZE);
__nosave_begin = .;
.data_nosave : { *(.data.nosave) }
- . = ALIGN(4096);
+ . = ALIGN(_PAGE_SIZE);
__nosave_end = .;
. = ALIGN(32);
_edata = .; /* End of data section */
/* will be freed after init */
- . = ALIGN(4096); /* Init code and data */
+ . = ALIGN(_PAGE_SIZE); /* Init code and data */
__init_begin = .;
.init.text : {
_sinittext = .;
.con_initcall.init : { *(.con_initcall.init) }
__con_initcall_end = .;
SECURITY_INIT
- . = ALIGN(4096);
+ . = ALIGN(_PAGE_SIZE);
__initramfs_start = .;
.init.ramfs : { *(.init.ramfs) }
__initramfs_end = .;
__per_cpu_start = .;
.data.percpu : { *(.data.percpu) }
__per_cpu_end = .;
- . = ALIGN(4096);
+ . = ALIGN(_PAGE_SIZE);
__init_end = .;
/* freed after init ends here */
*/
#include <linux/config.h>
#include <linux/kernel.h>
+#include <linux/pm.h>
+
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/lasat/lasat.h>
+
#include "picvue.h"
#include "prom.h"
{
_machine_restart = lasat_machine_restart;
_machine_halt = lasat_machine_halt;
- _machine_power_off = lasat_machine_halt;
+ pm_power_off = lasat_machine_halt;
}
printk("task->mm == %8p\n", t->mm);
//printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd);
- if (addr > KSEG0)
+ if (addr > KSEG0) {
page_dir = pgd_offset_k(0);
- else if (t->mm) {
- page_dir = pgd_offset(t->mm, 0);
- printk("page_dir == %08x\n", (unsigned int) page_dir);
- } else
- printk("Current thread has no mm\n");
-
- if (addr > KSEG0)
pgd = pgd_offset_k(addr);
- else if (t->mm) {
+ } else if (t->mm) {
+ page_dir = pgd_offset(t->mm, 0);
pgd = pgd_offset(t->mm, addr);
- printk("pgd == %08x, ", (unsigned int) pgd);
- pud = pud_offset(pgd, addr);
- printk("pud == %08x, ", (unsigned int) pud);
+ } else {
+ printk("Current thread has no mm\n");
+ return;
+ }
+ printk("page_dir == %08x\n", (unsigned int) page_dir);
+ printk("pgd == %08x, ", (unsigned int) pgd);
+ pud = pud_offset(pgd, addr);
+ printk("pud == %08x, ", (unsigned int) pud);
- pmd = pmd_offset(pud, addr);
- printk("pmd == %08x, ", (unsigned int) pmd);
+ pmd = pmd_offset(pud, addr);
+ printk("pmd == %08x, ", (unsigned int) pmd);
- pte = pte_offset(pmd, addr);
- printk("pte == %08x, ", (unsigned int) pte);
- } else
- printk("Current thread has no mm\n");
+ pte = pte_offset(pmd, addr);
+ printk("pte == %08x, ", (unsigned int) pte);
page = *pte;
#ifdef CONFIG_64BIT_PHYS_ADDR
CLEARCX;
FLUSHXDP;
+ /*
+ * Invert the sign ALWAYS to prevent an endless recursion on
+ * pow() in libc.
+ */
+ /* quick fix up */
+ DPSIGN(x) ^= 1;
+
if (xc == IEEE754_CLASS_SNAN) {
+ ieee754dp y = ieee754dp_indef();
SETCX(IEEE754_INVALID_OPERATION);
- return ieee754dp_nanxcpt(ieee754dp_indef(), "neg");
+ DPSIGN(y) = DPSIGN(x);
+ return ieee754dp_nanxcpt(y, "neg");
}
if (ieee754dp_isnan(x)) /* but not infinity */
return ieee754dp_nanxcpt(x, "neg", x);
-
- /* quick fix up */
- DPSIGN(x) ^= 1;
return x;
}
CLEARCX;
FLUSHXSP;
+ /*
+ * Invert the sign ALWAYS to prevent an endless recursion on
+ * pow() in libc.
+ */
+ /* quick fix up */
+ SPSIGN(x) ^= 1;
+
if (xc == IEEE754_CLASS_SNAN) {
+ ieee754sp y = ieee754sp_indef();
SETCX(IEEE754_INVALID_OPERATION);
- return ieee754sp_nanxcpt(ieee754sp_indef(), "neg");
+ SPSIGN(y) = SPSIGN(x);
+ return ieee754sp_nanxcpt(y, "neg");
}
if (ieee754sp_isnan(x)) /* but not infinity */
return ieee754sp_nanxcpt(x, "neg", x);
-
- /* quick fix up */
- SPSIGN(x) ^= 1;
return x;
}
*
*/
#include <linux/config.h>
+#include <linux/pm.h>
#include <asm/io.h>
#include <asm/reboot.h>
_machine_restart = mips_machine_restart;
_machine_halt = mips_machine_halt;
#if defined(CONFIG_MIPS_ATLAS)
- _machine_power_off = atlas_machine_power_off;
+ pm_power_off = atlas_machine_power_off;
#endif
#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD)
- _machine_power_off = mips_machine_halt;
+ pm_power_off = mips_machine_halt;
#endif
}
}
struct flush_icache_range_args {
- unsigned long __user start;
- unsigned long __user end;
+ unsigned long start;
+ unsigned long end;
};
static inline void local_r4k_flush_icache_range(void *args)
}
}
-static void r4k_flush_icache_range(unsigned long __user start,
- unsigned long __user end)
+static void r4k_flush_icache_range(unsigned long start, unsigned long end)
{
struct flush_icache_range_args args;
unsigned long end);
void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
unsigned long pfn);
-void (*flush_icache_range)(unsigned long __user start,
- unsigned long __user end);
+void (*flush_icache_range)(unsigned long start, unsigned long end);
void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
/* MIPS specific cache operations */
* We could optimize the case where the cache argument is not BCACHE but
* that seems very atypical use ...
*/
-asmlinkage int sys_cacheflush(unsigned long __user addr,
+asmlinkage int sys_cacheflush(unsigned long addr,
unsigned long bytes, unsigned int cache)
{
if (bytes == 0)
#include <linux/bootmem.h>
#include <linux/highmem.h>
#include <linux/swap.h>
+#include <linux/proc_fs.h>
#include <asm/bootinfo.h>
#include <asm/cachectl.h>
return 0;
}
+static struct kcore_list kcore_mem, kcore_vmalloc;
+#ifdef CONFIG_64BIT
+static struct kcore_list kcore_kseg0;
+#endif
+
void __init mem_init(void)
{
unsigned long codesize, reservedpages, datasize, initsize;
datasize = (unsigned long) &_edata - (unsigned long) &_etext;
initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
+#ifdef CONFIG_64BIT
+ if ((unsigned long) &_text > (unsigned long) CKSEG0)
+ /* The -4 is a hack so that user tools don't have to handle
+ the overflow. */
+ kclist_add(&kcore_kseg0, (void *) CKSEG0, 0x80000000 - 4);
+#endif
+ kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT);
+ kclist_add(&kcore_vmalloc, (void *)VMALLOC_START,
+ VMALLOC_END-VMALLOC_START);
+
printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
"%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n",
(unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
#include <linux/pci.h>
#include <linux/swap.h>
#include <linux/ioport.h>
+#include <linux/pm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
_machine_restart = momenco_jaguar_restart;
_machine_halt = momenco_jaguar_halt;
- _machine_power_off = momenco_jaguar_power_off;
+ pm_power_off = momenco_jaguar_power_off;
/*
* initrd_start = (ulong)jaguar_initrd_start;
#include <linux/timex.h>
#include <linux/bootmem.h>
#include <linux/mv643xx.h>
+#include <linux/pm.h>
+
#include <asm/time.h>
#include <asm/page.h>
#include <asm/bootinfo.h>
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
- _machine_power_off = momenco_ocelot_power_off;
+ pm_power_off = momenco_ocelot_power_off;
/* Wired TLB entries */
setup_wired_tlb_entries();
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
+#include <linux/pm.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
+
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
- _machine_power_off = momenco_ocelot_power_off;
+ pm_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (ulong)ocelot_initrd_start;
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
+#include <linux/pm.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
+
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
- _machine_power_off = momenco_ocelot_power_off;
+ pm_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (ulong)ocelot_initrd_start;
oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
+oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
case CPU_20KC:
case CPU_24K:
case CPU_25KF:
+ case CPU_34K:
+ case CPU_SB1:
+ case CPU_SB1A:
lmodel = &op_model_mipsxx;
break;
op_model_mipsxx.cpu_type = "mips/25K";
break;
+#ifndef CONFIG_SMP
+ case CPU_34K:
+ op_model_mipsxx.cpu_type = "mips/34K";
+ break;
+#endif
+
case CPU_5KC:
op_model_mipsxx.cpu_type = "mips/5K";
break;
+ case CPU_SB1:
+ case CPU_SB1A:
+ op_model_mipsxx.cpu_type = "mips/sb1";
+ break;
+
default:
printk(KERN_ERR "Profiling unsupported for this CPU\n");
obj-$(CONFIG_SGI_IP27) += pci-ip27.o
obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
+obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
#include <asm/io.h>
#include <asm/gt64120.h>
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
extern int cobalt_board_id;
pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
if (lt < 64)
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
* host bridge.
*/
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
/*
* The code described by the comment below has been removed
#include <asm/io.h>
#include <asm/gt64120.h>
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
/*
* Device 31 on the GT64111 is used to generate PCI special
/* turn on ExpMemEn */
cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
- printk("PCIFeatureCtrl = %x\n", cmdreg);
WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
cmdreg | 0x10);
cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
- printk("PCIFeatureCtrl = %x\n", cmdreg);
/*
* Establish mappings in KSEG2 (kernel virtual) to PCI I/O
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/serial_ip3106.h>
+#include <linux/pm.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
_machine_restart = pnx8550_machine_restart;
_machine_halt = pnx8550_machine_halt;
- _machine_power_off = pnx8550_machine_power_off;
+ pm_power_off = pnx8550_machine_power_off;
board_time_init = pnx8550_time_init;
board_timer_setup = pnx8550_timer_setup;
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/delay.h>
+#include <linux/pm.h>
#include <linux/smp.h>
#include <asm/io.h>
/* Callbacks for halt, restart */
_machine_restart = (void (*)(char *)) prom_exit;
_machine_halt = prom_halt;
- _machine_power_off = prom_halt;
+ pm_power_off = prom_halt;
debug_vectors = cv;
arcs_cmdline[0] = '\0';
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1997, 1998, 2001, 2003 by Ralf Baechle
+ * Copyright (C) 1997, 1998, 2001, 03, 05, 06 by Ralf Baechle
*/
+#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/ds1286.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/notifier.h>
+#include <linux/pm.h>
#include <linux/timer.h>
#include <asm/io.h>
#define MACHINE_PANICED 1
#define MACHINE_SHUTTING_DOWN 2
-static int machine_state = 0;
-static void sgi_machine_restart(char *command) __attribute__((noreturn));
-static void sgi_machine_halt(void) __attribute__((noreturn));
-static void sgi_machine_power_off(void) __attribute__((noreturn));
+static int machine_state;
-static void sgi_machine_restart(char *command)
-{
- if (machine_state & MACHINE_SHUTTING_DOWN)
- sgi_machine_power_off();
- sgimc->cpuctrl0 |= SGIMC_CCTRL0_SYSINIT;
- while (1);
-}
-
-static void sgi_machine_halt(void)
-{
- if (machine_state & MACHINE_SHUTTING_DOWN)
- sgi_machine_power_off();
- ArcEnterInteractiveMode();
-}
-
-static void sgi_machine_power_off(void)
+static void ATTRIB_NORET sgi_machine_power_off(void)
{
unsigned int tmp;
}
}
+static void ATTRIB_NORET sgi_machine_restart(char *command)
+{
+ if (machine_state & MACHINE_SHUTTING_DOWN)
+ sgi_machine_power_off();
+ sgimc->cpuctrl0 |= SGIMC_CCTRL0_SYSINIT;
+ while (1);
+}
+
+static void ATTRIB_NORET sgi_machine_halt(void)
+{
+ if (machine_state & MACHINE_SHUTTING_DOWN)
+ sgi_machine_power_off();
+ ArcEnterInteractiveMode();
+}
+
static void power_timeout(unsigned long data)
{
sgi_machine_power_off();
sgi_ioc_reset ^= (SGIOC_RESET_LC0OFF|SGIOC_RESET_LC1OFF);
sgioc->reset = sgi_ioc_reset;
- mod_timer(&blink_timer, jiffies+data);
+ mod_timer(&blink_timer, jiffies + data);
}
static void debounce(unsigned long data)
del_timer(&debounce_timer);
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
/* Interrupt still being sent. */
- debounce_timer.expires = jiffies + 5; /* 0.05s */
+ debounce_timer.expires = jiffies + (HZ / 20); /* 0.05s */
add_timer(&debounce_timer);
sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR |
indy_volume_button(1);
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
- volume_timer.expires = jiffies + 1;
+ volume_timer.expires = jiffies + (HZ / 100);
add_timer(&volume_timer);
}
}
indy_volume_button(-1);
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
- volume_timer.expires = jiffies + 1;
+ volume_timer.expires = jiffies + (HZ / 100);
add_timer(&volume_timer);
}
}
if (!(buttons & SGIOC_PANEL_VOLUPINTR)) {
init_timer(&volume_timer);
volume_timer.function = volume_up_button;
- volume_timer.expires = jiffies + 1;
+ volume_timer.expires = jiffies + (HZ / 100);
add_timer(&volume_timer);
}
/* Volume down button was pressed */
if (!(buttons & SGIOC_PANEL_VOLDNINTR)) {
init_timer(&volume_timer);
volume_timer.function = volume_down_button;
- volume_timer.expires = jiffies + 1;
+ volume_timer.expires = jiffies + (HZ / 100);
add_timer(&volume_timer);
}
{
_machine_restart = sgi_machine_restart;
_machine_halt = sgi_machine_halt;
- _machine_power_off = sgi_machine_power_off;
+ pm_power_off = sgi_machine_power_off;
request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL);
init_timer(&blink_timer);
void __init plat_setup(void)
{
char *ctype;
+ char *cserial;
board_be_init = ip22_be_init;
ip22_time_init();
/* ARCS console environment variable is set to "g?" for
* graphics console, it is set to "d" for the first serial
* line and "d2" for the second serial line.
+ *
+ * Need to check if the case is 'g' but no keyboard:
+ * (ConsoleIn/Out = serial)
*/
ctype = ArcGetEnvironmentVariable("console");
- if (ctype && *ctype == 'd') {
+ cserial = ArcGetEnvironmentVariable("ConsoleOut");
+
+ if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) {
static char options[8];
char *baud = ArcGetEnvironmentVariable("dbaud");
if (baud)
add_preferred_console("ttyS", *(ctype + 1) == '2' ? 1 : 0,
baud ? options : NULL);
} else if (!ctype || *ctype != 'g') {
- /* Use ARC if we don't want serial ('d') or Newport ('g'). */
+ /* Use ARC if we don't want serial ('d') or graphics ('g'). */
prom_flags |= PROM_FLAG_USE_AS_CONSOLE;
add_preferred_console("arc", 0, NULL);
}
*
* Reset an IP27.
*
- * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1997, 1998, 1999, 2000, 06 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#include <linux/config.h>
#include <linux/smp.h>
#include <linux/mmzone.h>
#include <linux/nodemask.h>
+#include <linux/pm.h>
#include <asm/io.h>
#include <asm/irq.h>
{
_machine_restart = ip27_machine_restart;
_machine_halt = ip27_machine_halt;
- _machine_power_off = ip27_machine_power_off;
+ pm_power_off = ip27_machine_power_off;
}
#include <linux/delay.h>
#include <linux/ds17287rtc.h>
#include <linux/interrupt.h>
+#include <linux/pm.h>
#include <asm/addrspace.h>
#include <asm/irq.h>
_machine_restart = ip32_machine_restart;
_machine_halt = ip32_machine_halt;
- _machine_power_off = ip32_machine_power_off;
+ pm_power_off = ip32_machine_power_off;
init_timer(&blink_timer);
blink_timer.function = blink_timeout;
#include <linux/mm.h>
#include <linux/blkdev.h>
#include <linux/bootmem.h>
+#include <linux/pm.h>
#include <linux/smp.h>
#include <asm/bootinfo.h>
_machine_restart = cfe_linux_restart;
_machine_halt = cfe_linux_halt;
- _machine_power_off = cfe_linux_halt;
+ pm_power_off = cfe_linux_halt;
/*
* Check if a loader was used; if NOT, the 4 arguments are
#include <linux/bootmem.h>
#include <linux/smp.h>
#include <linux/initrd.h>
+#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
{
_machine_restart = (void (*)(char *))prom_linux_exit;
_machine_halt = prom_linux_exit;
- _machine_power_off = prom_linux_exit;
+ pm_power_off = prom_linux_exit;
strcpy(arcs_cmdline, "root=/dev/ram0 ");
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/config.h>
+#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/string.h>
/* Setup code likely to be common to all SiByte platforms */
-static inline int sys_rev_decode(void)
+static int __init sys_rev_decode(void)
{
int ret = 0;
return ret;
}
-static inline int setup_bcm1250(void)
+static int __init setup_bcm1250(void)
{
int ret = 0;
return ret;
}
-static inline int setup_bcm112x(void)
+static int __init setup_bcm112x(void)
{
int ret = 0;
return ret;
}
-void sb1250_setup(void)
+void __init sb1250_setup(void)
{
uint64_t sys_rev;
int plldiv;
soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
prom_printf("Board type: %s\n", get_system_type());
- switch(war_pass) {
+ switch (war_pass) {
case K_SYS_REVISION_BCM1250_PASS1:
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
- prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
+ prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
+ "and the kernel doesn't have the proper "
+ "workarounds compiled in. @@@@\n");
bad_config = 1;
#endif
break;
case K_SYS_REVISION_BCM1250_PASS2:
/* Pass 2 - easiest as default for now - so many numbers */
-#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
- prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
+#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
+ !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
+ prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the "
+ "kernel doesn't have the proper workarounds "
+ "compiled in. @@@@\n");
bad_config = 1;
#endif
#ifdef CONFIG_CPU_HAS_PREFETCH
- prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n");
+ prom_printf("@@@@ Prefetches may be enabled in this kernel, "
+ "but are buggy on this board. @@@@\n");
bad_config = 1;
#endif
break;
case K_SYS_REVISION_BCM1250_PASS2_2:
#ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
- prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
+ prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the "
+ "kernel doesn't have the proper workarounds "
+ "compiled in. @@@@\n");
bad_config = 1;
#endif
-#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH)
- prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n");
+#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
+ !defined(CONFIG_CPU_HAS_PREFETCH)
+ prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is "
+ "conservatively configured for an 'A' stepping. "
+ "@@@@\n");
#endif
break;
default:
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1996, 97, 98, 2000, 03, 04 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
*/
#include <linux/config.h>
#include <linux/eisa.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
+#include <linux/pm.h>
#include <linux/pci.h>
#include <linux/console.h>
#include <linux/fb.h>
_machine_restart = sni_machine_restart;
_machine_halt = sni_machine_halt;
- _machine_power_off = sni_machine_power_off;
+ pm_power_off = sni_machine_power_off;
sni_display_setup();
void __init prom_init(void)
{
- const char* toshiba_name_list[] = GROUP_TOSHIBA_NAMES;
extern int tx4927_get_mem_size(void);
extern char* toshiba_name;
int msize;
mips_machgroup = MACH_GROUP_TOSHIBA;
- if ((read_c0_prid() & 0xff) == PRID_REV_TX4927)
+ if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) {
mips_machtype = MACH_TOSHIBA_RBTX4927;
- else
+ toshiba_name = "TX4927";
+ } else {
mips_machtype = MACH_TOSHIBA_RBTX4937;
-
- toshiba_name = toshiba_name_list[mips_machtype];
+ toshiba_name = "TX4937";
+ }
msize = tx4927_get_mem_size();
add_memory_region(0, msize << 20, BOOT_MEM_RAM);
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
+#include <linux/pm.h>
+
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/io.h>
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_io_port_base",
mips_io_port_base);
-
- TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
- "setup pci_io_resource to 0x%08lx 0x%08lx\n",
- pci_io_resource.start,
- pci_io_resource.end);
- TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
- "setup pci_mem_resource to 0x%08lx 0x%08lx\n",
- pci_mem_resource.start,
- pci_mem_resource.end);
-
if (!called) {
printk
- ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
+ ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
+ toshiba_name,
(unsigned short) (tx4927_pcicptr->pciid >> 16),
(unsigned short) (tx4927_pcicptr->pciid & 0xffff),
(unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
int pciclk = 0;
- switch ((unsigned long) tx4927_ccfgptr->
- ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
- case TX4927_CCFG_PCIDIVMODE_2_5:
- pciclk = tx4927_cpu_clock * 2 / 5;
- break;
- case TX4927_CCFG_PCIDIVMODE_3:
- pciclk = tx4927_cpu_clock / 3;
- break;
- case TX4927_CCFG_PCIDIVMODE_5:
- pciclk = tx4927_cpu_clock / 5;
- break;
- case TX4927_CCFG_PCIDIVMODE_6:
- pciclk = tx4927_cpu_clock / 6;
- break;
- }
+ if (mips_machtype == MACH_TOSHIBA_RBTX4937)
+ switch ((unsigned long) tx4927_ccfgptr->
+ ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
+ case TX4937_CCFG_PCIDIVMODE_4:
+ pciclk = tx4927_cpu_clock / 4;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_4_5:
+ pciclk = tx4927_cpu_clock * 2 / 9;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_5:
+ pciclk = tx4927_cpu_clock / 5;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_5_5:
+ pciclk = tx4927_cpu_clock * 2 / 11;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_8:
+ pciclk = tx4927_cpu_clock / 8;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_9:
+ pciclk = tx4927_cpu_clock / 9;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_10:
+ pciclk = tx4927_cpu_clock / 10;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_11:
+ pciclk = tx4927_cpu_clock / 11;
+ break;
+ }
+
+ else
+ switch ((unsigned long) tx4927_ccfgptr->
+ ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
+ case TX4927_CCFG_PCIDIVMODE_2_5:
+ pciclk = tx4927_cpu_clock * 2 / 5;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_3:
+ pciclk = tx4927_cpu_clock / 3;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_5:
+ pciclk = tx4927_cpu_clock / 5;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_6:
+ pciclk = tx4927_cpu_clock / 6;
+ break;
+ }
+
printk("Internal(%dMHz)", pciclk / 1000000);
} else {
int pciclk = 0;
":ResetRoutines\n");
_machine_restart = toshiba_rbtx4927_restart;
_machine_halt = toshiba_rbtx4927_halt;
- _machine_power_off = toshiba_rbtx4927_power_off;
+ pm_power_off = toshiba_rbtx4927_power_off;
#ifdef CONFIG_PCI
/* PCIC */
/*
* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
- * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
+ *
+ * For TX4927:
+ * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
* CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
* CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
* CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
* CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
* i.e. S9[3]: ON (83MHz), OFF (100MHz)
+ *
+ * For TX4937:
+ * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
+ * PCIDIVMODE[10] is 0.
+ * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
+ * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
+ * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
+ * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
+ * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
+ * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
+ *
*/
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
- "ccfg is %lx, DIV is %x\n",
- (unsigned long) tx4927_ccfgptr->
- ccfg, TX4927_CCFG_PCIDIVMODE_MASK);
+ "ccfg is %lx, PCIDIVMODE is %x\n",
+ (unsigned long) tx4927_ccfgptr->ccfg,
+ (unsigned long) tx4927_ccfgptr->ccfg &
+ (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
+ TX4937_CCFG_PCIDIVMODE_MASK :
+ TX4927_CCFG_PCIDIVMODE_MASK));
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
"PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
(unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIXARB);
- TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
- "PCIDIVMODE is %lx\n",
- (unsigned long) tx4927_ccfgptr->
- ccfg & TX4927_CCFG_PCIDIVMODE_MASK);
-
- switch ((unsigned long) tx4927_ccfgptr->
- ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
- case TX4927_CCFG_PCIDIVMODE_2_5:
- case TX4927_CCFG_PCIDIVMODE_5:
- tx4927_cpu_clock = 166000000; /* 166MHz */
- break;
- default:
- tx4927_cpu_clock = 200000000; /* 200MHz */
- }
+ if (mips_machtype == MACH_TOSHIBA_RBTX4937)
+ switch ((unsigned long)tx4927_ccfgptr->
+ ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
+ case TX4937_CCFG_PCIDIVMODE_8:
+ case TX4937_CCFG_PCIDIVMODE_4:
+ tx4927_cpu_clock = 266666666; /* 266MHz */
+ break;
+ case TX4937_CCFG_PCIDIVMODE_9:
+ case TX4937_CCFG_PCIDIVMODE_4_5:
+ tx4927_cpu_clock = 300000000; /* 300MHz */
+ break;
+ default:
+ tx4927_cpu_clock = 333333333; /* 333MHz */
+ }
+ else
+ switch ((unsigned long)tx4927_ccfgptr->
+ ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
+ case TX4927_CCFG_PCIDIVMODE_2_5:
+ case TX4927_CCFG_PCIDIVMODE_5:
+ tx4927_cpu_clock = 166666666; /* 166MHz */
+ break;
+ default:
+ tx4927_cpu_clock = 200000000; /* 200MHz */
+ }
/* CCFG */
/* enable Timeout BusError */
#include <linux/interrupt.h>
#include <linux/console.h>
#include <linux/pci.h>
+#include <linux/pm.h>
+
#include <asm/wbflush.h>
#include <asm/reboot.h>
#include <asm/irq.h>
_machine_restart = rbtx4938_machine_restart;
_machine_halt = rbtx4938_machine_halt;
- _machine_power_off = rbtx4938_machine_power_off;
+ pm_power_off = rbtx4938_machine_power_off;
*rbtx4938_led_ptr = 0xff;
printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
+#include <linux/pm.h>
#include <linux/smp.h>
#include <linux/types.h>
_machine_restart = vr41xx_restart;
_machine_halt = vr41xx_halt;
- _machine_power_off = vr41xx_power_off;
+ pm_power_off = vr41xx_power_off;
return 0;
}
{
CommandList_struct *cmd = rq->completion_data;
ctlr_info_t *h = hba[cmd->ctlr];
+ unsigned long flags;
u64bit temp64;
int i, ddir;
printk("Done with %p\n", rq);
#endif /* CCISS_DEBUG */
- spin_lock_irq(&h->lock);
+ spin_lock_irqsave(&h->lock, flags);
end_that_request_last(rq, rq->errors);
cmd_free(h, cmd,1);
- spin_unlock_irq(&h->lock);
+ spin_unlock_irqrestore(&h->lock, flags);
}
/* checks the status of the job and calls complete buffers to mark all
dma_addr_t tx_bufs_dma;
signed char phys[4]; /* MII device addresses. */
char twistie, twist_row, twist_col; /* Twister tune state. */
+ unsigned int watchdog_fired : 1;
unsigned int default_port : 4; /* Last dev->if_port value. */
unsigned int have_thread : 1;
spinlock_t lock;
static void __set_rx_mode (struct net_device *dev);
static void rtl8139_hw_start (struct net_device *dev);
static void rtl8139_thread (void *_data);
+static void rtl8139_tx_timeout_task(void *_data);
static struct ethtool_ops rtl8139_ethtool_ops;
/* write MMIO register, with flush */
{
struct net_device *dev = _data;
struct rtl8139_private *tp = netdev_priv(dev);
- unsigned long thr_delay;
+ unsigned long thr_delay = next_tick;
- if (rtnl_shlock_nowait() == 0) {
+ if (tp->watchdog_fired) {
+ tp->watchdog_fired = 0;
+ rtl8139_tx_timeout_task(_data);
+ } else if (rtnl_shlock_nowait() == 0) {
rtl8139_thread_iter (dev, tp, tp->mmio_addr);
rtnl_unlock ();
-
- thr_delay = next_tick;
} else {
/* unlikely race. mitigate with fast poll. */
thr_delay = HZ / 2;
if (tp->have_thread) {
cancel_rearming_delayed_work(&tp->thread);
tp->have_thread = 0;
- }
+ } else
+ flush_scheduled_work();
}
static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
/* XXX account for unsent Tx packets in tp->stats.tx_dropped */
}
-
-static void rtl8139_tx_timeout (struct net_device *dev)
+static void rtl8139_tx_timeout_task (void *_data)
{
+ struct net_device *dev = _data;
struct rtl8139_private *tp = netdev_priv(dev);
void __iomem *ioaddr = tp->mmio_addr;
int i;
u8 tmp8;
- unsigned long flags;
printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
"media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
if (tmp8 & CmdTxEnb)
RTL_W8 (ChipCmd, CmdRxEnb);
- spin_lock(&tp->rx_lock);
+ spin_lock_bh(&tp->rx_lock);
/* Disable interrupts by clearing the interrupt mask. */
RTL_W16 (IntrMask, 0x0000);
/* Stop a shared interrupt from scavenging while we are. */
- spin_lock_irqsave (&tp->lock, flags);
+ spin_lock_irq(&tp->lock);
rtl8139_tx_clear (tp);
- spin_unlock_irqrestore (&tp->lock, flags);
+ spin_unlock_irq(&tp->lock);
/* ...and finally, reset everything */
if (netif_running(dev)) {
rtl8139_hw_start (dev);
netif_wake_queue (dev);
}
- spin_unlock(&tp->rx_lock);
+ spin_unlock_bh(&tp->rx_lock);
}
+static void rtl8139_tx_timeout (struct net_device *dev)
+{
+ struct rtl8139_private *tp = netdev_priv(dev);
+
+ if (!tp->have_thread) {
+ INIT_WORK(&tp->thread, rtl8139_tx_timeout_task, dev);
+ schedule_delayed_work(&tp->thread, next_tick);
+ } else
+ tp->watchdog_fired = 1;
+
+}
static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
{
#
menu "Network device support"
+ depends on NET
config NETDEVICES
- depends on NET
default y if UML
bool "Network device support"
---help---
If unsure, say Y.
-# All the following symbols are dependent on NETDEVICES - do not repeat
-# that for each of the symbols.
-if NETDEVICES
config IFB
tristate "Intermediate Functional Block support"
If you want to log kernel messages over the network, enable this.
See <file:Documentation/networking/netconsole.txt> for details.
-endif #NETDEVICES
-
config NETPOLL
def_bool NETCONSOLE
}
#define BOND_INTERSECT_FEATURES \
- (NETIF_F_SG|NETIF_F_IP_CSUM|NETIF_F_NO_CSUM|NETIF_F_HW_CSUM)
+ (NETIF_F_SG|NETIF_F_IP_CSUM|NETIF_F_NO_CSUM|NETIF_F_HW_CSUM|\
+ NETIF_F_TSO|NETIF_F_UFO)
/*
* Compute the common dev->feature set available to all slaves. Some
NETIF_F_HW_CSUM)))
features &= ~NETIF_F_SG;
+ /*
+ * features will include NETIF_F_TSO (NETIF_F_UFO) iff all
+ * slave devices support NETIF_F_TSO (NETIF_F_UFO), which
+ * implies that all slaves also support scatter-gather
+ * (NETIF_F_SG), which implies that features also includes
+ * NETIF_F_SG. So no need to check whether we have an
+ * illegal combination of NETIF_F_{TSO,UFO} and
+ * !NETIF_F_SG
+ */
+
features |= (bond_dev->features & ~BOND_INTERSECT_FEATURES);
bond_dev->features = features;
static struct ethtool_ops bond_ethtool_ops = {
.get_tx_csum = ethtool_op_get_tx_csum,
+ .get_tso = ethtool_op_get_tso,
+ .get_ufo = ethtool_op_get_ufo,
.get_sg = ethtool_op_get_sg,
.get_drvinfo = bond_ethtool_get_drvinfo,
};
char *ifname;
int i, res, found, ret = count;
struct slave *slave;
- struct net_device *dev = 0;
+ struct net_device *dev = NULL;
struct bonding *bond = to_bond(cd);
/* Quick sanity check -- is the bond interface up? */
printk(KERN_INFO DRV_NAME
": %s: Setting primary slave to None.\n",
bond->dev->name);
- bond->primary_slave = 0;
+ bond->primary_slave = NULL;
bond_select_active_slave(bond);
} else {
printk(KERN_INFO DRV_NAME
printk(KERN_INFO DRV_NAME
": %s: Setting active slave to None.\n",
bond->dev->name);
- bond->primary_slave = 0;
+ bond->primary_slave = NULL;
bond_select_active_slave(bond);
} else {
printk(KERN_INFO DRV_NAME
retval = pci_enable_wake(pdev, 0, 0);
if (retval)
DPRINTK(PROBE,ERR, "Error clearing wake events\n");
- if(e100_hw_init(nic))
- DPRINTK(HW, ERR, "e100_hw_init failed\n");
netif_device_attach(netdev);
if(netif_running(netdev))
/* get a pointer to the register memory */
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = (struct gfar *)
- ioremap(r->start, sizeof (struct gfar));
+ priv->regs = ioremap(r->start, sizeof (struct gfar));
if (NULL == priv->regs) {
err = -ENOMEM;
return 0;
register_fail:
- iounmap((void *) priv->regs);
+ iounmap(priv->regs);
regs_fail:
free_netdev(dev);
return err;
platform_set_drvdata(pdev, NULL);
- iounmap((void *) priv->regs);
+ iounmap(priv->regs);
free_netdev(dev);
return 0;
/* Zero out the rmon mib registers if it has them */
if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
- memset((void *) &(priv->regs->rmon), 0,
- sizeof (struct rmon_mib));
+ memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
/* Mask off the CAM interrupts */
gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
void gfar_halt(struct net_device *dev)
{
struct gfar_private *priv = netdev_priv(dev);
- struct gfar *regs = priv->regs;
+ struct gfar __iomem *regs = priv->regs;
u32 tempval;
/* Mask all interrupts */
void stop_gfar(struct net_device *dev)
{
struct gfar_private *priv = netdev_priv(dev);
- struct gfar *regs = priv->regs;
+ struct gfar __iomem *regs = priv->regs;
unsigned long flags;
phy_stop(priv->phydev);
void gfar_start(struct net_device *dev)
{
struct gfar_private *priv = netdev_priv(dev);
- struct gfar *regs = priv->regs;
+ struct gfar __iomem *regs = priv->regs;
u32 tempval;
/* Enable Rx and Tx in MACCFG1 */
unsigned long vaddr;
int i;
struct gfar_private *priv = netdev_priv(dev);
- struct gfar *regs = priv->regs;
+ struct gfar __iomem *regs = priv->regs;
int err = 0;
u32 rctrl = 0;
u32 attrs = 0;
static void adjust_link(struct net_device *dev)
{
struct gfar_private *priv = netdev_priv(dev);
- struct gfar *regs = priv->regs;
+ struct gfar __iomem *regs = priv->regs;
unsigned long flags;
struct phy_device *phydev = priv->phydev;
int new_state = 0;
{
struct dev_mc_list *mc_ptr;
struct gfar_private *priv = netdev_priv(dev);
- struct gfar *regs = priv->regs;
+ struct gfar __iomem *regs = priv->regs;
u32 tempval;
if(dev->flags & IFF_PROMISC) {
int idx;
char tmpbuf[MAC_ADDR_LEN];
u32 tempval;
- u32 *macptr = &priv->regs->macstnaddr1;
+ u32 __iomem *macptr = &priv->regs->macstnaddr1;
macptr += num*2;
struct rxbd8 *cur_rx; /* Next free rx ring entry */
struct txbd8 *cur_tx; /* Next free ring entry */
struct txbd8 *dirty_tx; /* The Ring entry to be freed. */
- struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */
- u32 *hash_regs[16];
+ struct gfar __iomem *regs; /* Pointer to the GFAR memory mapped Registers */
+ u32 __iomem *hash_regs[16];
int hash_width;
struct net_device_stats stats; /* linux network statistics */
struct gfar_extra_stats extra_stats;
uint32_t msg_enable;
};
-static inline u32 gfar_read(volatile unsigned *addr)
+static inline u32 gfar_read(volatile unsigned __iomem *addr)
{
u32 val;
val = in_be32(addr);
return val;
}
-static inline void gfar_write(volatile unsigned *addr, u32 val)
+static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
{
out_be32(addr, val);
}
u64 *extra = (u64 *) & priv->extra_stats;
if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
- u32 *rmon = (u32 *) & priv->regs->rmon;
+ u32 __iomem *rmon = (u32 __iomem *) & priv->regs->rmon;
struct gfar_stats *stats = (struct gfar_stats *) buf;
for (i = 0; i < GFAR_RMON_LEN; i++)
- stats->rmon[i] = (u64) (rmon[i]);
+ stats->rmon[i] = (u64) gfar_read(&rmon[i]);
for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++)
stats->extra[i] = extra[i];
{
int i;
struct gfar_private *priv = netdev_priv(dev);
- u32 *theregs = (u32 *) priv->regs;
+ u32 __iomem *theregs = (u32 __iomem *) priv->regs;
u32 *buf = (u32 *) regbuf;
for (i = 0; i < sizeof (struct gfar) / sizeof (u32); i++)
- buf[i] = theregs[i];
+ buf[i] = gfar_read(&theregs[i]);
}
/* Convert microseconds to ethernet clock ticks, which changes
* All PHY configuration is done through the TSEC1 MIIM regs */
int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
{
- struct gfar_mii *regs = bus->priv;
+ struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
/* Set the PHY address and the register address we want to write */
gfar_write(®s->miimadd, (mii_id << 8) | regnum);
* configuration has to be done through the TSEC1 MIIM regs */
int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
- struct gfar_mii *regs = bus->priv;
+ struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
u16 value;
/* Set the PHY address and the register address we want to read */
/* Reset the MIIM registers, and wait for the bus to free */
int gfar_mdio_reset(struct mii_bus *bus)
{
- struct gfar_mii *regs = bus->priv;
+ struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
unsigned int timeout = PHY_INIT_TIMEOUT;
spin_lock_bh(&bus->mdio_lock);
{
struct platform_device *pdev = to_platform_device(dev);
struct gianfar_mdio_data *pdata;
- struct gfar_mii *regs;
+ struct gfar_mii __iomem *regs;
struct mii_bus *new_bus;
struct resource *r;
int err = 0;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
/* Set the PHY base address */
- regs = (struct gfar_mii *) ioremap(r->start,
- sizeof (struct gfar_mii));
+ regs = ioremap(r->start, sizeof (struct gfar_mii));
if (NULL == regs) {
err = -ENOMEM;
goto reg_map_fail;
}
- new_bus->priv = regs;
+ new_bus->priv = (void __force *)regs;
new_bus->irq = pdata->irq;
return 0;
bus_register_fail:
- iounmap((void *) regs);
+ iounmap(regs);
reg_map_fail:
kfree(new_bus);
dev_set_drvdata(dev, NULL);
- iounmap((void *) (&bus->priv));
+ iounmap((void __iomem *)bus->priv);
bus->priv = NULL;
kfree(bus);
int i;
RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
- udelay(1000);
- for (i = 2000; i > 0; i--) {
+ for (i = 20; i > 0; i--) {
/* Check if the RTL8169 has completed writing to the specified MII register */
if (!(RTL_R32(PHYAR) & 0x80000000))
break;
- udelay(100);
+ udelay(25);
}
}
int i, value = -1;
RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
- udelay(1000);
- for (i = 2000; i > 0; i--) {
+ for (i = 20; i > 0; i--) {
/* Check if the RTL8169 has completed retrieving data from the specified MII register */
if (RTL_R32(PHYAR) & 0x80000000) {
value = (int) (RTL_R32(PHYAR) & 0xFFFF);
break;
}
- udelay(100);
+ udelay(25);
}
return value;
}
if (duplex == DUPLEX_HALF)
auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
+
+ if (duplex == DUPLEX_FULL)
+ auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
}
tp->phy_auto_nego_reg = auto_nego;
rxcfg=0x34, //Receive Configuration Register
flctrl=0x38, //Flow Control Register
rxlen=0x3c, //Receive Packet Length Register
- cfgpmcsr=0x44, //Configuration Power Management Control/Status Register
rfcr=0x48, //Receive Filter Control Register
rfdr=0x4C, //Receive Filter Data Register
pmctrl=0xB0, //Power Management Control Register
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-/*
- * TOTEST
- * - speed setting
- * - suspend/resume
- */
-
#include <linux/config.h>
#include <linux/crc32.h>
#include <linux/kernel.h>
#include "sky2.h"
#define DRV_NAME "sky2"
-#define DRV_VERSION "0.13"
+#define DRV_VERSION "0.15"
#define PFX DRV_NAME " "
/*
module_param(copybreak, int, 0);
MODULE_PARM_DESC(copybreak, "Receive copy threshold");
+static int disable_msi = 0;
+module_param(disable_msi, int, 0);
+MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
+
static const struct pci_device_id sky2_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
- vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
+ vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
(power_control & PCI_PM_CAP_PME_D3cold);
pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
u16 hwidx;
u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
+ sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
+
hwidx = sky2_read16(hw, STAT_PUT_IDX);
BUG_ON(hwidx >= STATUS_RING_SIZE);
rmb();
}
exit_loop:
- sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
-
sky2_tx_check(hw, 0, tx_done[0]);
sky2_tx_check(hw, 1, tx_done[1]);
- if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
+ if (likely(work_done < to_do)) {
/* need to restart TX timer */
if (is_ec_a1(hw)) {
sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
static int sky2_reset(struct sky2_hw *hw)
{
- u32 ctst;
u16 status;
u8 t8, pmd_type;
- int i;
-
- ctst = sky2_read32(hw, B0_CTST);
+ int i, err;
sky2_write8(hw, B0_CTST, CS_RST_CLR);
+
hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
return -EOPNOTSUPP;
}
- /* ring for status responses */
- hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
- &hw->st_dma);
- if (!hw->st_le)
- return -ENOMEM;
-
/* disable ASF */
if (hw->chip_id <= CHIP_ID_YUKON_EC) {
sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
sky2_write8(hw, B0_CTST, CS_RST_CLR);
/* clear PCI errors, if any */
- pci_read_config_word(hw->pdev, PCI_STATUS, &status);
+ err = pci_read_config_word(hw->pdev, PCI_STATUS, &status);
+ if (err)
+ goto pci_err;
+
sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
- pci_write_config_word(hw->pdev, PCI_STATUS,
- status | PCI_STATUS_ERROR_BITS);
+ err = pci_write_config_word(hw->pdev, PCI_STATUS,
+ status | PCI_STATUS_ERROR_BITS);
+ if (err)
+ goto pci_err;
sky2_write8(hw, B0_CTST, CS_MRST_CLR);
/* clear any PEX errors */
- if (is_pciex(hw)) {
- u16 lstat;
- pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
- 0xffffffffUL);
- pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
+ if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
+ err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
+ 0xffffffffUL);
+ if (err)
+ goto pci_err;
}
pmd_type = sky2_read8(hw, B2_PMD_TYP);
sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
return 0;
+
+pci_err:
+ /* This is to catch a BIOS bug workaround where
+ * mmconfig table doesn't have other buses.
+ */
+ printk(KERN_ERR PFX "%s: can't access PCI config space\n",
+ pci_name(hw->pdev));
+ return err;
}
static u32 sky2_supported_modes(const struct sky2_hw *hw)
static int sky2_set_mac_address(struct net_device *dev, void *p)
{
struct sky2_port *sky2 = netdev_priv(dev);
- struct sockaddr *addr = p;
+ struct sky2_hw *hw = sky2->hw;
+ unsigned port = sky2->port;
+ const struct sockaddr *addr = p;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
- memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
+ memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
dev->dev_addr, ETH_ALEN);
- memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
+ memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
dev->dev_addr, ETH_ALEN);
- if (netif_running(dev))
- sky2_phy_reinit(sky2);
+ /* virtual address for data */
+ gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
+
+ /* physical address: used for pause frames */
+ gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
return 0;
}
if (ecmd->rx_coalesce_usecs_irq == 0)
sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
else {
- sky2_write32(hw, STAT_TX_TIMER_INI,
+ sky2_write32(hw, STAT_ISR_TIMER_INI,
sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
}
dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
}
+/* Handle software interrupt used during MSI test */
+static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ struct sky2_hw *hw = dev_id;
+ u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
+
+ if (status == 0)
+ return IRQ_NONE;
+
+ if (status & Y2_IS_IRQ_SW) {
+ sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
+ hw->msi = 1;
+ }
+ sky2_write32(hw, B0_Y2_SP_ICR, 2);
+
+ sky2_read32(hw, B0_IMSK);
+ return IRQ_HANDLED;
+}
+
+/* Test interrupt path by forcing a a software IRQ */
+static int __devinit sky2_test_msi(struct sky2_hw *hw)
+{
+ struct pci_dev *pdev = hw->pdev;
+ int i, err;
+
+ sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
+
+ err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
+ if (err) {
+ printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
+ pci_name(pdev), pdev->irq);
+ return err;
+ }
+
+ sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
+ wmb();
+
+ for (i = 0; i < 10; i++) {
+ barrier();
+ if (hw->msi)
+ goto found;
+ mdelay(1);
+ }
+
+ err = -EOPNOTSUPP;
+ sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
+ found:
+ sky2_write32(hw, B0_IMSK, 0);
+
+ free_irq(pdev->irq, hw);
+
+ return err;
+}
+
static int __devinit sky2_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
}
hw->pm_cap = pm_cap;
+ /* ring for status responses */
+ hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
+ &hw->st_dma);
+ if (!hw->st_le)
+ goto err_out_iounmap;
+
err = sky2_reset(hw);
if (err)
goto err_out_iounmap;
}
}
- err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
+ if (!disable_msi && pci_enable_msi(pdev) == 0) {
+ err = sky2_test_msi(hw);
+ if (err == -EOPNOTSUPP) {
+ /* MSI test failed, go back to INTx mode */
+ printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
+ "switching to INTx mode. Please report this failure to "
+ "the PCI maintainer and include system chipset information.\n",
+ pci_name(pdev));
+ pci_disable_msi(pdev);
+ }
+ else if (err)
+ goto err_out_unregister;
+ }
+
+ err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
+ DRV_NAME, hw);
if (err) {
printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
pci_name(pdev), pdev->irq);
return 0;
err_out_unregister:
+ if (hw->msi)
+ pci_disable_msi(pdev);
if (dev1) {
unregister_netdev(dev1);
free_netdev(dev1);
sky2_read8(hw, B0_CTST);
free_irq(pdev->irq, hw);
+ if (hw->msi)
+ pci_disable_msi(pdev);
pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
pci_release_regions(pdev);
pci_disable_device(pdev);
static int sky2_resume(struct pci_dev *pdev)
{
struct sky2_hw *hw = pci_get_drvdata(pdev);
- int i;
+ int i, err;
pci_restore_state(pdev);
pci_enable_wake(pdev, PCI_D0, 0);
- sky2_set_power_state(hw, PCI_D0);
+ err = sky2_set_power_state(hw, PCI_D0);
+ if (err)
+ goto out;
- sky2_reset(hw);
+ err = sky2_reset(hw);
+ if (err)
+ goto out;
for (i = 0; i < 2; i++) {
struct net_device *dev = hw->dev[i];
- if (dev) {
- if (netif_running(dev)) {
- netif_device_attach(dev);
- if (sky2_up(dev))
- dev_close(dev);
+ if (dev && netif_running(dev)) {
+ netif_device_attach(dev);
+ err = sky2_up(dev);
+ if (err) {
+ printk(KERN_ERR PFX "%s: could not up: %d\n",
+ dev->name, err);
+ dev_close(dev);
+ break;
}
}
}
- return 0;
+out:
+ return err;
}
#endif
struct net_device *dev[2];
int pm_cap;
+ int msi;
u8 chip_id;
u8 chip_rev;
u8 copper;
return readb(hw->regs + reg);
}
-/* This should probably go away, bus based tweeks suck */
-static inline int is_pciex(const struct sky2_hw *hw)
-{
- u32 status;
- pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
- return (status & PCI_OS_PCI_X) == 0;
-}
-
static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
{
writel(val, hw->regs + reg);
/* For module input parameter */
static int debug;
static u32 cr6set;
-static unsigned char mode = 8;
+static int mode = 8;
/* function declaration ------------------------------------- */
static int uli526x_open(struct net_device *);
(++i%TX_RING_SIZE)*sizeof(*tx_fd));
} while (i < TX_RING_SIZE);
- if (dscc4_init_dummy_skb(dpriv) < 0)
+ if (!dscc4_init_dummy_skb(dpriv))
goto err_free_dma_tx;
memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
}
/*
- * flz - find last zero in word.
+ * fls - find last bit set.
* @word: The word to search
*
- * Returns 0..SZLONG-1
- * Undefined if no zero exists, so code should check against ~0UL first.
+ * Returns 1..SZLONG
+ * Returns 0 if no bit exists
*/
-static inline unsigned long flz(unsigned long word)
+static inline unsigned long fls(unsigned long word)
{
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
- return __ilog2(~word);
-#else
#ifdef CONFIG_32BIT
- int r = 31, s;
- word = ~word;
+#ifdef CONFIG_CPU_MIPS32
+ __asm__ ("clz %0, %1" : "=r" (word) : "r" (word));
+
+ return 32 - word;
+#else
+ {
+ int r = 32, s;
+
+ if (word == 0)
+ return 0;
+
s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s;
s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s;
s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s;
s = 1; if ((word & 0x80000000)) s = 0; r -= s;
return r;
+ }
#endif
+#endif /* CONFIG_32BIT */
+
#ifdef CONFIG_64BIT
- int r = 63, s;
- word = ~word;
+#ifdef CONFIG_CPU_MIPS64
+
+ __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word));
+
+ return 64 - word;
+#else
+ {
+ int r = 64, s;
+
+ if (word == 0)
+ return 0;
+
s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s;
s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s;
s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s;
s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s;
return r;
+ }
#endif
-#endif
+#endif /* CONFIG_64BIT */
}
-/*
- * fls - find last bit set.
- * @word: The word to search
- *
- * Returns 1..SZLONG
- * Returns 0 if no bit exists
- */
-static inline unsigned long fls(unsigned long word)
-{
- if (word == 0)
- return 0;
-
- return flz(~word) + 1;
-}
#define fls64(x) generic_fls64(x)
/*
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
+#include <linux/config.h>
+#include <linux/compiler.h>
#include <asm/types.h>
#ifdef __GNUC__
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+ __asm__(
+ " wsbh %0, %1 \n"
+ : "=r" (x)
+ : "r" (x));
+
+ return x;
+}
+#define __arch__swab16(x) ___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+ __asm__(
+ " wsbh %0, %1 \n"
+ " rotr %0, %0, 16 \n"
+ : "=r" (x)
+ : "r" (x));
+
+ return x;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
extern void (*flush_icache_page)(struct vm_area_struct *vma,
struct page *page);
-extern void (*flush_icache_range)(unsigned long __user start,
- unsigned long __user end);
+extern void (*flush_icache_range)(unsigned long start, unsigned long end);
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
__asm__(
" .macro _ssnop \n\t"
- " sll $0, $2, 1 \n\t"
+ " sll $0, $0, 1 \n\t"
" .endm \n\t"
" \n\t"
" .macro _ehb \n\t"
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
+/*
+ * For TX49, operating only IE bit is not enough.
+ *
+ * If mfc0 $12 follows store and the mfc0 is last instruction of a
+ * page and fetching the next instruction causes TLB miss, the result
+ * of the mfc0 might wrongly contain EXL bit.
+ *
+ * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
+ *
+ * Workaround: mask EXL bit of the result or place a nop before mfc0.
+ */
__asm__ (
" .macro local_irq_disable\n"
" .set push \n"
" di \n"
#else
" mfc0 $1,$12 \n"
- " ori $1,1 \n"
- " xori $1,1 \n"
+ " ori $1,0x1f \n"
+ " xori $1,0x1f \n"
" .set noreorder \n"
" mtc0 $1,$12 \n"
#endif
" andi \\result, 1 \n"
#else
" mfc0 \\result, $12 \n"
- " ori $1, \\result, 1 \n"
- " xori $1, 1 \n"
+ " ori $1, \\result, 0x1f \n"
+ " xori $1, 0x1f \n"
" .set noreorder \n"
" mtc0 $1, $12 \n"
#endif
__asm__ (
" .macro local_irq_restore flags \n"
+ " .set push \n"
" .set noreorder \n"
" .set noat \n"
#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
#else
" mfc0 $1, $12 \n"
" andi \\flags, 1 \n"
- " ori $1, 1 \n"
- " xori $1, 1 \n"
+ " ori $1, 0x1f \n"
+ " xori $1, 0x1f \n"
" or \\flags, $1 \n"
" mtc0 \\flags, $12 \n"
#endif
" irq_disable_hazard \n"
- " .set at \n"
- " .set reorder \n"
+ " .set pop \n"
" .endm \n");
#define local_irq_restore(flags) \
/* UARTS 0-3 */
#define UART_BASE UART0_ADDR
+#ifdef CONFIG_SOC_AU1200
+#define UART_DEBUG_BASE UART1_ADDR
+#else
#define UART_DEBUG_BASE UART3_ADDR
+#endif
#define UART_RX 0 /* Receive buffer */
#define UART_TX 4 /* Transmit buffer */
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/config.h>
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 1
+#define cpu_has_32fpr 1
+#define cpu_has_counter 1
+#define cpu_has_watch 0
+#define cpu_has_divec 1
+#define cpu_has_vce 0
+#define cpu_has_cache_cdex_p 0
+#define cpu_has_cache_cdex_s 0
+#define cpu_has_prefetch 0
+#define cpu_has_mcheck 0
+#define cpu_has_ejtag 0
+
+#define cpu_has_subset_pcaches 0
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+#define cpu_scache_line_size() 0
+
+#ifdef CONFIG_64BIT
+#define cpu_has_llsc 0
+#else
+#define cpu_has_llsc 1
+#endif
+
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_ic_fills_f_dc 0
+#define cpu_icache_snoops_remote_store 0
+#define cpu_has_dsp 0
+
+#define cpu_has_mips32r1 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
* so, for 64bit IP32 kernel we just don't use ll/sc.
* This does not affect luserland.
*/
-#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT)
+#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
#define cpu_has_llsc 0
#else
#define cpu_has_llsc 1
: "r" (base), \
"i" (op));
-static inline void blast_dcache16(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.dcache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
- unsigned long ws_end = current_cpu_data.dcache.ways <<
- current_cpu_data.dcache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
-}
-
-static inline void blast_dcache16_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
-
- do {
- cache16_unroll32(start,Hit_Writeback_Inv_D);
- start += 0x200;
- } while (start < end);
-}
-
-static inline void blast_dcache16_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
- unsigned long ws_end = current_cpu_data.dcache.ways <<
- current_cpu_data.dcache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
-}
-
-static inline void blast_icache16(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.icache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Invalidate_I);
-}
-
-static inline void blast_icache16_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
-
- do {
- cache16_unroll32(start,Hit_Invalidate_I);
- start += 0x200;
- } while (start < end);
-}
-
-static inline void blast_icache16_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Invalidate_I);
-}
-
-static inline void blast_scache16(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.scache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
-static inline void blast_scache16_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = page + PAGE_SIZE;
-
- do {
- cache16_unroll32(start,Hit_Writeback_Inv_SD);
- start += 0x200;
- } while (start < end);
-}
-
-static inline void blast_scache16_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
#define cache32_unroll32(base,op) \
__asm__ __volatile__( \
" .set push \n" \
: "r" (base), \
"i" (op));
-static inline void blast_dcache32(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.dcache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
- unsigned long ws_end = current_cpu_data.dcache.ways <<
- current_cpu_data.dcache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
-}
-
-static inline void blast_dcache32_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
-
- do {
- cache32_unroll32(start,Hit_Writeback_Inv_D);
- start += 0x400;
- } while (start < end);
-}
-
-static inline void blast_dcache32_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
- unsigned long ws_end = current_cpu_data.dcache.ways <<
- current_cpu_data.dcache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
-}
-
-static inline void blast_icache32(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.icache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Invalidate_I);
-}
-
-static inline void blast_icache32_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
-
- do {
- cache32_unroll32(start,Hit_Invalidate_I);
- start += 0x400;
- } while (start < end);
-}
-
-static inline void blast_icache32_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Invalidate_I);
-}
-
-static inline void blast_scache32(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.scache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
-static inline void blast_scache32_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = page + PAGE_SIZE;
-
- do {
- cache32_unroll32(start,Hit_Writeback_Inv_SD);
- start += 0x400;
- } while (start < end);
-}
-
-static inline void blast_scache32_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
#define cache64_unroll32(base,op) \
__asm__ __volatile__( \
" .set push \n" \
: "r" (base), \
"i" (op));
-static inline void blast_icache64(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.icache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x800)
- cache64_unroll32(addr|ws,Index_Invalidate_I);
-}
-
-static inline void blast_icache64_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
-
- do {
- cache64_unroll32(start,Hit_Invalidate_I);
- start += 0x800;
- } while (start < end);
-}
-
-static inline void blast_icache64_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x800)
- cache64_unroll32(addr|ws,Index_Invalidate_I);
-}
-
-static inline void blast_scache64(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.scache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x800)
- cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
-static inline void blast_scache64_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = page + PAGE_SIZE;
-
- do {
- cache64_unroll32(start,Hit_Writeback_Inv_SD);
- start += 0x800;
- } while (start < end);
-}
-
-static inline void blast_scache64_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x800)
- cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
#define cache128_unroll32(base,op) \
__asm__ __volatile__( \
" .set push \n" \
: "r" (base), \
"i" (op));
-static inline void blast_scache128(void)
-{
- unsigned long start = INDEX_BASE;
- unsigned long end = start + current_cpu_data.scache.waysize;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x1000)
- cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
-
-static inline void blast_scache128_page(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = page + PAGE_SIZE;
-
- do {
- cache128_unroll32(start,Hit_Writeback_Inv_SD);
- start += 0x1000;
- } while (start < end);
-}
-
-static inline void blast_scache128_page_indexed(unsigned long page)
-{
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
- unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
- unsigned long ws_end = current_cpu_data.scache.ways <<
- current_cpu_data.scache.waybit;
- unsigned long ws, addr;
-
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x1000)
- cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
-}
+/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
+static inline void blast_##pfx##cache##lsize(void) \
+{ \
+ unsigned long start = INDEX_BASE; \
+ unsigned long end = start + current_cpu_data.desc.waysize; \
+ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
+ unsigned long ws_end = current_cpu_data.desc.ways << \
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws,indexop); \
+} \
+ \
+static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
+{ \
+ unsigned long start = page; \
+ unsigned long end = page + PAGE_SIZE; \
+ \
+ do { \
+ cache##lsize##_unroll32(start,hitop); \
+ start += lsize * 32; \
+ } while (start < end); \
+} \
+ \
+static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
+{ \
+ unsigned long start = page; \
+ unsigned long end = start + PAGE_SIZE; \
+ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
+ unsigned long ws_end = current_cpu_data.desc.ways << \
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws,indexop); \
+}
+
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
#endif /* _ASM_R4KCACHE_H */
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#ifndef _ASM_REBOOT_H
extern void (*_machine_restart)(char *command);
extern void (*_machine_halt)(void);
-extern void (*_machine_power_off)(void);
#endif /* _ASM_REBOOT_H */
#define __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-#ifdef CONFIG_32BIT
-#define __HAVE_ARCH_MEMSCAN
-static __inline__ void *memscan(void *__addr, int __c, size_t __size)
-{
- char *__end = (char *)__addr + __size;
- unsigned char __uc = (unsigned char) __c;
-
- __asm__(".set\tpush\n\t"
- ".set\tnoat\n\t"
- ".set\treorder\n\t"
- "1:\tbeq\t%0,%1,2f\n\t"
- "addiu\t%0,1\n\t"
- "lbu\t$1,-1(%0)\n\t"
- "bne\t$1,%z4,1b\n"
- "2:\t.set\tpop"
- : "=r" (__addr), "=r" (__end)
- : "0" (__addr), "1" (__end), "Jr" (__uc));
-
- return __addr;
-}
-#endif /* CONFIG_32BIT */
-
#endif /* _ASM_STRING_H */
* Author: MontaVista Software, Inc.
* source@mvista.com
*
- * Copyright 2001-2002 MontaVista Software Inc.
+ * Copyright 2001-2006 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
#include <asm/tx4927/tx4927_mips.h>
/*
- This register naming came from the intergrate cpu/controoler name TX4927
+ This register naming came from the integrated CPU/controller name TX4927
followed by the device name from table 4.2.2 on page 4-3 and then followed
by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul
- used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001".
+ used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001".
*/
#define TX4927_SIO_0_BASE
/* TX4927 Timer 0 (32-bit registers) */
#define TX4927_TMR0_BASE 0xf000
-#define TX4927_TMR0_TMTCR0 0xf004
-#define TX4927_TMR0_TMTISR0 0xf008
+#define TX4927_TMR0_TMTCR0 0xf000
+#define TX4927_TMR0_TMTISR0 0xf004
#define TX4927_TMR0_TMCPRA0 0xf008
#define TX4927_TMR0_TMCPRB0 0xf00c
#define TX4927_TMR0_TMITMR0 0xf010
/* TX4927 Timer 1 (32-bit registers) */
#define TX4927_TMR1_BASE 0xf100
-#define TX4927_TMR1_TMTCR1 0xf104
-#define TX4927_TMR1_TMTISR1 0xf108
+#define TX4927_TMR1_TMTCR1 0xf100
+#define TX4927_TMR1_TMTISR1 0xf104
#define TX4927_TMR1_TMCPRA1 0xf108
#define TX4927_TMR1_TMCPRB1 0xf10c
#define TX4927_TMR1_TMITMR1 0xf110
/* TX4927 Timer 2 (32-bit registers) */
#define TX4927_TMR2_BASE 0xf200
-#define TX4927_TMR2_TMTCR2 0xf104
-#define TX4927_TMR2_TMTISR2 0xf208
+#define TX4927_TMR2_TMTCR2 0xf200
+#define TX4927_TMR2_TMTISR2 0xf204
#define TX4927_TMR2_TMCPRA2 0xf208
-#define TX4927_TMR2_TMCPRB2 0xf20c
#define TX4927_TMR2_TMITMR2 0xf210
#define TX4927_TMR2_TMCCDR2 0xf220
-#define TX4927_TMR2_TMPGMR2 0xf230
+#define TX4927_TMR2_TMWTMR2 0xf240
#define TX4927_TMR2_TMTRR2 0xf2f0
#define TX4927_TMR2_LIMIT 0xf2ff
#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
+#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
+#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
+#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
+#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
+#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
+#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
+#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
+#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
+#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
+
/* PCFG : Pin Configuration */
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
* Yuck. We need two variants, one for 64bit operation and one
* for 32 bit mode and old iron.
*/
-#ifdef __mips64
-#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr)
-#else
-#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr)
+#ifdef CONFIG_32BIT
+#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr)
#endif
-#define __get_user_nocheck(x,ptr,size) \
-({ \
- __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \
- long __gu_err = 0; \
- \
+extern void __get_user_unknown(void);
+
+#define __get_user_common(val, size, ptr) \
+do { \
switch (size) { \
- case 1: __get_user_asm("lb", ptr); break; \
- case 2: __get_user_asm("lh", ptr); break; \
- case 4: __get_user_asm("lw", ptr); break; \
- case 8: __GET_USER_DW(ptr); break; \
+ case 1: __get_user_asm(val, "lb", ptr); break; \
+ case 2: __get_user_asm(val, "lh", ptr); break; \
+ case 4: __get_user_asm(val, "lw", ptr); break; \
+ case 8: __GET_USER_DW(val, ptr); break; \
default: __get_user_unknown(); break; \
} \
- (x) = (__typeof__(*(ptr))) __gu_val; \
+} while (0)
+
+#define __get_user_nocheck(x,ptr,size) \
+({ \
+ long __gu_err; \
+ \
+ __get_user_common((x), size, ptr); \
__gu_err; \
})
#define __get_user_check(x,ptr,size) \
({ \
- const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \
- __typeof__(*(ptr)) __gu_val = 0; \
long __gu_err = -EFAULT; \
+ const void __user * __gu_ptr = (ptr); \
+ \
+ if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \
+ __get_user_common((x), size, __gu_ptr); \
\
- if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \
- switch (size) { \
- case 1: __get_user_asm("lb", __gu_addr); break; \
- case 2: __get_user_asm("lh", __gu_addr); break; \
- case 4: __get_user_asm("lw", __gu_addr); break; \
- case 8: __GET_USER_DW(__gu_addr); break; \
- default: __get_user_unknown(); break; \
- } \
- } \
- (x) = (__typeof__(*(ptr))) __gu_val; \
__gu_err; \
})
-#define __get_user_asm(insn, addr) \
+#define __get_user_asm(val, insn, addr) \
{ \
+ long __gu_tmp; \
+ \
__asm__ __volatile__( \
"1: " insn " %1, %3 \n" \
"2: \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 3b \n" \
" .previous \n" \
- : "=r" (__gu_err), "=r" (__gu_val) \
+ : "=r" (__gu_err), "=r" (__gu_tmp) \
: "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \
+ \
+ (val) = (__typeof__(val)) __gu_tmp; \
}
/*
* Get a long long 64 using 32 bit registers.
*/
-#define __get_user_asm_ll32(addr) \
+#define __get_user_asm_ll32(val, addr) \
{ \
__asm__ __volatile__( \
"1: lw %1, (%3) \n" \
" " __UA_ADDR " 1b, 4b \n" \
" " __UA_ADDR " 2b, 4b \n" \
" .previous \n" \
- : "=r" (__gu_err), "=&r" (__gu_val) \
+ : "=r" (__gu_err), "=&r" (val) \
: "0" (0), "r" (addr), "i" (-EFAULT)); \
}
-extern void __get_user_unknown(void);
-
/*
* Yuck. We need two variants, one for 64bit operation and one
* for 32 bit mode and old iron.
*/
-#ifdef __mips64
-#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
-#else
+#ifdef CONFIG_32BIT
#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
#endif
+#ifdef CONFIG_64BIT
+#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
+#endif
#define __put_user_nocheck(x,ptr,size) \
({ \
#
check-lxdialog := $(srctree)/$(src)/check-lxdialog.sh
-HOST_EXTRACFLAGS:= $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags)
-HOST_LOADLIBES := $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
+
+# Use reursively expanded variables so we do not call gcc unless
+# we really need to do so. (Do not call gcc as part of make mrproper)
+HOST_EXTRACFLAGS = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags)
+HOST_LOADLIBES = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
HOST_EXTRACFLAGS += -DLOCALE
# What library to link
ldflags()
{
- echo "main() {}" | $cc -lncursesw -xc - -o /dev/null 2> /dev/null
+ $cc -print-file-name=libncursesw.so | grep -q /
if [ $? -eq 0 ]; then
echo '-lncursesw'
exit
fi
- echo "main() {}" | $cc -lncurses -xc - -o /dev/null 2> /dev/null
+ $cc -print-file-name=libncurses.so | grep -q /
if [ $? -eq 0 ]; then
echo '-lncurses'
exit
fi
- echo "main() {}" | $cc -lcurses -xc - -o /dev/null 2> /dev/null
+ $cc -print-file-name=libcurses.so | grep -q /
if [ $? -eq 0 ]; then
echo '-lcurses'
exit
fi
}
-compiler=""
+# Temp file, try to clean up after us
+tmp=.lxdialog.tmp
+trap "rm -f $tmp" 0 1 2 3 15
+
# Check if we can link to ncurses
check() {
- echo "main() {}" | $cc -xc - -o /dev/null 2> /dev/null
+ echo "main() {}" | $cc -xc - -o $tmp 2> /dev/null
if [ $? != 0 ]; then
echo " *** Unable to find the ncurses libraries." 1>&2
echo " *** make menuconfig require the ncurses libraries" 1>&2
exit 1
fi
+cc=""
case "$1" in
"-check")
shift
git.openpandora.org / pandora-kernel.git / commitdiff