locking, ARM: Annotate low level hw locks as raw

Annotate the low level hardware locks which must not be preempted.

In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 3227ca9..6fba8bd 100644 (file)
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -33,7 +33,7 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 
-static DEFINE_SPINLOCK(irq_controller_lock);
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
 /* Address of GIC 0 CPU interface */
 void __iomem *gic_cpu_base_addr __read_mostly;
@@ -82,30 +82,30 @@ static void gic_mask_irq(struct irq_data *d)
 {
        u32 mask = 1 << (d->irq % 32);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
        if (gic_arch_extn.irq_mask)
                gic_arch_extn.irq_mask(d);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
        u32 mask = 1 << (d->irq % 32);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        if (gic_arch_extn.irq_unmask)
                gic_arch_extn.irq_unmask(d);
        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 }
 
 static void gic_eoi_irq(struct irq_data *d)
 {
        if (gic_arch_extn.irq_eoi) {
-               spin_lock(&irq_controller_lock);
+               raw_spin_lock(&irq_controller_lock);
                gic_arch_extn.irq_eoi(d);
-               spin_unlock(&irq_controller_lock);
+               raw_spin_unlock(&irq_controller_lock);
        }
 
        writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
@@ -129,7 +129,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
        if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
                return -EINVAL;
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
 
        if (gic_arch_extn.irq_set_type)
                gic_arch_extn.irq_set_type(d, type);
@@ -154,7 +154,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
        if (enabled)
                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
 
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 
        return 0;
 }
@@ -182,10 +182,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
        mask = 0xff << shift;
        bit = 1 << (cpu + shift);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        val = readl_relaxed(reg) & ~mask;
        writel_relaxed(val | bit, reg);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 
        return IRQ_SET_MASK_OK;
 }
@@ -215,9 +215,9 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 
        chained_irq_enter(chip, desc);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 
        gic_irq = (status & 0x3ff);
        if (gic_irq == 1023)

diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 628670e..69a5b0b 100644 (file)
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -34,18 +34,18 @@
 #define DMA_MODE_CASCADE 0xc0
 #define DMA_AUTOINIT    0x10
 
-extern spinlock_t  dma_spin_lock;
+extern raw_spinlock_t  dma_spin_lock;
 
 static inline unsigned long claim_dma_lock(void)
 {
        unsigned long flags;
-       spin_lock_irqsave(&dma_spin_lock, flags);
+       raw_spin_lock_irqsave(&dma_spin_lock, flags);
        return flags;
 }
 
 static inline void release_dma_lock(unsigned long flags)
 {
-       spin_unlock_irqrestore(&dma_spin_lock, flags);
+       raw_spin_unlock_irqrestore(&dma_spin_lock, flags);
 }
 
 /* Clear the 'DMA Pointer Flip Flop'.

diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index b4ffe9d..1496565 100644 (file)
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -6,7 +6,7 @@
 typedef struct {
 #ifdef CONFIG_CPU_HAS_ASID
        unsigned int id;
-       spinlock_t id_lock;
+       raw_spinlock_t id_lock;
 #endif
        unsigned int kvm_seq;
 } mm_context_t;
@@ -16,7 +16,7 @@ typedef struct {
 
 /* init_mm.context.id_lock should be initialized. */
 #define INIT_MM_CONTEXT(name)                                                 \
-       .context.id_lock    = __SPIN_LOCK_UNLOCKED(name.context.id_lock),
+       .context.id_lock    = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
 #else
 #define ASID(mm)       (0)
 #endif

diff --git a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c
index 2c4a185..7b829d9 100644 (file)
--- a/arch/arm/kernel/dma.c
+++ b/arch/arm/kernel/dma.c
@@ -23,7 +23,7 @@
 
 #include <asm/mach/dma.h>
 
-DEFINE_SPINLOCK(dma_spin_lock);
+DEFINE_RAW_SPINLOCK(dma_spin_lock);
 EXPORT_SYMBOL(dma_spin_lock);
 
 static dma_t *dma_chan[MAX_DMA_CHANNELS];

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d88ff02..4e76e0c 100644 (file)
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -538,7 +538,7 @@ static void percpu_timer_stop(void)
 }
 #endif
 
-static DEFINE_SPINLOCK(stop_lock);
+static DEFINE_RAW_SPINLOCK(stop_lock);
 
 /*
  * ipi_cpu_stop - handle IPI from smp_send_stop()
@@ -547,10 +547,10 @@ static void ipi_cpu_stop(unsigned int cpu)
 {
        if (system_state == SYSTEM_BOOTING ||
            system_state == SYSTEM_RUNNING) {
-               spin_lock(&stop_lock);
+               raw_spin_lock(&stop_lock);
                printk(KERN_CRIT "CPU%u: stopping\n", cpu);
                dump_stack();
-               spin_unlock(&stop_lock);
+               raw_spin_unlock(&stop_lock);
        }
 
        set_cpu_online(cpu, false);

diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index bc9f9da..81cc05a 100644 (file)
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -255,7 +255,7 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt
        return ret;
 }
 
-static DEFINE_SPINLOCK(die_lock);
+static DEFINE_RAW_SPINLOCK(die_lock);
 
 /*
  * This function is protected against re-entrancy.
@@ -267,7 +267,7 @@ void die(const char *str, struct pt_regs *regs, int err)
 
        oops_enter();
 
-       spin_lock_irq(&die_lock);
+       raw_spin_lock_irq(&die_lock);
        console_verbose();
        bust_spinlocks(1);
        ret = __die(str, err, thread, regs);
@@ -277,7 +277,7 @@ void die(const char *str, struct pt_regs *regs, int err)
 
        bust_spinlocks(0);
        add_taint(TAINT_DIE);
-       spin_unlock_irq(&die_lock);
+       raw_spin_unlock_irq(&die_lock);
        oops_exit();
 
        if (in_interrupt())
@@ -302,24 +302,24 @@ void arm_notify_die(const char *str, struct pt_regs *regs,
 }
 
 static LIST_HEAD(undef_hook);
-static DEFINE_SPINLOCK(undef_lock);
+static DEFINE_RAW_SPINLOCK(undef_lock);
 
 void register_undef_hook(struct undef_hook *hook)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&undef_lock, flags);
+       raw_spin_lock_irqsave(&undef_lock, flags);
        list_add(&hook->node, &undef_hook);
-       spin_unlock_irqrestore(&undef_lock, flags);
+       raw_spin_unlock_irqrestore(&undef_lock, flags);
 }
 
 void unregister_undef_hook(struct undef_hook *hook)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&undef_lock, flags);
+       raw_spin_lock_irqsave(&undef_lock, flags);
        list_del(&hook->node);
-       spin_unlock_irqrestore(&undef_lock, flags);
+       raw_spin_unlock_irqrestore(&undef_lock, flags);
 }
 
 static int call_undef_hook(struct pt_regs *regs, unsigned int instr)
@@ -328,12 +328,12 @@ static int call_undef_hook(struct pt_regs *regs, unsigned int instr)
        unsigned long flags;
        int (*fn)(struct pt_regs *regs, unsigned int instr) = NULL;
 
-       spin_lock_irqsave(&undef_lock, flags);
+       raw_spin_lock_irqsave(&undef_lock, flags);
        list_for_each_entry(hook, &undef_hook, node)
                if ((instr & hook->instr_mask) == hook->instr_val &&
                    (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val)
                        fn = hook->fn;
-       spin_unlock_irqrestore(&undef_lock, flags);
+       raw_spin_unlock_irqrestore(&undef_lock, flags);
 
        return fn ? fn(regs, instr) : 1;
 }

diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
index 15d5498..e3d6cca 100644 (file)
--- a/arch/arm/mach-footbridge/include/mach/hardware.h
+++ b/arch/arm/mach-footbridge/include/mach/hardware.h
@@ -93,7 +93,7 @@
 #define CPLD_FLASH_WR_ENABLE   1
 
 #ifndef __ASSEMBLY__
-extern spinlock_t nw_gpio_lock;
+extern raw_spinlock_t nw_gpio_lock;
 extern void nw_gpio_modify_op(unsigned int mask, unsigned int set);
 extern void nw_gpio_modify_io(unsigned int mask, unsigned int in);
 extern unsigned int nw_gpio_read(void);

diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 06e514f..5b73190 100644 (file)
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -68,7 +68,7 @@ static inline void wb977_ww(int reg, int val)
 /*
  * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE
  */
-DEFINE_SPINLOCK(nw_gpio_lock);
+DEFINE_RAW_SPINLOCK(nw_gpio_lock);
 EXPORT_SYMBOL(nw_gpio_lock);
 
 static unsigned int current_gpio_op;
@@ -327,9 +327,9 @@ static inline void wb977_init_gpio(void)
        /*
         * Set Group1/Group2 outputs
         */
-       spin_lock_irqsave(&nw_gpio_lock, flags);
+       raw_spin_lock_irqsave(&nw_gpio_lock, flags);
        nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN);
-       spin_unlock_irqrestore(&nw_gpio_lock, flags);
+       raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 /*
@@ -390,9 +390,9 @@ static void __init cpld_init(void)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&nw_gpio_lock, flags);
+       raw_spin_lock_irqsave(&nw_gpio_lock, flags);
        nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE);
-       spin_unlock_irqrestore(&nw_gpio_lock, flags);
+       raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 static unsigned char rwa_unlock[] __initdata =
@@ -616,9 +616,9 @@ static int __init nw_hw_init(void)
                cpld_init();
                rwa010_init();
 
-               spin_lock_irqsave(&nw_gpio_lock, flags);
+               raw_spin_lock_irqsave(&nw_gpio_lock, flags);
                nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
-               spin_unlock_irqrestore(&nw_gpio_lock, flags);
+               raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
        }
        return 0;
 }

diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
index 00269fe..e57102e 100644 (file)
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ b/arch/arm/mach-footbridge/netwinder-leds.c
@@ -31,13 +31,13 @@
 static char led_state;
 static char hw_led_state;
 
-static DEFINE_SPINLOCK(leds_lock);
+static DEFINE_RAW_SPINLOCK(leds_lock);
 
 static void netwinder_leds_event(led_event_t evt)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&leds_lock, flags);
+       raw_spin_lock_irqsave(&leds_lock, flags);
 
        switch (evt) {
        case led_start:
@@ -117,12 +117,12 @@ static void netwinder_leds_event(led_event_t evt)
                break;
        }
 
-       spin_unlock_irqrestore(&leds_lock, flags);
+       raw_spin_unlock_irqrestore(&leds_lock, flags);
 
        if  (led_state & LED_STATE_ENABLED) {
-               spin_lock_irqsave(&nw_gpio_lock, flags);
+               raw_spin_lock_irqsave(&nw_gpio_lock, flags);
                nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
-               spin_unlock_irqrestore(&nw_gpio_lock, flags);
+               raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
        }
 }
 

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 77315b9..0c20cf6 100644 (file)
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -205,7 +205,7 @@ static struct amba_pl010_data integrator_uart_data = {
 
 #define CM_CTRL        IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 
-static DEFINE_SPINLOCK(cm_lock);
+static DEFINE_RAW_SPINLOCK(cm_lock);
 
 /**
  * cm_control - update the CM_CTRL register.
@@ -217,10 +217,10 @@ void cm_control(u32 mask, u32 set)
        unsigned long flags;
        u32 val;
 
-       spin_lock_irqsave(&cm_lock, flags);
+       raw_spin_lock_irqsave(&cm_lock, flags);
        val = readl(CM_CTRL) & ~mask;
        writel(val | set, CM_CTRL);
-       spin_unlock_irqrestore(&cm_lock, flags);
+       raw_spin_unlock_irqrestore(&cm_lock, flags);
 }
 
 EXPORT_SYMBOL(cm_control);

diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index dd56bfb..56c3062 100644 (file)
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -164,7 +164,7 @@
  *      7:2    register number
  *  
  */
-static DEFINE_SPINLOCK(v3_lock);
+static DEFINE_RAW_SPINLOCK(v3_lock);
 
 #define PCI_BUS_NONMEM_START   0x00000000
 #define PCI_BUS_NONMEM_SIZE    SZ_256M
@@ -285,7 +285,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
        unsigned long flags;
        u32 v;
 
-       spin_lock_irqsave(&v3_lock, flags);
+       raw_spin_lock_irqsave(&v3_lock, flags);
        addr = v3_open_config_window(bus, devfn, where);
 
        switch (size) {
@@ -303,7 +303,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
        }
 
        v3_close_config_window();
-       spin_unlock_irqrestore(&v3_lock, flags);
+       raw_spin_unlock_irqrestore(&v3_lock, flags);
 
        *val = v;
        return PCIBIOS_SUCCESSFUL;
@@ -315,7 +315,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        unsigned long addr;
        unsigned long flags;
 
-       spin_lock_irqsave(&v3_lock, flags);
+       raw_spin_lock_irqsave(&v3_lock, flags);
        addr = v3_open_config_window(bus, devfn, where);
 
        switch (size) {
@@ -336,7 +336,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        }
 
        v3_close_config_window();
-       spin_unlock_irqrestore(&v3_lock, flags);
+       raw_spin_unlock_irqrestore(&v3_lock, flags);
 
        return PCIBIOS_SUCCESSFUL;
 }
@@ -515,7 +515,7 @@ void __init pci_v3_preinit(void)
        hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
        hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
 
-       spin_lock_irqsave(&v3_lock, flags);
+       raw_spin_lock_irqsave(&v3_lock, flags);
 
        /*
         * Unlock V3 registers, but only if they were previously locked.
@@ -588,7 +588,7 @@ void __init pci_v3_preinit(void)
                printk(KERN_ERR "PCI: unable to grab PCI error "
                       "interrupt: %d\n", ret);
 
-       spin_unlock_irqrestore(&v3_lock, flags);
+       raw_spin_unlock_irqrestore(&v3_lock, flags);
 }
 
 void __init pci_v3_postinit(void)

diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 2131832..1b5fe87 100644 (file)
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -54,7 +54,7 @@ unsigned long ixp4xx_pci_reg_base = 0;
  * these transactions are atomic or we will end up
  * with corrupt data on the bus or in a driver.
  */
-static DEFINE_SPINLOCK(ixp4xx_pci_lock);
+static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
 
 /*
  * Read from PCI config space
@@ -62,10 +62,10 @@ static DEFINE_SPINLOCK(ixp4xx_pci_lock);
 static void crp_read(u32 ad_cbe, u32 *data)
 {
        unsigned long flags;
-       spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+       raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
        *PCI_CRP_AD_CBE = ad_cbe;
        *data = *PCI_CRP_RDATA;
-       spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+       raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 }
 
 /*
@@ -74,10 +74,10 @@ static void crp_read(u32 ad_cbe, u32 *data)
 static void crp_write(u32 ad_cbe, u32 data)
 { 
        unsigned long flags;
-       spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+       raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
        *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
        *PCI_CRP_WDATA = data;
-       spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+       raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 }
 
 static inline int check_master_abort(void)
@@ -101,7 +101,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
        int retval = 0;
        int i;
 
-       spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+       raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 
        *PCI_NP_AD = addr;
 
@@ -118,7 +118,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
        if(check_master_abort())
                retval = 1;
 
-       spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+       raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
        return retval;
 }
 
@@ -127,7 +127,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
        unsigned long flags;
        int retval = 0;
 
-       spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+       raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 
        *PCI_NP_AD = addr;
 
@@ -140,7 +140,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
        if(check_master_abort())
                retval = 1;
 
-       spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+       raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
        return retval;
 }
 
@@ -149,7 +149,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
        unsigned long flags;
        int retval = 0;
 
-       spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+       raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 
        *PCI_NP_AD = addr;
 
@@ -162,7 +162,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
        if(check_master_abort())
                retval = 1;
 
-       spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+       raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
        return retval;
 }
 

diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index c9e32de..ccd4918 100644 (file)
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -36,7 +36,7 @@ static char led_state;
 static short hw_led_state;
 static short saved_state;
 
-static DEFINE_SPINLOCK(leds_lock);
+static DEFINE_RAW_SPINLOCK(leds_lock);
 
 short sequoia_read(int addr) {
   outw(addr,0x24);
@@ -52,7 +52,7 @@ static void sequoia_leds_event(led_event_t evt)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&leds_lock, flags);
+       raw_spin_lock_irqsave(&leds_lock, flags);
 
        hw_led_state = sequoia_read(0x09);
 
@@ -144,7 +144,7 @@ static void sequoia_leds_event(led_event_t evt)
        if  (led_state & LED_STATE_ENABLED)
                sequoia_write(hw_led_state,0x09);
 
-       spin_unlock_irqrestore(&leds_lock, flags);
+       raw_spin_unlock_irqrestore(&leds_lock, flags);
 }
 
 static int __init leds_init(void)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9ecfdb5..3255c51 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -26,7 +26,7 @@
 #define CACHE_LINE_SIZE                32
 
 static void __iomem *l2x0_base;
-static DEFINE_SPINLOCK(l2x0_lock);
+static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static uint32_t l2x0_way_mask; /* Bitmask of active ways */
 static uint32_t l2x0_size;
 
@@ -115,9 +115,9 @@ static void l2x0_cache_sync(void)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void __l2x0_flush_all(void)
@@ -134,9 +134,9 @@ static void l2x0_flush_all(void)
        unsigned long flags;
 
        /* clean all ways */
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        __l2x0_flush_all();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_all(void)
@@ -144,11 +144,11 @@ static void l2x0_clean_all(void)
        unsigned long flags;
 
        /* clean all ways */
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
        cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_all(void)
@@ -156,13 +156,13 @@ static void l2x0_inv_all(void)
        unsigned long flags;
 
        /* invalidate all ways */
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        /* Invalidating when L2 is enabled is a nono */
        BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
        cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_range(unsigned long start, unsigned long end)
@@ -170,7 +170,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
        void __iomem *base = l2x0_base;
        unsigned long flags;
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        if (start & (CACHE_LINE_SIZE - 1)) {
                start &= ~(CACHE_LINE_SIZE - 1);
                debug_writel(0x03);
@@ -195,13 +195,13 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
                }
 
                if (blk_end < end) {
-                       spin_unlock_irqrestore(&l2x0_lock, flags);
-                       spin_lock_irqsave(&l2x0_lock, flags);
+                       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                       raw_spin_lock_irqsave(&l2x0_lock, flags);
                }
        }
        cache_wait(base + L2X0_INV_LINE_PA, 1);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_range(unsigned long start, unsigned long end)
@@ -214,7 +214,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                return;
        }
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
                unsigned long blk_end = start + min(end - start, 4096UL);
@@ -225,13 +225,13 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                }
 
                if (blk_end < end) {
-                       spin_unlock_irqrestore(&l2x0_lock, flags);
-                       spin_lock_irqsave(&l2x0_lock, flags);
+                       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                       raw_spin_lock_irqsave(&l2x0_lock, flags);
                }
        }
        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_flush_range(unsigned long start, unsigned long end)
@@ -244,7 +244,7 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
                return;
        }
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
                unsigned long blk_end = start + min(end - start, 4096UL);
@@ -257,24 +257,24 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
                debug_writel(0x00);
 
                if (blk_end < end) {
-                       spin_unlock_irqrestore(&l2x0_lock, flags);
-                       spin_lock_irqsave(&l2x0_lock, flags);
+                       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                       raw_spin_lock_irqsave(&l2x0_lock, flags);
                }
        }
        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_disable(void)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        __l2x0_flush_all();
        writel_relaxed(0, l2x0_base + L2X0_CTRL);
        dsb();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void __init l2x0_unlock(__u32 cache_id)

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index b0ee9ba..93aac06 100644 (file)
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -16,7 +16,7 @@
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
 
-static DEFINE_SPINLOCK(cpu_asid_lock);
+static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 #ifdef CONFIG_SMP
 DEFINE_PER_CPU(struct mm_struct *, current_mm);
@@ -31,7 +31,7 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
        mm->context.id = 0;
-       spin_lock_init(&mm->context.id_lock);
+       raw_spin_lock_init(&mm->context.id_lock);
 }
 
 static void flush_context(void)
@@ -58,7 +58,7 @@ static void set_mm_context(struct mm_struct *mm, unsigned int asid)
         * the broadcast. This function is also called via IPI so the
         * mm->context.id_lock has to be IRQ-safe.
         */
-       spin_lock_irqsave(&mm->context.id_lock, flags);
+       raw_spin_lock_irqsave(&mm->context.id_lock, flags);
        if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
                /*
                 * Old version of ASID found. Set the new one and
@@ -67,7 +67,7 @@ static void set_mm_context(struct mm_struct *mm, unsigned int asid)
                mm->context.id = asid;
                cpumask_clear(mm_cpumask(mm));
        }
-       spin_unlock_irqrestore(&mm->context.id_lock, flags);
+       raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
 
        /*
         * Set the mm_cpumask(mm) bit for the current CPU.
@@ -117,7 +117,7 @@ void __new_context(struct mm_struct *mm)
 {
        unsigned int asid;
 
-       spin_lock(&cpu_asid_lock);
+       raw_spin_lock(&cpu_asid_lock);
 #ifdef CONFIG_SMP
        /*
         * Check the ASID again, in case the change was broadcast from
@@ -125,7 +125,7 @@ void __new_context(struct mm_struct *mm)
         */
        if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
                cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
-               spin_unlock(&cpu_asid_lock);
+               raw_spin_unlock(&cpu_asid_lock);
                return;
        }
 #endif
@@ -153,5 +153,5 @@ void __new_context(struct mm_struct *mm)
        }
 
        set_mm_context(mm, asid);
-       spin_unlock(&cpu_asid_lock);
+       raw_spin_unlock(&cpu_asid_lock);
 }

diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index b806151..7d0a8c2 100644 (file)
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -30,7 +30,7 @@
 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
                                  L_PTE_MT_MINICACHE)
 
-static DEFINE_SPINLOCK(minicache_lock);
+static DEFINE_RAW_SPINLOCK(minicache_lock);
 
 /*
  * ARMv4 mini-dcache optimised copy_user_highpage
@@ -76,14 +76,14 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                __flush_dcache_page(page_mapping(from), from);
 
-       spin_lock(&minicache_lock);
+       raw_spin_lock(&minicache_lock);
 
        set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(page_to_pfn(from), minicache_pgprot), 0);
        flush_tlb_kernel_page(0xffff8000);
 
        mc_copy_user_page((void *)0xffff8000, kto);
 
-       spin_unlock(&minicache_lock);
+       raw_spin_unlock(&minicache_lock);
 
        kunmap_atomic(kto, KM_USER1);
 }

diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 63cca00..3d9a155 100644 (file)
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -27,7 +27,7 @@
 #define from_address   (0xffff8000)
 #define to_address     (0xffffc000)
 
-static DEFINE_SPINLOCK(v6_lock);
+static DEFINE_RAW_SPINLOCK(v6_lock);
 
 /*
  * Copy the user page.  No aliasing to deal with so we can just
@@ -88,7 +88,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
         * Now copy the page using the same cache colour as the
         * pages ultimate destination.
         */
-       spin_lock(&v6_lock);
+       raw_spin_lock(&v6_lock);
 
        set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(page_to_pfn(from), PAGE_KERNEL), 0);
        set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(to), PAGE_KERNEL), 0);
@@ -101,7 +101,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 
        copy_page((void *)kto, (void *)kfrom);
 
-       spin_unlock(&v6_lock);
+       raw_spin_unlock(&v6_lock);
 }
 
 /*
@@ -121,13 +121,13 @@ static void v6_clear_user_highpage_aliasing(struct page *page, unsigned long vad
         * Now clear the page using the same cache colour as
         * the pages ultimate destination.
         */
-       spin_lock(&v6_lock);
+       raw_spin_lock(&v6_lock);
 
        set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(page), PAGE_KERNEL), 0);
        flush_tlb_kernel_page(to);
        clear_page((void *)to);
 
-       spin_unlock(&v6_lock);
+       raw_spin_unlock(&v6_lock);
 }
 
 struct cpu_user_fns v6_user_fns __initdata = {

diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 649bbcd..610c24c 100644 (file)
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -32,7 +32,7 @@
 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
                                  L_PTE_MT_MINICACHE)
 
-static DEFINE_SPINLOCK(minicache_lock);
+static DEFINE_RAW_SPINLOCK(minicache_lock);
 
 /*
  * XScale mini-dcache optimised copy_user_highpage
@@ -98,14 +98,14 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                __flush_dcache_page(page_mapping(from), from);
 
-       spin_lock(&minicache_lock);
+       raw_spin_lock(&minicache_lock);
 
        set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(page_to_pfn(from), minicache_pgprot), 0);
        flush_tlb_kernel_page(COPYPAGE_MINICACHE);
 
        mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
 
-       spin_unlock(&minicache_lock);
+       raw_spin_unlock(&minicache_lock);
 
        kunmap_atomic(kto, KM_USER1);
 }