drm/i915: Add MIPI mmio reg base

This patch adds a mmio base address variable for DSI display,
to make the DSI code generic, so that, if required, the same code
can be re-used for future platforms with different mmio base.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Appease checkpatch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0fd2c1..c9231f2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1360,6 +1360,9 @@ struct drm_i915_private {
         */
        uint32_t gpio_mmio_base;
 
+       /* MMIO base address for MIPI regs */
+       uint32_t mipi_mmio_base;
+
        wait_queue_head_t gmbus_wait_queue;
 
        struct pci_dev *bridge_dev;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d437d1..2a4aac4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1032,6 +1032,7 @@ enum punit_power_well {
 #define   GFX_PPGTT_ENABLE             (1<<9)
 
 #define VLV_DISPLAY_BASE 0x180000
+#define VLV_MIPI_BASE VLV_DISPLAY_BASE
 
 #define VLV_GU_CTL0    (VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1    (VLV_DISPLAY_BASE + 0x2034)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8d357cc..2525cdd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -649,6 +649,7 @@ bool intel_dsi_init(struct drm_device *dev)
        struct intel_connector *intel_connector;
        struct drm_connector *connector;
        struct drm_display_mode *fixed_mode = NULL;
+       struct drm_i915_private *dev_priv = dev->dev_private;
        const struct intel_dsi_device *dsi;
        unsigned int i;
 
@@ -668,6 +669,13 @@ bool intel_dsi_init(struct drm_device *dev)
        encoder = &intel_encoder->base;
        intel_dsi->attached_connector = intel_connector;
 
+       if (IS_VALLEYVIEW(dev)) {
+               dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+       } else {
+               DRM_ERROR("Unsupported Mipi device to reg base");
+               return false;
+       }
+
        connector = &intel_connector->base;
 
        drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);