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[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
authorPavel Pisa <ppisa@pikron.com>
Wed, 7 Mar 2007 22:56:16 +0000 (23:56 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 12 Mar 2007 16:49:35 +0000 (16:49 +0000)
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

No differences found
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